1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCTargetDesc.h" 10 #include "TargetInfo/PowerPCTargetInfo.h" 11 #include "llvm/MC/MCDecoderOps.h" 12 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/MC/TargetRegistry.h" 16 #include "llvm/Support/Endian.h" 17 18 using namespace llvm; 19 20 DEFINE_PPC_REGCLASSES 21 22 #define DEBUG_TYPE "ppc-disassembler" 23 24 typedef MCDisassembler::DecodeStatus DecodeStatus; 25 26 namespace { 27 class PPCDisassembler : public MCDisassembler { 28 bool IsLittleEndian; 29 30 public: 31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 32 bool IsLittleEndian) 33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 34 35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 36 ArrayRef<uint8_t> Bytes, uint64_t Address, 37 raw_ostream &CStream) const override; 38 }; 39 } // end anonymous namespace 40 41 static MCDisassembler *createPPCDisassembler(const Target &T, 42 const MCSubtargetInfo &STI, 43 MCContext &Ctx) { 44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 45 } 46 47 static MCDisassembler *createPPCLEDisassembler(const Target &T, 48 const MCSubtargetInfo &STI, 49 MCContext &Ctx) { 50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 51 } 52 53 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() { 54 // Register the disassembler for each target. 55 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), 56 createPPCDisassembler); 57 TargetRegistry::RegisterMCDisassembler(getThePPC32LETarget(), 58 createPPCLEDisassembler); 59 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), 60 createPPCDisassembler); 61 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), 62 createPPCLEDisassembler); 63 } 64 65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, 66 uint64_t /*Address*/, 67 const MCDisassembler * /*Decoder*/) { 68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm))); 69 return MCDisassembler::Success; 70 } 71 72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, 73 uint64_t /*Address*/, 74 const MCDisassembler * /*Decoder*/) { 75 int32_t Offset = SignExtend32<24>(Imm); 76 Inst.addOperand(MCOperand::createImm(Offset)); 77 return MCDisassembler::Success; 78 } 79 80 // FIXME: These can be generated by TableGen from the existing register 81 // encoding values! 82 83 template <std::size_t N> 84 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 85 const MCPhysReg (&Regs)[N]) { 86 assert(RegNo < N && "Invalid register number"); 87 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 88 return MCDisassembler::Success; 89 } 90 91 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 92 uint64_t Address, 93 const MCDisassembler *Decoder) { 94 return decodeRegisterClass(Inst, RegNo, CRRegs); 95 } 96 97 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 98 uint64_t Address, 99 const MCDisassembler *Decoder) { 100 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 101 } 102 103 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 104 uint64_t Address, 105 const MCDisassembler *Decoder) { 106 return decodeRegisterClass(Inst, RegNo, FRegs); 107 } 108 109 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 110 uint64_t Address, 111 const MCDisassembler *Decoder) { 112 return decodeRegisterClass(Inst, RegNo, FRegs); 113 } 114 115 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 116 uint64_t Address, 117 const MCDisassembler *Decoder) { 118 return decodeRegisterClass(Inst, RegNo, VFRegs); 119 } 120 121 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 122 uint64_t Address, 123 const MCDisassembler *Decoder) { 124 return decodeRegisterClass(Inst, RegNo, VRegs); 125 } 126 127 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 128 uint64_t Address, 129 const MCDisassembler *Decoder) { 130 return decodeRegisterClass(Inst, RegNo, VSRegs); 131 } 132 133 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 134 uint64_t Address, 135 const MCDisassembler *Decoder) { 136 return decodeRegisterClass(Inst, RegNo, VSFRegs); 137 } 138 139 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 140 uint64_t Address, 141 const MCDisassembler *Decoder) { 142 return decodeRegisterClass(Inst, RegNo, VSSRegs); 143 } 144 145 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 146 uint64_t Address, 147 const MCDisassembler *Decoder) { 148 return decodeRegisterClass(Inst, RegNo, RRegs); 149 } 150 151 static DecodeStatus 152 DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, 153 const MCDisassembler *Decoder) { 154 return decodeRegisterClass(Inst, RegNo, RRegsNoR0); 155 } 156 157 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 158 uint64_t Address, 159 const MCDisassembler *Decoder) { 160 return decodeRegisterClass(Inst, RegNo, XRegs); 161 } 162 163 static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, 164 uint64_t Address, 165 const MCDisassembler *Decoder) { 166 return decodeRegisterClass(Inst, RegNo, XRegs); 167 } 168 169 static DecodeStatus 170 DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, 171 const MCDisassembler *Decoder) { 172 return decodeRegisterClass(Inst, RegNo, XRegsNoX0); 173 } 174 175 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 176 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 177 178 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, 179 uint64_t Address, 180 const MCDisassembler *Decoder) { 181 return decodeRegisterClass(Inst, RegNo, SPERegs); 182 } 183 184 static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, 185 uint64_t Address, 186 const MCDisassembler *Decoder) { 187 return decodeRegisterClass(Inst, RegNo, ACCRegs); 188 } 189 190 static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, 191 uint64_t Address, 192 const void *Decoder) { 193 return decodeRegisterClass(Inst, RegNo, WACCRegs); 194 } 195 196 static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo, 197 uint64_t Address, 198 const void *Decoder) { 199 return decodeRegisterClass(Inst, RegNo, WACC_HIRegs); 200 } 201 202 // TODO: Make this function static when the register class is used by a new 203 // instruction. 204 DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo, 205 uint64_t Address, 206 const void *Decoder) { 207 return decodeRegisterClass(Inst, RegNo, DMRROWRegs); 208 } 209 210 static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo, 211 uint64_t Address, 212 const void *Decoder) { 213 return decodeRegisterClass(Inst, RegNo, DMRROWpRegs); 214 } 215 216 static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 217 uint64_t Address, 218 const void *Decoder) { 219 return decodeRegisterClass(Inst, RegNo, DMRRegs); 220 } 221 222 // TODO: Make this function static when the register class is used by a new 223 // instruction. 224 DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, 225 uint64_t Address, const void *Decoder) { 226 return decodeRegisterClass(Inst, RegNo, DMRpRegs); 227 } 228 229 static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, 230 uint64_t Address, 231 const MCDisassembler *Decoder) { 232 return decodeRegisterClass(Inst, RegNo, VSRpRegs); 233 } 234 235 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 236 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 237 238 template <unsigned N> 239 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 240 int64_t Address, 241 const MCDisassembler *Decoder) { 242 assert(isUInt<N>(Imm) && "Invalid immediate"); 243 Inst.addOperand(MCOperand::createImm(Imm)); 244 return MCDisassembler::Success; 245 } 246 247 template <unsigned N> 248 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 249 int64_t Address, 250 const MCDisassembler *Decoder) { 251 assert(isUInt<N>(Imm) && "Invalid immediate"); 252 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 253 return MCDisassembler::Success; 254 } 255 256 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, 257 int64_t Address, 258 const MCDisassembler *Decoder) { 259 if (Imm != 0) 260 return MCDisassembler::Fail; 261 Inst.addOperand(MCOperand::createImm(Imm)); 262 return MCDisassembler::Success; 263 } 264 265 static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, 266 uint64_t Address, 267 const MCDisassembler *Decoder) { 268 if (RegNo & 1) 269 return MCDisassembler::Fail; 270 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1])); 271 return MCDisassembler::Success; 272 } 273 274 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 275 int64_t Address, 276 const MCDisassembler *Decoder) { 277 // Decode the memri field (imm, reg), which has the low 16-bits as the 278 // displacement and the next 5 bits as the register #. 279 280 uint64_t Base = Imm >> 16; 281 uint64_t Disp = Imm & 0xFFFF; 282 283 assert(Base < 32 && "Invalid base register"); 284 285 switch (Inst.getOpcode()) { 286 default: break; 287 case PPC::LBZU: 288 case PPC::LHAU: 289 case PPC::LHZU: 290 case PPC::LWZU: 291 case PPC::LFSU: 292 case PPC::LFDU: 293 // Add the tied output operand. 294 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 295 break; 296 case PPC::STBU: 297 case PPC::STHU: 298 case PPC::STWU: 299 case PPC::STFSU: 300 case PPC::STFDU: 301 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 302 break; 303 } 304 305 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 306 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 307 return MCDisassembler::Success; 308 } 309 310 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 311 int64_t Address, 312 const MCDisassembler *Decoder) { 313 // Decode the memrix field (imm, reg), which has the low 14-bits as the 314 // displacement and the next 5 bits as the register #. 315 316 uint64_t Base = Imm >> 14; 317 uint64_t Disp = Imm & 0x3FFF; 318 319 assert(Base < 32 && "Invalid base register"); 320 321 if (Inst.getOpcode() == PPC::LDU) 322 // Add the tied output operand. 323 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 324 else if (Inst.getOpcode() == PPC::STDU) 325 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 326 327 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 328 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 329 return MCDisassembler::Success; 330 } 331 332 static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm, 333 int64_t Address, 334 const MCDisassembler *Decoder) { 335 // Decode the memrix field for a hash store or hash check operation. 336 // The field is composed of a register and an immediate value that is 6 bits 337 // and covers the range -8 to -512. The immediate is always negative and 2s 338 // complement which is why we sign extend a 7 bit value. 339 const uint64_t Base = Imm >> 6; 340 const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8; 341 342 assert(Base < 32 && "Invalid base register"); 343 344 Inst.addOperand(MCOperand::createImm(Disp)); 345 Inst.addOperand(MCOperand::createReg(RRegs[Base])); 346 return MCDisassembler::Success; 347 } 348 349 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 350 int64_t Address, 351 const MCDisassembler *Decoder) { 352 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 353 // displacement with 16-byte aligned, and the next 5 bits as the register #. 354 355 uint64_t Base = Imm >> 12; 356 uint64_t Disp = Imm & 0xFFF; 357 358 assert(Base < 32 && "Invalid base register"); 359 360 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 361 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 362 return MCDisassembler::Success; 363 } 364 365 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm, 366 int64_t Address, 367 const MCDisassembler *Decoder) { 368 // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the 369 // displacement, and the next 5 bits as an immediate 0. 370 uint64_t Base = Imm >> 34; 371 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 372 373 assert(Base < 32 && "Invalid base register"); 374 375 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 376 return decodeImmZeroOperand(Inst, Base, Address, Decoder); 377 } 378 379 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm, 380 int64_t Address, 381 const MCDisassembler *Decoder) { 382 // Decode the memri34 field (imm, reg), which has the low 34-bits as the 383 // displacement, and the next 5 bits as the register #. 384 uint64_t Base = Imm >> 34; 385 uint64_t Disp = Imm & 0x3FFFFFFFFUL; 386 387 assert(Base < 32 && "Invalid base register"); 388 389 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp))); 390 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 391 return MCDisassembler::Success; 392 } 393 394 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, 395 int64_t Address, 396 const MCDisassembler *Decoder) { 397 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the 398 // displacement with 8-byte aligned, and the next 5 bits as the register #. 399 400 uint64_t Base = Imm >> 5; 401 uint64_t Disp = Imm & 0x1F; 402 403 assert(Base < 32 && "Invalid base register"); 404 405 Inst.addOperand(MCOperand::createImm(Disp << 3)); 406 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 407 return MCDisassembler::Success; 408 } 409 410 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, 411 int64_t Address, 412 const MCDisassembler *Decoder) { 413 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the 414 // displacement with 4-byte aligned, and the next 5 bits as the register #. 415 416 uint64_t Base = Imm >> 5; 417 uint64_t Disp = Imm & 0x1F; 418 419 assert(Base < 32 && "Invalid base register"); 420 421 Inst.addOperand(MCOperand::createImm(Disp << 2)); 422 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 423 return MCDisassembler::Success; 424 } 425 426 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, 427 int64_t Address, 428 const MCDisassembler *Decoder) { 429 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the 430 // displacement with 2-byte aligned, and the next 5 bits as the register #. 431 432 uint64_t Base = Imm >> 5; 433 uint64_t Disp = Imm & 0x1F; 434 435 assert(Base < 32 && "Invalid base register"); 436 437 Inst.addOperand(MCOperand::createImm(Disp << 1)); 438 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 439 return MCDisassembler::Success; 440 } 441 442 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 443 int64_t Address, 444 const MCDisassembler *Decoder) { 445 // The cr bit encoding is 0x80 >> cr_reg_num. 446 447 unsigned Zeros = countTrailingZeros(Imm); 448 assert(Zeros < 8 && "Invalid CR bit value"); 449 450 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 451 return MCDisassembler::Success; 452 } 453 454 #include "PPCGenDisassemblerTables.inc" 455 456 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 457 ArrayRef<uint8_t> Bytes, 458 uint64_t Address, 459 raw_ostream &CS) const { 460 auto *ReadFunc = IsLittleEndian ? support::endian::read32le 461 : support::endian::read32be; 462 463 // If this is an 8-byte prefixed instruction, handle it here. 464 // Note: prefixed instructions aren't technically 8-byte entities - the prefix 465 // appears in memory at an address 4 bytes prior to that of the base 466 // instruction regardless of endianness. So we read the two pieces and 467 // rebuild the 8-byte instruction. 468 // TODO: In this function we call decodeInstruction several times with 469 // different decoder tables. It may be possible to only call once by 470 // looking at the top 6 bits of the instruction. 471 if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) { 472 uint32_t Prefix = ReadFunc(Bytes.data()); 473 uint32_t BaseInst = ReadFunc(Bytes.data() + 4); 474 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32; 475 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address, 476 this, STI); 477 if (result != MCDisassembler::Fail) { 478 Size = 8; 479 return result; 480 } 481 } 482 483 // Get the four bytes of the instruction. 484 Size = 4; 485 if (Bytes.size() < 4) { 486 Size = 0; 487 return MCDisassembler::Fail; 488 } 489 490 // Read the instruction in the proper endianness. 491 uint64_t Inst = ReadFunc(Bytes.data()); 492 493 if (STI.getFeatureBits()[PPC::FeatureSPE]) { 494 DecodeStatus result = 495 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI); 496 if (result != MCDisassembler::Fail) 497 return result; 498 } 499 500 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 501 } 502