1 //===-- PPCMCCodeEmitter.h - Convert PPC code to machine code -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the PPCMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_PPC_MCCODEEMITTER_PPCCODEEMITTER_H 14 #define LLVM_LIB_TARGET_PPC_MCCODEEMITTER_PPCCODEEMITTER_H 15 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCCodeEmitter.h" 18 #include "llvm/MC/MCSubtargetInfo.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCInst.h" 22 23 namespace llvm { 24 25 class PPCMCCodeEmitter : public MCCodeEmitter { 26 const MCInstrInfo &MCII; 27 const MCContext &CTX; 28 bool IsLittleEndian; 29 30 public: 31 PPCMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 32 : MCII(mcii), CTX(ctx), 33 IsLittleEndian(ctx.getAsmInfo()->isLittleEndian()) {} 34 PPCMCCodeEmitter(const PPCMCCodeEmitter &) = delete; 35 void operator=(const PPCMCCodeEmitter &) = delete; 36 ~PPCMCCodeEmitter() override = default; 37 38 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 39 SmallVectorImpl<MCFixup> &Fixups, 40 const MCSubtargetInfo &STI) const; 41 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 42 SmallVectorImpl<MCFixup> &Fixups, 43 const MCSubtargetInfo &STI) const; 44 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 45 SmallVectorImpl<MCFixup> &Fixups, 46 const MCSubtargetInfo &STI) const; 47 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 48 SmallVectorImpl<MCFixup> &Fixups, 49 const MCSubtargetInfo &STI) const; 50 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 51 SmallVectorImpl<MCFixup> &Fixups, 52 const MCSubtargetInfo &STI) const; 53 uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo, 54 SmallVectorImpl<MCFixup> &Fixups, 55 const MCSubtargetInfo &STI, 56 MCFixupKind Fixup) const; 57 uint64_t getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo, 58 SmallVectorImpl<MCFixup> &Fixups, 59 const MCSubtargetInfo &STI) const; 60 uint64_t getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 unsigned getDispRIEncoding(const MCInst &MI, unsigned OpNo, 64 SmallVectorImpl<MCFixup> &Fixups, 65 const MCSubtargetInfo &STI) const; 66 unsigned getDispRIXEncoding(const MCInst &MI, unsigned OpNo, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 unsigned getDispRIX16Encoding(const MCInst &MI, unsigned OpNo, 70 SmallVectorImpl<MCFixup> &Fixups, 71 const MCSubtargetInfo &STI) const; 72 unsigned getDispRIHashEncoding(const MCInst &MI, unsigned OpNo, 73 SmallVectorImpl<MCFixup> &Fixups, 74 const MCSubtargetInfo &STI) const; 75 uint64_t getDispRI34PCRelEncoding(const MCInst &MI, unsigned OpNo, 76 SmallVectorImpl<MCFixup> &Fixups, 77 const MCSubtargetInfo &STI) const; 78 uint64_t getDispRI34Encoding(const MCInst &MI, unsigned OpNo, 79 SmallVectorImpl<MCFixup> &Fixups, 80 const MCSubtargetInfo &STI) const; 81 unsigned getDispSPE8Encoding(const MCInst &MI, unsigned OpNo, 82 SmallVectorImpl<MCFixup> &Fixups, 83 const MCSubtargetInfo &STI) const; 84 unsigned getDispSPE4Encoding(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups, 86 const MCSubtargetInfo &STI) const; 87 unsigned getDispSPE2Encoding(const MCInst &MI, unsigned OpNo, 88 SmallVectorImpl<MCFixup> &Fixups, 89 const MCSubtargetInfo &STI) const; 90 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 91 SmallVectorImpl<MCFixup> &Fixups, 92 const MCSubtargetInfo &STI) const; 93 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 94 SmallVectorImpl<MCFixup> &Fixups, 95 const MCSubtargetInfo &STI) const; 96 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, 97 SmallVectorImpl<MCFixup> &Fixups, 98 const MCSubtargetInfo &STI) const; 99 unsigned getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo, 100 SmallVectorImpl<MCFixup> &Fixups, 101 const MCSubtargetInfo &STI) const; 102 103 /// getMachineOpValue - Return binary encoding of operand. If the machine 104 /// operand requires relocation, record the relocation and return zero. 105 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 106 SmallVectorImpl<MCFixup> &Fixups, 107 const MCSubtargetInfo &STI) const; 108 109 // getBinaryCodeForInstr - TableGen'erated function for getting the 110 // binary encoding for an instruction. 111 uint64_t getBinaryCodeForInstr(const MCInst &MI, 112 SmallVectorImpl<MCFixup> &Fixups, 113 const MCSubtargetInfo &STI) const; 114 115 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB, 116 SmallVectorImpl<MCFixup> &Fixups, 117 const MCSubtargetInfo &STI) const override; 118 119 // Get the number of bytes used to encode the given MCInst. 120 unsigned getInstSizeInBytes(const MCInst &MI) const; 121 122 // Is this instruction a prefixed instruction. 123 bool isPrefixedInstruction(const MCInst &MI) const; 124 }; 125 126 } // namespace llvm 127 128 #endif // LLVM_LIB_TARGET_PPC_MCCODEEMITTER_PPCCODEEMITTER_H 129