1//===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the itinerary class data for the POWER9 processor.
10//
11//===----------------------------------------------------------------------===//
12def P9Model : SchedMachineModel {
13  // The maximum number of instructions to be issued at the same time.
14  // While a value of 8 is technically correct since 8 instructions can be
15  // fetched from the instruction cache. However, only 6 instructions may be
16  // actually dispatched at a time.
17  let IssueWidth = 8;
18
19  // Load latency is 4 or 5 cycles depending on the load. This latency assumes
20  // that we have a cache hit. For a cache miss the load latency will be more.
21  // There are two instructions (lxvl, lxvll) that have a latency of 6 cycles.
22  // However it is not worth bumping this value up to 6 when the vast majority
23  // of instructions are 4 or 5 cycles.
24  let LoadLatency = 5;
25
26  // A total of 16 cycles to recover from a branch mispredict.
27  let MispredictPenalty = 16;
28
29  // Try to make sure we have at least 10 dispatch groups in a loop.
30  // A dispatch group is 6 instructions.
31  let LoopMicroOpBufferSize = 60;
32
33  // As iops are dispatched to a slice, they are held in an independent slice
34  // issue queue until all register sources and other dependencies have been
35  // resolved and they can be issued. Each of four execution slices has an
36  // 11-entry iop issue queue.
37  let MicroOpBufferSize = 44;
38
39  let CompleteModel = 1;
40
41  // Do not support SPE (Signal Processing Engine), prefixed instructions on
42  // Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions
43  // introduced in ISA 3.1.
44  let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, MMA,
45                             PCRelativeMemops, IsISA3_1];
46}
47
48let SchedModel = P9Model in {
49
50  // ***************** Processor Resources *****************
51
52  // Dispatcher slots:
53  // x0, x1, x2, and x3 are the dedicated slice dispatch ports, where each
54  // corresponds to one of the four execution slices.
55  def DISPx02 : ProcResource<2>;
56  def DISPx13 : ProcResource<2>;
57  // The xa and xb ports can be used to send an iop to either of the two slices
58  // of the superslice, but are restricted to iops with only two primary sources.
59  def DISPxab : ProcResource<2>;
60  // b0 and b1 are dedicated dispatch ports into the branch slice.
61  def DISPb01 : ProcResource<2>;
62
63  // Any non BR dispatch ports
64  def DISP_NBR
65      : ProcResGroup<[ DISPx02, DISPx13, DISPxab]>;
66  def DISP_SS : ProcResGroup<[ DISPx02, DISPx13]>;
67
68  // Issue Ports
69  // An instruction can go down one of two issue queues.
70  // Address Generation (AGEN) mainly for loads and stores.
71  // Execution (EXEC) for most other instructions.
72  // Some instructions cannot be run on just any issue queue and may require an
73  // Even or an Odd queue. The EXECE represents the even queues and the EXECO
74  // represents the odd queues.
75  def IP_AGEN : ProcResource<4>;
76  def IP_EXEC : ProcResource<4>;
77  def IP_EXECE : ProcResource<2> {
78    //Even Exec Ports
79    let Super = IP_EXEC;
80  }
81  def IP_EXECO : ProcResource<2> {
82    //Odd Exec Ports
83    let Super = IP_EXEC;
84  }
85
86  // Pipeline Groups
87  // Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd.
88  def ALU : ProcResource<4>;
89  def ALUE : ProcResource<2> {
90    //Even ALU pipelines
91    let Super = ALU;
92  }
93  def ALUO : ProcResource<2> {
94    //Odd ALU pipelines
95    let Super = ALU;
96  }
97
98  // Two DIV (Fixed Point Divide) units.
99  def DIV : ProcResource<2>;
100
101  // Four DP (Floating Point) units in total. Two even, two Odd.
102  def DP : ProcResource<4>;
103  def DPE : ProcResource<2> {
104    //Even DP pipelines
105    let Super = DP;
106  }
107  def DPO : ProcResource<2> {
108    //Odd DP pipelines
109    let Super = DP;
110  }
111
112  // Four LS (Load or Store) units.
113  def LS : ProcResource<4>;
114
115  // Two PM (Permute) units.
116  def PM : ProcResource<2>;
117
118  // Only one DFU (Decimal Floating Point and Quad Precision) unit.
119  def DFU : ProcResource<1>;
120
121  // Only one Branch unit.
122  def BR : ProcResource<1> {
123    let BufferSize = 16;
124  }
125
126  // Only one CY (Crypto) unit.
127  def CY : ProcResource<1>;
128
129  // ***************** SchedWriteRes Definitions *****************
130
131  // Dispatcher
132  // Dispatch Rules: '-' or 'V'
133  // Vector ('V') - vector iops (128-bit operand) take only one decode and
134  // dispatch slot but are dispatched to both the even and odd slices of a
135  // superslice.
136  def DISP_1C : SchedWriteRes<[DISP_NBR]> {
137    let NumMicroOps = 0;
138    let Latency = 1;
139  }
140  // Dispatch Rules: 'E'
141  // Even slice ('E')- certain operations must be sent only to an even slice.
142  // Also consumes odd dispatch slice slot of the same superslice at dispatch
143  def DISP_EVEN_1C : SchedWriteRes<[ DISPx02, DISPx13 ]> {
144    let NumMicroOps = 0;
145    let Latency = 1;
146  }
147  // Dispatch Rules: 'P'
148  // Paired ('P') - certain cracked and expanded iops are paired such that they
149  // must dispatch together to the same superslice.
150  def DISP_PAIR_1C : SchedWriteRes<[ DISP_SS, DISP_SS]> {
151    let NumMicroOps = 0;
152    let Latency = 1;
153  }
154  // Tuple Restricted ('R') - certain iops preclude dispatching more than one
155  // operation per slice for the super- slice to which they are dispatched
156  def DISP_3SLOTS_1C : SchedWriteRes<[DISPx02, DISPx13, DISPxab]> {
157    let NumMicroOps = 0;
158    let Latency = 1;
159  }
160  // Each execution and branch slice can receive up to two iops per cycle
161  def DISP_BR_1C : SchedWriteRes<[ DISPxab ]> {
162    let NumMicroOps = 0;
163    let Latency = 1;
164  }
165
166  // Issue Ports
167  def IP_AGEN_1C : SchedWriteRes<[IP_AGEN]> {
168    let NumMicroOps = 0;
169    let Latency = 1;
170  }
171
172  def IP_EXEC_1C : SchedWriteRes<[IP_EXEC]> {
173    let NumMicroOps = 0;
174    let Latency = 1;
175  }
176
177  def IP_EXECE_1C : SchedWriteRes<[IP_EXECE]> {
178    let NumMicroOps = 0;
179    let Latency = 1;
180  }
181
182  def IP_EXECO_1C : SchedWriteRes<[IP_EXECO]> {
183    let NumMicroOps = 0;
184    let Latency = 1;
185  }
186
187  //Pipeline Groups
188
189  // ALU Units
190  // An ALU may take either 2 or 3 cycles to complete the operation.
191  // However, the ALU unit is only ever busy for 1 cycle at a time and may
192  // receive new instructions each cycle.
193  def P9_ALU_2C : SchedWriteRes<[ALU]> {
194    let Latency = 2;
195  }
196
197  def P9_ALUE_2C : SchedWriteRes<[ALUE]> {
198    let Latency = 2;
199  }
200
201  def P9_ALUO_2C : SchedWriteRes<[ALUO]> {
202    let Latency = 2;
203  }
204
205  def P9_ALU_3C : SchedWriteRes<[ALU]> {
206    let Latency = 3;
207  }
208
209  def P9_ALUE_3C : SchedWriteRes<[ALUE]> {
210    let Latency = 3;
211  }
212
213  def P9_ALUO_3C : SchedWriteRes<[ALUO]> {
214    let Latency = 3;
215  }
216
217  // DIV Unit
218  // A DIV unit may take from 5 to 40 cycles to complete.
219  // Some DIV operations may keep the unit busy for up to 8 cycles.
220  def P9_DIV_5C : SchedWriteRes<[DIV]> {
221    let Latency = 5;
222  }
223
224  def P9_DIV_12C : SchedWriteRes<[DIV]> {
225    let Latency = 12;
226  }
227
228  def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
229    let ResourceCycles = [8];
230    let Latency = 16;
231  }
232
233  def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
234    let ResourceCycles = [8];
235    let Latency = 24;
236  }
237
238  def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
239    let ResourceCycles = [8];
240    let Latency = 40;
241  }
242
243  // DP Unit
244  // A DP unit may take from 2 to 36 cycles to complete.
245  // Some DP operations keep the unit busy for up to 10 cycles.
246  def P9_DP_5C : SchedWriteRes<[DP]> {
247    let Latency = 5;
248  }
249
250  def P9_DP_7C : SchedWriteRes<[DP]> {
251    let Latency = 7;
252  }
253
254  def P9_DPE_7C : SchedWriteRes<[DPE]> {
255    let Latency = 7;
256  }
257
258  def P9_DPO_7C : SchedWriteRes<[DPO]> {
259    let Latency = 7;
260  }
261
262  def P9_DP_22C_5 : SchedWriteRes<[DP]> {
263    let ResourceCycles = [5];
264    let Latency = 22;
265  }
266
267  def P9_DPO_24C_8 : SchedWriteRes<[DPO]> {
268    let ResourceCycles = [8];
269    let Latency = 24;
270  }
271
272  def P9_DPE_24C_8 : SchedWriteRes<[DPE]> {
273    let ResourceCycles = [8];
274    let Latency = 24;
275  }
276
277  def P9_DP_26C_5 : SchedWriteRes<[DP]> {
278    let ResourceCycles = [5];
279    let Latency = 22;
280  }
281
282  def P9_DPE_27C_10 : SchedWriteRes<[DP]> {
283    let ResourceCycles = [10];
284    let Latency = 27;
285  }
286
287  def P9_DPO_27C_10 : SchedWriteRes<[DP]> {
288    let ResourceCycles = [10];
289    let Latency = 27;
290  }
291
292  def P9_DP_33C_8 : SchedWriteRes<[DP]> {
293    let ResourceCycles = [8];
294    let Latency = 33;
295  }
296
297  def P9_DPE_33C_8 : SchedWriteRes<[DPE]> {
298    let ResourceCycles = [8];
299    let Latency = 33;
300  }
301
302  def P9_DPO_33C_8 : SchedWriteRes<[DPO]> {
303    let ResourceCycles = [8];
304    let Latency = 33;
305  }
306
307  def P9_DP_36C_10 : SchedWriteRes<[DP]> {
308    let ResourceCycles = [10];
309    let Latency = 36;
310  }
311
312  def P9_DPE_36C_10 : SchedWriteRes<[DP]> {
313    let ResourceCycles = [10];
314    let Latency = 36;
315  }
316
317  def P9_DPO_36C_10 : SchedWriteRes<[DP]> {
318    let ResourceCycles = [10];
319    let Latency = 36;
320  }
321
322  // PM Unit
323  // Three cycle permute operations.
324  def P9_PM_3C : SchedWriteRes<[PM]> {
325    let Latency = 3;
326  }
327
328  // Load and Store Units
329  // Loads can have 4, 5 or 6 cycles of latency.
330  // Stores are listed as having a single cycle of latency. This is not
331  // completely accurate since it takes more than 1 cycle to actually store
332  // the value. However, since the store does not produce a result it can be
333  // considered complete after one cycle.
334  def P9_LS_1C : SchedWriteRes<[LS]> {
335    let Latency = 1;
336  }
337
338  def P9_LS_4C : SchedWriteRes<[LS]> {
339    let Latency = 4;
340  }
341
342  def P9_LS_5C : SchedWriteRes<[LS]> {
343    let Latency = 5;
344  }
345
346  def P9_LS_6C : SchedWriteRes<[LS]> {
347    let Latency = 6;
348  }
349
350  // DFU Unit
351  // Some of the most expensive ops use the DFU.
352  // Can take from 12 cycles to 76 cycles to obtain a result.
353  // The unit may be busy for up to 62 cycles.
354  def P9_DFU_12C : SchedWriteRes<[DFU]> {
355    let Latency = 12;
356  }
357
358  def P9_DFU_23C : SchedWriteRes<[DFU]> {
359    let Latency = 23;
360    let ResourceCycles = [11];
361  }
362
363  def P9_DFU_24C : SchedWriteRes<[DFU]> {
364    let Latency = 24;
365    let ResourceCycles = [12];
366  }
367
368  def P9_DFU_37C : SchedWriteRes<[DFU]> {
369    let Latency = 37;
370    let ResourceCycles = [25];
371  }
372
373  def P9_DFU_58C : SchedWriteRes<[DFU]> {
374    let Latency = 58;
375    let ResourceCycles = [44];
376  }
377
378  def P9_DFU_76C : SchedWriteRes<[DFU]> {
379    let Latency = 76;
380    let ResourceCycles = [62];
381  }
382
383  // 2 or 5 cycle latencies for the branch unit.
384  def P9_BR_2C : SchedWriteRes<[BR]> {
385    let Latency = 2;
386  }
387
388  def P9_BR_5C : SchedWriteRes<[BR]> {
389    let Latency = 5;
390  }
391
392  // 6 cycle latency for the crypto unit
393  def P9_CY_6C : SchedWriteRes<[CY]> {
394    let Latency = 6;
395  }
396
397  // ***************** WriteSeq Definitions *****************
398
399  // These are combinations of the resources listed above.
400  // The idea is that some cracked instructions cannot be done in parallel and
401  // so the latencies for their resources must be added.
402  def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
403  def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
404  def P9_LoadAndALU2Op_7C : WriteSequence<[P9_LS_4C, P9_ALU_3C]>;
405  def P9_LoadAndALU2Op_8C : WriteSequence<[P9_LS_5C, P9_ALU_3C]>;
406  def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
407  def P9_LoadAndLoadOp_8C : WriteSequence<[P9_LS_4C, P9_LS_4C]>;
408  def P9_IntDivAndALUOp_18C_8 : WriteSequence<[P9_DIV_16C_8, P9_ALU_2C]>;
409  def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
410  def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
411  def P9_StoreAndALUOp_3C : WriteSequence<[P9_LS_1C, P9_ALU_2C]>;
412  def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
413  def P9_ALU2OpAndALU2Op_6C : WriteSequence<[P9_ALU_3C, P9_ALU_3C]>;
414  def P9_ALUOpAndALUOpAndALUOp_6C :
415    WriteSequence<[P9_ALU_2C, P9_ALU_2C, P9_ALU_2C]>;
416  def P9_DPOpAndALUOp_7C : WriteSequence<[P9_DP_5C, P9_ALU_2C]>;
417  def P9_DPOpAndALU2Op_10C : WriteSequence<[P9_DP_7C, P9_ALU_3C]>;
418  def P9_DPOpAndALU2Op_25C_5 : WriteSequence<[P9_DP_22C_5, P9_ALU_3C]>;
419  def P9_DPOpAndALU2Op_29C_5 : WriteSequence<[P9_DP_26C_5, P9_ALU_3C]>;
420  def P9_DPOpAndALU2Op_36C_8 : WriteSequence<[P9_DP_33C_8, P9_ALU_3C]>;
421  def P9_DPOpAndALU2Op_39C_10 : WriteSequence<[P9_DP_36C_10, P9_ALU_3C]>;
422  def P9_BROpAndALUOp_7C : WriteSequence<[P9_BR_5C, P9_ALU_2C]>;
423
424  // Include the resource requirements of individual instructions.
425  include "P9InstrResources.td"
426
427}
428
429