1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the PowerPC target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCTargetMachine.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "PPC.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCMachineScheduler.h"
18 #include "PPCMacroFusion.h"
19 #include "PPCSubtarget.h"
20 #include "PPCTargetObjectFile.h"
21 #include "PPCTargetTransformInfo.h"
22 #include "TargetInfo/PowerPCTargetInfo.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Analysis/TargetTransformInfo.h"
26 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
27 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
29 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
30 #include "llvm/CodeGen/GlobalISel/Localizer.h"
31 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
32 #include "llvm/CodeGen/MachineScheduler.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/CodeGen/TargetPassConfig.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/InitializePasses.h"
39 #include "llvm/MC/TargetRegistry.h"
40 #include "llvm/Pass.h"
41 #include "llvm/Support/CodeGen.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/TargetParser/Triple.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <cassert>
48 #include <memory>
49 #include <optional>
50 #include <string>
51 
52 using namespace llvm;
53 
54 
55 static cl::opt<bool>
56     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
57                            cl::desc("enable coalescing of duplicate branches for PPC"));
58 static cl::
59 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
60                         cl::desc("Disable CTR loops for PPC"));
61 
62 static cl::
63 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
64                             cl::desc("Disable PPC loop instr form prep"));
65 
66 static cl::opt<bool>
67 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
68   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
69 
70 static cl::
71 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
72                                 cl::desc("Disable VSX Swap Removal for PPC"));
73 
74 static cl::
75 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
76                             cl::desc("Disable machine peepholes for PPC"));
77 
78 static cl::opt<bool>
79 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
80              cl::desc("Enable optimizations on complex GEPs"),
81              cl::init(true));
82 
83 static cl::opt<bool>
84 EnablePrefetch("enable-ppc-prefetching",
85                   cl::desc("enable software prefetching on PPC"),
86                   cl::init(false), cl::Hidden);
87 
88 static cl::opt<bool>
89 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
90                       cl::desc("Add extra TOC register dependencies"),
91                       cl::init(true), cl::Hidden);
92 
93 static cl::opt<bool>
94 EnableMachineCombinerPass("ppc-machine-combiner",
95                           cl::desc("Enable the machine combiner pass"),
96                           cl::init(true), cl::Hidden);
97 
98 static cl::opt<bool>
99   ReduceCRLogical("ppc-reduce-cr-logicals",
100                   cl::desc("Expand eligible cr-logical binary ops to branches"),
101                   cl::init(true), cl::Hidden);
102 
103 static cl::opt<bool> EnablePPCGenScalarMASSEntries(
104     "enable-ppc-gen-scalar-mass", cl::init(false),
105     cl::desc("Enable lowering math functions to their corresponding MASS "
106              "(scalar) entries"),
107     cl::Hidden);
108 
109 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget() {
110   // Register the targets
111   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
112   RegisterTargetMachine<PPCTargetMachine> B(getThePPC32LETarget());
113   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64Target());
114   RegisterTargetMachine<PPCTargetMachine> D(getThePPC64LETarget());
115 
116   PassRegistry &PR = *PassRegistry::getPassRegistry();
117 #ifndef NDEBUG
118   initializePPCCTRLoopsVerifyPass(PR);
119 #endif
120   initializePPCLoopInstrFormPrepPass(PR);
121   initializePPCTOCRegDepsPass(PR);
122   initializePPCEarlyReturnPass(PR);
123   initializePPCVSXCopyPass(PR);
124   initializePPCVSXFMAMutatePass(PR);
125   initializePPCVSXSwapRemovalPass(PR);
126   initializePPCReduceCRLogicalsPass(PR);
127   initializePPCBSelPass(PR);
128   initializePPCBranchCoalescingPass(PR);
129   initializePPCBoolRetToIntPass(PR);
130   initializePPCExpandISELPass(PR);
131   initializePPCPreEmitPeepholePass(PR);
132   initializePPCTLSDynamicCallPass(PR);
133   initializePPCMIPeepholePass(PR);
134   initializePPCLowerMASSVEntriesPass(PR);
135   initializePPCGenScalarMASSEntriesPass(PR);
136   initializePPCExpandAtomicPseudoPass(PR);
137   initializeGlobalISel(PR);
138   initializePPCCTRLoopsPass(PR);
139   initializePPCDAGToDAGISelPass(PR);
140 }
141 
142 static bool isLittleEndianTriple(const Triple &T) {
143   return T.getArch() == Triple::ppc64le || T.getArch() == Triple::ppcle;
144 }
145 
146 /// Return the datalayout string of a subtarget.
147 static std::string getDataLayoutString(const Triple &T) {
148   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
149   std::string Ret;
150 
151   // Most PPC* platforms are big endian, PPC(64)LE is little endian.
152   if (isLittleEndianTriple(T))
153     Ret = "e";
154   else
155     Ret = "E";
156 
157   Ret += DataLayout::getManglingComponent(T);
158 
159   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
160   // pointers.
161   if (!is64Bit || T.getOS() == Triple::Lv2)
162     Ret += "-p:32:32";
163 
164   // If the target ABI uses function descriptors, then the alignment of function
165   // pointers depends on the alignment used to emit the descriptor. Otherwise,
166   // function pointers are aligned to 32 bits because the instructions must be.
167   if ((T.getArch() == Triple::ppc64 && !T.isPPC64ELFv2ABI())) {
168     Ret += "-Fi64";
169   } else if (T.isOSAIX()) {
170     Ret += is64Bit ? "-Fi64" : "-Fi32";
171   } else {
172     Ret += "-Fn32";
173   }
174 
175   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
176   // documentation are wrong; these are correct (i.e. "what gcc does").
177   Ret += "-i64:64";
178 
179   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
180   if (is64Bit)
181     Ret += "-n32:64";
182   else
183     Ret += "-n32";
184 
185   // Specify the vector alignment explicitly. For v256i1 and v512i1, the
186   // calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
187   // which is 256 and 512 bytes - way over aligned.
188   if (is64Bit && (T.isOSAIX() || T.isOSLinux()))
189     Ret += "-S128-v256:256:256-v512:512:512";
190 
191   return Ret;
192 }
193 
194 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
195                                       const Triple &TT) {
196   std::string FullFS = std::string(FS);
197 
198   // Make sure 64-bit features are available when CPUname is generic
199   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
200     if (!FullFS.empty())
201       FullFS = "+64bit," + FullFS;
202     else
203       FullFS = "+64bit";
204   }
205 
206   if (OL >= CodeGenOpt::Default) {
207     if (!FullFS.empty())
208       FullFS = "+crbits," + FullFS;
209     else
210       FullFS = "+crbits";
211   }
212 
213   if (OL != CodeGenOpt::None) {
214     if (!FullFS.empty())
215       FullFS = "+invariant-function-descriptors," + FullFS;
216     else
217       FullFS = "+invariant-function-descriptors";
218   }
219 
220   if (TT.isOSAIX()) {
221     if (!FullFS.empty())
222       FullFS = "+aix," + FullFS;
223     else
224       FullFS = "+aix";
225   }
226 
227   return FullFS;
228 }
229 
230 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
231   if (TT.isOSAIX())
232     return std::make_unique<TargetLoweringObjectFileXCOFF>();
233 
234   return std::make_unique<PPC64LinuxTargetObjectFile>();
235 }
236 
237 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
238                                                  const TargetOptions &Options) {
239   if (Options.MCOptions.getABIName().startswith("elfv1"))
240     return PPCTargetMachine::PPC_ABI_ELFv1;
241   else if (Options.MCOptions.getABIName().startswith("elfv2"))
242     return PPCTargetMachine::PPC_ABI_ELFv2;
243 
244   assert(Options.MCOptions.getABIName().empty() &&
245          "Unknown target-abi option!");
246 
247   switch (TT.getArch()) {
248   case Triple::ppc64le:
249     return PPCTargetMachine::PPC_ABI_ELFv2;
250   case Triple::ppc64:
251     if (TT.isPPC64ELFv2ABI())
252       return PPCTargetMachine::PPC_ABI_ELFv2;
253     else
254       return PPCTargetMachine::PPC_ABI_ELFv1;
255   default:
256     return PPCTargetMachine::PPC_ABI_UNKNOWN;
257   }
258 }
259 
260 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
261                                            std::optional<Reloc::Model> RM) {
262   assert((!TT.isOSAIX() || !RM || *RM == Reloc::PIC_) &&
263          "Invalid relocation model for AIX.");
264 
265   if (RM)
266     return *RM;
267 
268   // Big Endian PPC and AIX default to PIC.
269   if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())
270     return Reloc::PIC_;
271 
272   // Rest are static by default.
273   return Reloc::Static;
274 }
275 
276 static CodeModel::Model
277 getEffectivePPCCodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
278                          bool JIT) {
279   if (CM) {
280     if (*CM == CodeModel::Tiny)
281       report_fatal_error("Target does not support the tiny CodeModel", false);
282     if (*CM == CodeModel::Kernel)
283       report_fatal_error("Target does not support the kernel CodeModel", false);
284     return *CM;
285   }
286 
287   if (JIT)
288     return CodeModel::Small;
289   if (TT.isOSAIX())
290     return CodeModel::Small;
291 
292   assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");
293 
294   if (TT.isArch32Bit())
295     return CodeModel::Small;
296 
297   assert(TT.isArch64Bit() && "Unsupported PPC architecture.");
298   return CodeModel::Medium;
299 }
300 
301 
302 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
303   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
304   ScheduleDAGMILive *DAG =
305     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
306                           std::make_unique<PPCPreRASchedStrategy>(C) :
307                           std::make_unique<GenericScheduler>(C));
308   // add DAG Mutations here.
309   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
310   if (ST.hasStoreFusion())
311     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
312   if (ST.hasFusion())
313     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
314 
315   return DAG;
316 }
317 
318 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
319   MachineSchedContext *C) {
320   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
321   ScheduleDAGMI *DAG =
322     new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
323                       std::make_unique<PPCPostRASchedStrategy>(C) :
324                       std::make_unique<PostGenericScheduler>(C), true);
325   // add DAG Mutations here.
326   if (ST.hasStoreFusion())
327     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
328   if (ST.hasFusion())
329     DAG->addMutation(createPowerPCMacroFusionDAGMutation());
330   return DAG;
331 }
332 
333 // The FeatureString here is a little subtle. We are modifying the feature
334 // string with what are (currently) non-function specific overrides as it goes
335 // into the LLVMTargetMachine constructor and then using the stored value in the
336 // Subtarget constructor below it.
337 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
338                                    StringRef CPU, StringRef FS,
339                                    const TargetOptions &Options,
340                                    std::optional<Reloc::Model> RM,
341                                    std::optional<CodeModel::Model> CM,
342                                    CodeGenOpt::Level OL, bool JIT)
343     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
344                         computeFSAdditions(FS, OL, TT), Options,
345                         getEffectiveRelocModel(TT, RM),
346                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
347       TLOF(createTLOF(getTargetTriple())),
348       TargetABI(computeTargetABI(TT, Options)),
349       Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {
350   initAsmInfo();
351 }
352 
353 PPCTargetMachine::~PPCTargetMachine() = default;
354 
355 const PPCSubtarget *
356 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
357   Attribute CPUAttr = F.getFnAttribute("target-cpu");
358   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
359   Attribute FSAttr = F.getFnAttribute("target-features");
360 
361   std::string CPU =
362       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
363   std::string TuneCPU =
364       TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
365   std::string FS =
366       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
367 
368   // FIXME: This is related to the code below to reset the target options,
369   // we need to know whether or not the soft float flag is set on the
370   // function before we can generate a subtarget. We also need to use
371   // it as a key for the subtarget since that can be the only difference
372   // between two functions.
373   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
374   // If the soft float attribute is set on the function turn on the soft float
375   // subtarget feature.
376   if (SoftFloat)
377     FS += FS.empty() ? "-hard-float" : ",-hard-float";
378 
379   auto &I = SubtargetMap[CPU + TuneCPU + FS];
380   if (!I) {
381     // This needs to be done before we create a new subtarget since any
382     // creation will depend on the TM and the code generation flags on the
383     // function that reside in TargetOptions.
384     resetTargetOptions(F);
385     I = std::make_unique<PPCSubtarget>(
386         TargetTriple, CPU, TuneCPU,
387         // FIXME: It would be good to have the subtarget additions here
388         // not necessary. Anything that turns them on/off (overrides) ends
389         // up being put at the end of the feature string, but the defaults
390         // shouldn't require adding them. Fixing this means pulling Feature64Bit
391         // out of most of the target cpus in the .td file and making it set only
392         // as part of initialization via the TargetTriple.
393         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
394   }
395   return I.get();
396 }
397 
398 //===----------------------------------------------------------------------===//
399 // Pass Pipeline Configuration
400 //===----------------------------------------------------------------------===//
401 
402 namespace {
403 
404 /// PPC Code Generator Pass Configuration Options.
405 class PPCPassConfig : public TargetPassConfig {
406 public:
407   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
408     : TargetPassConfig(TM, PM) {
409     // At any optimization level above -O0 we use the Machine Scheduler and not
410     // the default Post RA List Scheduler.
411     if (TM.getOptLevel() != CodeGenOpt::None)
412       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
413   }
414 
415   PPCTargetMachine &getPPCTargetMachine() const {
416     return getTM<PPCTargetMachine>();
417   }
418 
419   void addIRPasses() override;
420   bool addPreISel() override;
421   bool addILPOpts() override;
422   bool addInstSelector() override;
423   void addMachineSSAOptimization() override;
424   void addPreRegAlloc() override;
425   void addPreSched2() override;
426   void addPreEmitPass() override;
427   void addPreEmitPass2() override;
428   // GlobalISEL
429   bool addIRTranslator() override;
430   bool addLegalizeMachineIR() override;
431   bool addRegBankSelect() override;
432   bool addGlobalInstructionSelect() override;
433 
434   ScheduleDAGInstrs *
435   createMachineScheduler(MachineSchedContext *C) const override {
436     return createPPCMachineScheduler(C);
437   }
438   ScheduleDAGInstrs *
439   createPostMachineScheduler(MachineSchedContext *C) const override {
440     return createPPCPostMachineScheduler(C);
441   }
442 };
443 
444 } // end anonymous namespace
445 
446 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
447   return new PPCPassConfig(*this, PM);
448 }
449 
450 void PPCPassConfig::addIRPasses() {
451   if (TM->getOptLevel() != CodeGenOpt::None)
452     addPass(createPPCBoolRetToIntPass());
453   addPass(createAtomicExpandPass());
454 
455   // Lower generic MASSV routines to PowerPC subtarget-specific entries.
456   addPass(createPPCLowerMASSVEntriesPass());
457 
458   // Generate PowerPC target-specific entries for scalar math functions
459   // that are available in IBM MASS (scalar) library.
460   if (TM->getOptLevel() == CodeGenOpt::Aggressive &&
461       EnablePPCGenScalarMASSEntries) {
462     TM->Options.PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries;
463     addPass(createPPCGenScalarMASSEntriesPass());
464   }
465 
466   // If explicitly requested, add explicit data prefetch intrinsics.
467   if (EnablePrefetch.getNumOccurrences() > 0)
468     addPass(createLoopDataPrefetchPass());
469 
470   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
471     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
472     // and lower a GEP with multiple indices to either arithmetic operations or
473     // multiple GEPs with single index.
474     addPass(createSeparateConstOffsetFromGEPPass(true));
475     // Call EarlyCSE pass to find and remove subexpressions in the lowered
476     // result.
477     addPass(createEarlyCSEPass());
478     // Do loop invariant code motion in case part of the lowered result is
479     // invariant.
480     addPass(createLICMPass());
481   }
482 
483   TargetPassConfig::addIRPasses();
484 }
485 
486 bool PPCPassConfig::addPreISel() {
487   if (!DisableInstrFormPrep && getOptLevel() != CodeGenOpt::None)
488     addPass(createPPCLoopInstrFormPrepPass(getPPCTargetMachine()));
489 
490   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
491     addPass(createHardwareLoopsLegacyPass());
492 
493   return false;
494 }
495 
496 bool PPCPassConfig::addILPOpts() {
497   addPass(&EarlyIfConverterID);
498 
499   if (EnableMachineCombinerPass)
500     addPass(&MachineCombinerID);
501 
502   return true;
503 }
504 
505 bool PPCPassConfig::addInstSelector() {
506   // Install an instruction selector.
507   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
508 
509 #ifndef NDEBUG
510   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
511     addPass(createPPCCTRLoopsVerify());
512 #endif
513 
514   addPass(createPPCVSXCopyPass());
515   return false;
516 }
517 
518 void PPCPassConfig::addMachineSSAOptimization() {
519   // Run CTR loops pass before any cfg modification pass to prevent the
520   // canonical form of hardware loop from being destroied.
521   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
522     addPass(createPPCCTRLoopsPass());
523 
524   // PPCBranchCoalescingPass need to be done before machine sinking
525   // since it merges empty blocks.
526   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
527     addPass(createPPCBranchCoalescingPass());
528   TargetPassConfig::addMachineSSAOptimization();
529   // For little endian, remove where possible the vector swap instructions
530   // introduced at code generation to normalize vector element order.
531   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
532       !DisableVSXSwapRemoval)
533     addPass(createPPCVSXSwapRemovalPass());
534   // Reduce the number of cr-logical ops.
535   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
536     addPass(createPPCReduceCRLogicalsPass());
537   // Target-specific peephole cleanups performed after instruction
538   // selection.
539   if (!DisableMIPeephole) {
540     addPass(createPPCMIPeepholePass());
541     addPass(&DeadMachineInstructionElimID);
542   }
543 }
544 
545 void PPCPassConfig::addPreRegAlloc() {
546   if (getOptLevel() != CodeGenOpt::None) {
547     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
548     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
549                &PPCVSXFMAMutateID);
550   }
551 
552   // FIXME: We probably don't need to run these for -fPIE.
553   if (getPPCTargetMachine().isPositionIndependent()) {
554     // FIXME: LiveVariables should not be necessary here!
555     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
556     // LiveVariables. This (unnecessary) dependency has been removed now,
557     // however a stage-2 clang build fails without LiveVariables computed here.
558     addPass(&LiveVariablesID);
559     addPass(createPPCTLSDynamicCallPass());
560   }
561   if (EnableExtraTOCRegDeps)
562     addPass(createPPCTOCRegDepsPass());
563 
564   if (getOptLevel() != CodeGenOpt::None)
565     addPass(&MachinePipelinerID);
566 }
567 
568 void PPCPassConfig::addPreSched2() {
569   if (getOptLevel() != CodeGenOpt::None)
570     addPass(&IfConverterID);
571 }
572 
573 void PPCPassConfig::addPreEmitPass() {
574   addPass(createPPCPreEmitPeepholePass());
575   addPass(createPPCExpandISELPass());
576 
577   if (getOptLevel() != CodeGenOpt::None)
578     addPass(createPPCEarlyReturnPass());
579 }
580 
581 void PPCPassConfig::addPreEmitPass2() {
582   // Schedule the expansion of AMOs at the last possible moment, avoiding the
583   // possibility for other passes to break the requirements for forward
584   // progress in the LL/SC block.
585   addPass(createPPCExpandAtomicPseudoPass());
586   // Must run branch selection immediately preceding the asm printer.
587   addPass(createPPCBranchSelectionPass());
588 }
589 
590 TargetTransformInfo
591 PPCTargetMachine::getTargetTransformInfo(const Function &F) const {
592   return TargetTransformInfo(PPCTTIImpl(this, F));
593 }
594 
595 bool PPCTargetMachine::isLittleEndian() const {
596   assert(Endianness != Endian::NOT_DETECTED &&
597          "Unable to determine endianness");
598   return Endianness == Endian::LITTLE;
599 }
600 
601 MachineFunctionInfo *PPCTargetMachine::createMachineFunctionInfo(
602     BumpPtrAllocator &Allocator, const Function &F,
603     const TargetSubtargetInfo *STI) const {
604   return PPCFunctionInfo::create<PPCFunctionInfo>(Allocator, F, STI);
605 }
606 
607 static MachineSchedRegistry
608 PPCPreRASchedRegistry("ppc-prera",
609                       "Run PowerPC PreRA specific scheduler",
610                       createPPCMachineScheduler);
611 
612 static MachineSchedRegistry
613 PPCPostRASchedRegistry("ppc-postra",
614                        "Run PowerPC PostRA specific scheduler",
615                        createPPCPostMachineScheduler);
616 
617 // Global ISEL
618 bool PPCPassConfig::addIRTranslator() {
619   addPass(new IRTranslator());
620   return false;
621 }
622 
623 bool PPCPassConfig::addLegalizeMachineIR() {
624   addPass(new Legalizer());
625   return false;
626 }
627 
628 bool PPCPassConfig::addRegBankSelect() {
629   addPass(new RegBankSelect());
630   return false;
631 }
632 
633 bool PPCPassConfig::addGlobalInstructionSelect() {
634   addPass(new InstructionSelect(getOptLevel()));
635   return false;
636 }
637