1 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCVDisassembler class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/RISCVBaseInfo.h"
14 #include "MCTargetDesc/RISCVMCTargetDesc.h"
15 #include "TargetInfo/RISCVTargetInfo.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/TargetRegistry.h"
24 #include "llvm/Support/Endian.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "riscv-disassembler"
29 
30 typedef MCDisassembler::DecodeStatus DecodeStatus;
31 
32 namespace {
33 class RISCVDisassembler : public MCDisassembler {
34   std::unique_ptr<MCInstrInfo const> const MCII;
35 
36 public:
37   RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
38                     MCInstrInfo const *MCII)
39       : MCDisassembler(STI, Ctx), MCII(MCII) {}
40 
41   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
42                               ArrayRef<uint8_t> Bytes, uint64_t Address,
43                               raw_ostream &CStream) const override;
44 };
45 } // end anonymous namespace
46 
47 static MCDisassembler *createRISCVDisassembler(const Target &T,
48                                                const MCSubtargetInfo &STI,
49                                                MCContext &Ctx) {
50   return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
51 }
52 
53 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
54   // Register the disassembler for each target.
55   TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
56                                          createRISCVDisassembler);
57   TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
58                                          createRISCVDisassembler);
59 }
60 
61 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
62                                            uint64_t Address,
63                                            const void *Decoder) {
64   const FeatureBitset &FeatureBits =
65       static_cast<const MCDisassembler *>(Decoder)
66           ->getSubtargetInfo()
67           .getFeatureBits();
68   bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
69 
70   if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
71     return MCDisassembler::Fail;
72 
73   MCRegister Reg = RISCV::X0 + RegNo;
74   Inst.addOperand(MCOperand::createReg(Reg));
75   return MCDisassembler::Success;
76 }
77 
78 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint64_t RegNo,
79                                              uint64_t Address,
80                                              const void *Decoder) {
81   if (RegNo >= 32)
82     return MCDisassembler::Fail;
83 
84   MCRegister Reg = RISCV::F0_H + RegNo;
85   Inst.addOperand(MCOperand::createReg(Reg));
86   return MCDisassembler::Success;
87 }
88 
89 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
90                                              uint64_t Address,
91                                              const void *Decoder) {
92   if (RegNo >= 32)
93     return MCDisassembler::Fail;
94 
95   MCRegister Reg = RISCV::F0_F + RegNo;
96   Inst.addOperand(MCOperand::createReg(Reg));
97   return MCDisassembler::Success;
98 }
99 
100 static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
101                                               uint64_t Address,
102                                               const void *Decoder) {
103   if (RegNo >= 8) {
104     return MCDisassembler::Fail;
105   }
106   MCRegister Reg = RISCV::F8_F + RegNo;
107   Inst.addOperand(MCOperand::createReg(Reg));
108   return MCDisassembler::Success;
109 }
110 
111 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
112                                              uint64_t Address,
113                                              const void *Decoder) {
114   if (RegNo >= 32)
115     return MCDisassembler::Fail;
116 
117   MCRegister Reg = RISCV::F0_D + RegNo;
118   Inst.addOperand(MCOperand::createReg(Reg));
119   return MCDisassembler::Success;
120 }
121 
122 static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
123                                               uint64_t Address,
124                                               const void *Decoder) {
125   if (RegNo >= 8) {
126     return MCDisassembler::Fail;
127   }
128   MCRegister Reg = RISCV::F8_D + RegNo;
129   Inst.addOperand(MCOperand::createReg(Reg));
130   return MCDisassembler::Success;
131 }
132 
133 static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
134                                                uint64_t Address,
135                                                const void *Decoder) {
136   if (RegNo == 0) {
137     return MCDisassembler::Fail;
138   }
139 
140   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
141 }
142 
143 static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
144                                                  uint64_t Address,
145                                                  const void *Decoder) {
146   if (RegNo == 2) {
147     return MCDisassembler::Fail;
148   }
149 
150   return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
151 }
152 
153 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
154                                             uint64_t Address,
155                                             const void *Decoder) {
156   if (RegNo >= 8)
157     return MCDisassembler::Fail;
158 
159   MCRegister Reg = RISCV::X8 + RegNo;
160   Inst.addOperand(MCOperand::createReg(Reg));
161   return MCDisassembler::Success;
162 }
163 
164 static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint64_t RegNo,
165                                                uint64_t Address,
166                                                const void *Decoder) {
167   if (RegNo >= 32 || RegNo & 1)
168     return MCDisassembler::Fail;
169 
170   MCRegister Reg = RISCV::X0 + RegNo;
171   Inst.addOperand(MCOperand::createReg(Reg));
172   return MCDisassembler::Success;
173 }
174 
175 static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
176                                           uint64_t Address,
177                                           const void *Decoder) {
178   if (RegNo >= 32)
179     return MCDisassembler::Fail;
180 
181   MCRegister Reg = RISCV::V0 + RegNo;
182   Inst.addOperand(MCOperand::createReg(Reg));
183   return MCDisassembler::Success;
184 }
185 
186 static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo,
187                                             uint64_t Address,
188                                             const void *Decoder) {
189   if (RegNo >= 32)
190     return MCDisassembler::Fail;
191 
192   if (RegNo % 2)
193     return MCDisassembler::Fail;
194 
195   const RISCVDisassembler *Dis =
196       static_cast<const RISCVDisassembler *>(Decoder);
197   const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
198   MCRegister Reg =
199       RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
200                               &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
201 
202   Inst.addOperand(MCOperand::createReg(Reg));
203   return MCDisassembler::Success;
204 }
205 
206 static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo,
207                                             uint64_t Address,
208                                             const void *Decoder) {
209   if (RegNo >= 32)
210     return MCDisassembler::Fail;
211 
212   if (RegNo % 4)
213     return MCDisassembler::Fail;
214 
215   const RISCVDisassembler *Dis =
216       static_cast<const RISCVDisassembler *>(Decoder);
217   const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
218   MCRegister Reg =
219       RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
220                               &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
221 
222   Inst.addOperand(MCOperand::createReg(Reg));
223   return MCDisassembler::Success;
224 }
225 
226 static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo,
227                                             uint64_t Address,
228                                             const void *Decoder) {
229   if (RegNo >= 32)
230     return MCDisassembler::Fail;
231 
232   if (RegNo % 8)
233     return MCDisassembler::Fail;
234 
235   const RISCVDisassembler *Dis =
236       static_cast<const RISCVDisassembler *>(Decoder);
237   const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
238   MCRegister Reg =
239       RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
240                               &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
241 
242   Inst.addOperand(MCOperand::createReg(Reg));
243   return MCDisassembler::Success;
244 }
245 
246 static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
247                                    uint64_t Address, const void *Decoder) {
248   MCRegister Reg = RISCV::NoRegister;
249   switch (RegNo) {
250   default:
251     return MCDisassembler::Fail;
252   case 0:
253     Reg = RISCV::V0;
254     break;
255   case 1:
256     break;
257   }
258   Inst.addOperand(MCOperand::createReg(Reg));
259   return MCDisassembler::Success;
260 }
261 
262 // Add implied SP operand for instructions *SP compressed instructions. The SP
263 // operand isn't explicitly encoded in the instruction.
264 static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
265   if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
266       Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
267       Inst.getOpcode() == RISCV::C_FLWSP ||
268       Inst.getOpcode() == RISCV::C_FSWSP ||
269       Inst.getOpcode() == RISCV::C_FLDSP ||
270       Inst.getOpcode() == RISCV::C_FSDSP ||
271       Inst.getOpcode() == RISCV::C_ADDI4SPN) {
272     DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
273   }
274   if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
275     DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
276     DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
277   }
278 }
279 
280 template <unsigned N>
281 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
282                                       int64_t Address, const void *Decoder) {
283   assert(isUInt<N>(Imm) && "Invalid immediate");
284   addImplySP(Inst, Address, Decoder);
285   Inst.addOperand(MCOperand::createImm(Imm));
286   return MCDisassembler::Success;
287 }
288 
289 template <unsigned N>
290 static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
291                                              int64_t Address,
292                                              const void *Decoder) {
293   if (Imm == 0)
294     return MCDisassembler::Fail;
295   return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
296 }
297 
298 template <unsigned N>
299 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
300                                       int64_t Address, const void *Decoder) {
301   assert(isUInt<N>(Imm) && "Invalid immediate");
302   addImplySP(Inst, Address, Decoder);
303   // Sign-extend the number in the bottom N bits of Imm
304   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
305   return MCDisassembler::Success;
306 }
307 
308 template <unsigned N>
309 static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
310                                              int64_t Address,
311                                              const void *Decoder) {
312   if (Imm == 0)
313     return MCDisassembler::Fail;
314   return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
315 }
316 
317 template <unsigned N>
318 static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
319                                              int64_t Address,
320                                              const void *Decoder) {
321   assert(isUInt<N>(Imm) && "Invalid immediate");
322   // Sign-extend the number in the bottom N bits of Imm after accounting for
323   // the fact that the N bit immediate is stored in N-1 bits (the LSB is
324   // always zero)
325   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
326   return MCDisassembler::Success;
327 }
328 
329 static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint64_t Imm,
330                                          int64_t Address,
331                                          const void *Decoder) {
332   assert(isUInt<6>(Imm) && "Invalid immediate");
333   if (Imm > 31) {
334     Imm = (SignExtend64<6>(Imm) & 0xfffff);
335   }
336   Inst.addOperand(MCOperand::createImm(Imm));
337   return MCDisassembler::Success;
338 }
339 
340 static DecodeStatus decodeFRMArg(MCInst &Inst, uint64_t Imm,
341                                  int64_t Address,
342                                  const void *Decoder) {
343   assert(isUInt<3>(Imm) && "Invalid immediate");
344   if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
345     return MCDisassembler::Fail;
346 
347   Inst.addOperand(MCOperand::createImm(Imm));
348   return MCDisassembler::Success;
349 }
350 
351 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
352                                        uint64_t Address, const void *Decoder);
353 
354 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
355                                          uint64_t Address, const void *Decoder);
356 
357 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
358                                             uint64_t Address,
359                                             const void *Decoder);
360 
361 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
362                                         uint64_t Address, const void *Decoder);
363 
364 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
365                                            uint64_t Address,
366                                            const void *Decoder);
367 
368 #include "RISCVGenDisassemblerTables.inc"
369 
370 static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
371                                        uint64_t Address, const void *Decoder) {
372   uint64_t SImm6 =
373       fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
374   DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
375   (void)Result;
376   assert(Result == MCDisassembler::Success && "Invalid immediate");
377   return MCDisassembler::Success;
378 }
379 
380 static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
381                                          uint64_t Address,
382                                          const void *Decoder) {
383   DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
384   uint64_t SImm6 =
385       fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
386   DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
387   (void)Result;
388   assert(Result == MCDisassembler::Success && "Invalid immediate");
389   return MCDisassembler::Success;
390 }
391 
392 static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
393                                             uint64_t Address,
394                                             const void *Decoder) {
395   DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
396   Inst.addOperand(Inst.getOperand(0));
397   uint64_t UImm6 =
398       fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
399   DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
400   (void)Result;
401   assert(Result == MCDisassembler::Success && "Invalid immediate");
402   return MCDisassembler::Success;
403 }
404 
405 static DecodeStatus decodeRVCInstrRdRs2(MCInst &Inst, unsigned Insn,
406                                         uint64_t Address, const void *Decoder) {
407   unsigned Rd = fieldFromInstruction(Insn, 7, 5);
408   unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
409   DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
410   DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
411   return MCDisassembler::Success;
412 }
413 
414 static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst &Inst, unsigned Insn,
415                                            uint64_t Address,
416                                            const void *Decoder) {
417   unsigned Rd = fieldFromInstruction(Insn, 7, 5);
418   unsigned Rs2 = fieldFromInstruction(Insn, 2, 5);
419   DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
420   Inst.addOperand(Inst.getOperand(0));
421   DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
422   return MCDisassembler::Success;
423 }
424 
425 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
426                                                ArrayRef<uint8_t> Bytes,
427                                                uint64_t Address,
428                                                raw_ostream &CS) const {
429   // TODO: This will need modification when supporting instruction set
430   // extensions with instructions > 32-bits (up to 176 bits wide).
431   uint32_t Insn;
432   DecodeStatus Result;
433 
434   // It's a 32 bit instruction if bit 0 and 1 are 1.
435   if ((Bytes[0] & 0x3) == 0x3) {
436     if (Bytes.size() < 4) {
437       Size = 0;
438       return MCDisassembler::Fail;
439     }
440     Insn = support::endian::read32le(Bytes.data());
441     if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] &&
442         !STI.getFeatureBits()[RISCV::Feature64Bit]) {
443       LLVM_DEBUG(dbgs() << "Trying RV32Zdinx table (Double in Integer and"
444                            "rv32)\n");
445       Result = decodeInstruction(DecoderTableRV32Zdinx32, MI, Insn, Address,
446                                  this, STI);
447       if (Result != MCDisassembler::Fail) {
448         Size = 4;
449         return Result;
450       }
451     }
452 
453     if (STI.getFeatureBits()[RISCV::FeatureStdExtZfinx]) {
454       LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n");
455       Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this,
456                                  STI);
457       if (Result != MCDisassembler::Fail) {
458         Size = 4;
459         return Result;
460       }
461     }
462     LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
463     Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
464     Size = 4;
465   } else {
466     if (Bytes.size() < 2) {
467       Size = 0;
468       return MCDisassembler::Fail;
469     }
470     Insn = support::endian::read16le(Bytes.data());
471 
472     if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
473       LLVM_DEBUG(
474           dbgs() << "Trying RISCV32Only_16 table (16-bit Instruction):\n");
475       // Calling the auto-generated decoder function.
476       Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address,
477                                  this, STI);
478       if (Result != MCDisassembler::Fail) {
479         Size = 2;
480         return Result;
481       }
482     }
483 
484     LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
485     // Calling the auto-generated decoder function.
486     Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
487     Size = 2;
488   }
489 
490   return Result;
491 }
492