1 //===-- RISCVTargetStreamer.cpp - RISC-V Target Streamer Methods ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides RISC-V specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetStreamer.h"
14 #include "RISCVBaseInfo.h"
15 #include "RISCVMCTargetDesc.h"
16 #include "llvm/MC/MCSymbol.h"
17 #include "llvm/Support/FormattedStream.h"
18 #include "llvm/Support/RISCVAttributes.h"
19 #include "llvm/Support/RISCVISAInfo.h"
20 
21 using namespace llvm;
22 
23 RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
24 
25 void RISCVTargetStreamer::finish() { finishAttributeSection(); }
26 void RISCVTargetStreamer::reset() {}
27 
28 void RISCVTargetStreamer::emitDirectiveOptionPush() {}
29 void RISCVTargetStreamer::emitDirectiveOptionPop() {}
30 void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
31 void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
32 void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
33 void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
34 void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
35 void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
36 void RISCVTargetStreamer::emitDirectiveOptionArch(
37     ArrayRef<RISCVOptionArchArg> Args) {}
38 void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {}
39 void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
40 void RISCVTargetStreamer::finishAttributeSection() {}
41 void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
42                                             StringRef String) {}
43 void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
44                                                unsigned IntValue,
45                                                StringRef StringValue) {}
46 void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
47   assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
48   TargetABI = ABI;
49 }
50 
51 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
52                                                bool EmitStackAlign) {
53   if (STI.hasFeature(RISCV::FeatureRVE))
54     report_fatal_error("Codegen not yet implemented for RVE");
55 
56   if (EmitStackAlign)
57     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
58 
59   auto ParseResult = RISCVFeatures::parseFeatureBits(
60       STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
61   if (!ParseResult) {
62     report_fatal_error(ParseResult.takeError());
63   } else {
64     auto &ISAInfo = *ParseResult;
65     emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());
66   }
67 }
68 
69 // This part is for ascii assembly output
70 RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
71                                                formatted_raw_ostream &OS)
72     : RISCVTargetStreamer(S), OS(OS) {}
73 
74 void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
75   OS << "\t.option\tpush\n";
76 }
77 
78 void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
79   OS << "\t.option\tpop\n";
80 }
81 
82 void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
83   OS << "\t.option\tpic\n";
84 }
85 
86 void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
87   OS << "\t.option\tnopic\n";
88 }
89 
90 void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
91   OS << "\t.option\trvc\n";
92 }
93 
94 void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
95   OS << "\t.option\tnorvc\n";
96 }
97 
98 void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
99   OS << "\t.option\trelax\n";
100 }
101 
102 void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
103   OS << "\t.option\tnorelax\n";
104 }
105 
106 void RISCVTargetAsmStreamer::emitDirectiveOptionArch(
107     ArrayRef<RISCVOptionArchArg> Args) {
108   OS << "\t.option\tarch";
109   for (const auto &Arg : Args) {
110     OS << ", ";
111     switch (Arg.Type) {
112     case RISCVOptionArchArgType::Full:
113       break;
114     case RISCVOptionArchArgType::Plus:
115       OS << "+";
116       break;
117     case RISCVOptionArchArgType::Minus:
118       OS << "-";
119       break;
120     }
121     OS << Arg.Value;
122   }
123   OS << "\n";
124 }
125 
126 void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol &Symbol) {
127   OS << "\t.variant_cc\t" << Symbol.getName() << "\n";
128 }
129 
130 void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
131   OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
132 }
133 
134 void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
135                                                StringRef String) {
136   OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
137 }
138 
139 void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
140                                                   unsigned IntValue,
141                                                   StringRef StringValue) {}
142 
143 void RISCVTargetAsmStreamer::finishAttributeSection() {}
144