1//===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9include "llvm/Target/Target.td"
10
11//===----------------------------------------------------------------------===//
12// RISC-V subtarget features and instruction predicates.
13//===----------------------------------------------------------------------===//
14
15def FeatureStdExtM
16    : SubtargetFeature<"m", "HasStdExtM", "true",
17                       "'M' (Integer Multiplication and Division)">;
18def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
19                           AssemblerPredicate<(all_of FeatureStdExtM),
20                           "'M' (Integer Multiplication and Division)">;
21
22def FeatureStdExtA
23    : SubtargetFeature<"a", "HasStdExtA", "true",
24                       "'A' (Atomic Instructions)">;
25def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
26                           AssemblerPredicate<(all_of FeatureStdExtA),
27                           "'A' (Atomic Instructions)">;
28
29def FeatureStdExtF
30    : SubtargetFeature<"f", "HasStdExtF", "true",
31                       "'F' (Single-Precision Floating-Point)">;
32def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
33                           AssemblerPredicate<(all_of FeatureStdExtF),
34                           "'F' (Single-Precision Floating-Point)">;
35
36def FeatureStdExtD
37    : SubtargetFeature<"d", "HasStdExtD", "true",
38                       "'D' (Double-Precision Floating-Point)",
39                       [FeatureStdExtF]>;
40def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
41                           AssemblerPredicate<(all_of FeatureStdExtD),
42                           "'D' (Double-Precision Floating-Point)">;
43
44def FeatureStdExtZfhmin
45    : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
46                       "'Zfhmin' (Half-Precision Floating-Point Minimal)",
47                       [FeatureStdExtF]>;
48def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
49                             AssemblerPredicate<(all_of FeatureStdExtZfhmin),
50                             "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
51
52def FeatureStdExtZfh
53    : SubtargetFeature<"zfh", "HasStdExtZfh", "true",
54                       "'Zfh' (Half-Precision Floating-Point)",
55                       [FeatureStdExtF]>;
56def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
57                             AssemblerPredicate<(all_of FeatureStdExtZfh),
58                             "'Zfh' (Half-Precision Floating-Point)">;
59
60def HasStdExtZfhOrZfhmin
61    : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZfhmin()">,
62                AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin),
63                                   "'Zfh' (Half-Precision Floating-Point) or "
64                                   "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
65
66def FeatureStdExtZfinx
67    : SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
68                       "'Zfinx' (Float in Integer)">;
69def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
70                               AssemblerPredicate<(all_of FeatureStdExtZfinx),
71                               "'Zfinx' (Float in Integer)">;
72
73def FeatureStdExtZdinx
74    : SubtargetFeature<"zdinx", "HasStdExtZdinx", "true",
75                       "'Zdinx' (Double in Integer)",
76                       [FeatureStdExtZfinx]>;
77def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
78                               AssemblerPredicate<(all_of FeatureStdExtZdinx),
79                               "'Zdinx' (Double in Integer)">;
80
81def FeatureStdExtZhinxmin
82    : SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true",
83                       "'Zhinxmin' (Half Float in Integer Minimal)",
84                       [FeatureStdExtZfinx]>;
85def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
86                                  AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
87                                  "'Zhinxmin' (Half Float in Integer Minimal)">;
88
89def FeatureStdExtZhinx
90    : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true",
91                       "'Zhinx' (Half Float in Integer)",
92                       [FeatureStdExtZfinx]>;
93def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
94                               AssemblerPredicate<(all_of FeatureStdExtZhinx),
95                               "'Zhinx' (Half Float in Integer)">;
96
97def HasStdExtZhinxOrZhinxmin
98    : Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
99                AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin),
100                                   "'Zhinx' (Half Float in Integer) or "
101                                   "'Zhinxmin' (Half Float in Integer Minimal)">;
102
103def FeatureStdExtC
104    : SubtargetFeature<"c", "HasStdExtC", "true",
105                       "'C' (Compressed Instructions)">;
106def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
107                           AssemblerPredicate<(all_of FeatureStdExtC),
108                           "'C' (Compressed Instructions)">;
109
110def FeatureStdExtZba
111    : SubtargetFeature<"zba", "HasStdExtZba", "true",
112                       "'Zba' (Address Generation Instructions)">;
113def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
114                             AssemblerPredicate<(all_of FeatureStdExtZba),
115                             "'Zba' (Address Generation Instructions)">;
116def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
117
118def FeatureStdExtZbb
119    : SubtargetFeature<"zbb", "HasStdExtZbb", "true",
120                       "'Zbb' (Basic Bit-Manipulation)">;
121def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
122                             AssemblerPredicate<(all_of FeatureStdExtZbb),
123                             "'Zbb' (Basic Bit-Manipulation)">;
124
125def FeatureStdExtZbc
126    : SubtargetFeature<"zbc", "HasStdExtZbc", "true",
127                       "'Zbc' (Carry-Less Multiplication)">;
128def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
129                             AssemblerPredicate<(all_of FeatureStdExtZbc),
130                             "'Zbc' (Carry-Less Multiplication)">;
131
132def FeatureStdExtZbe
133    : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true",
134                       "'Zbe' (Extract-Deposit 'Zb' Instructions)">;
135def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">,
136                             AssemblerPredicate<(all_of FeatureStdExtZbe),
137                             "'Zbe' (Extract-Deposit 'Zb' Instructions)">;
138
139def FeatureStdExtZbf
140    : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true",
141                       "'Zbf' (Bit-Field 'Zb' Instructions)">;
142def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">,
143                             AssemblerPredicate<(all_of FeatureStdExtZbf),
144                             "'Zbf' (Bit-Field 'Zb' Instructions)">;
145
146def FeatureStdExtZbm
147    : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true",
148                       "'Zbm' (Matrix 'Zb' Instructions)">;
149def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">,
150                             AssemblerPredicate<(all_of FeatureStdExtZbm),
151                             "'Zbm' (Matrix 'Zb' Instructions)">;
152
153def FeatureStdExtZbp
154    : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true",
155                       "'Zbp' (Permutation 'Zb' Instructions)">;
156def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">,
157                             AssemblerPredicate<(all_of FeatureStdExtZbp),
158                             "'Zbp' (Permutation 'Zb' Instructions)">;
159
160def FeatureStdExtZbr
161    : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true",
162                       "'Zbr' (Polynomial Reduction 'Zb' Instructions)">;
163def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">,
164                             AssemblerPredicate<(all_of FeatureStdExtZbr),
165                             "'Zbr' (Polynomial Reduction 'Zb' Instructions)">;
166
167def FeatureStdExtZbs
168    : SubtargetFeature<"zbs", "HasStdExtZbs", "true",
169                       "'Zbs' (Single-Bit Instructions)">;
170def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
171                             AssemblerPredicate<(all_of FeatureStdExtZbs),
172                             "'Zbs' (Single-Bit Instructions)">;
173
174def FeatureStdExtZbt
175    : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true",
176                       "'Zbt' (Ternary 'Zb' Instructions)">;
177def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
178                             AssemblerPredicate<(all_of FeatureStdExtZbt),
179                             "'Zbt' (Ternary 'Zb' Instructions)">;
180
181// Some instructions belong to both the basic and the permutation
182// subextensions. They should be enabled if either has been specified.
183def HasStdExtZbbOrZbp
184    : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">,
185                AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp),
186                                   "'Zbb' (Basic Bit-Manipulation) or "
187                                   "'Zbp' (Permutation 'Zb' Instructions)">;
188
189def FeatureStdExtZbkb
190    : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
191                       "'Zbkb' (Bitmanip instructions for Cryptography)">;
192def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
193                             AssemblerPredicate<(all_of FeatureStdExtZbkb),
194                             "'Zbkb' (Bitmanip instructions for Cryptography)">;
195
196def FeatureStdExtZbkx
197    : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true",
198                       "'Zbkx' (Crossbar permutation instructions)">;
199def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
200                             AssemblerPredicate<(all_of FeatureStdExtZbkx),
201                             "'Zbkx' (Crossbar permutation instructions)">;
202
203def HasStdExtZbpOrZbkx
204    : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkx()">,
205                AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkx),
206                                   "'Zbp' (Permutation 'Zb' Instructions) or "
207                                   "'Zbkx' (Crossbar permutation instructions)">;
208
209def HasStdExtZbpOrZbkb
210    : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
211                AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkb),
212                                   "'Zbp' (Permutation 'Zb' Instructions) or "
213                                   "'Zbkb' (Bitmanip instructions for Cryptography)">;
214
215def HasStdExtZbbOrZbkb
216    : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
217                AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),
218                                   "'Zbb' (Basic Bit-Manipulation) or "
219                                   "'Zbkb' (Bitmanip instructions for Cryptography)">;
220
221def HasStdExtZbbOrZbpOrZbkb
222    : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
223                AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp, FeatureStdExtZbkb),
224                                   "'Zbb' (Basic Bit-Manipulation) or "
225                                   "'Zbp' (Permutation 'Zb' Instructions) or "
226                                   "'Zbkb' (Bitmanip instructions for Cryptography)">;
227
228// The Carry-less multiply subextension for cryptography is a subset of basic carry-less multiply subextension. The former should be enabled if the latter is enabled.
229def FeatureStdExtZbkc
230    : SubtargetFeature<"zbkc", "HasStdExtZbkc", "true",
231                       "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
232def HasStdExtZbkc
233    : Predicate<"Subtarget->hasStdExtZbkc()">,
234                             AssemblerPredicate<(all_of FeatureStdExtZbkc),
235                             "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
236
237def HasStdExtZbcOrZbkc
238    : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
239                AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
240                                   "'Zbc' (Carry-Less Multiplication) or "
241                                   "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
242
243def FeatureStdExtZknd
244    : SubtargetFeature<"zknd", "HasStdExtZknd", "true",
245                       "'Zknd' (NIST Suite: AES Decryption)">;
246def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
247                             AssemblerPredicate<(all_of FeatureStdExtZknd),
248                             "'Zknd' (NIST Suite: AES Decryption)">;
249
250def FeatureStdExtZkne
251    : SubtargetFeature<"zkne", "HasStdExtZkne", "true",
252                       "'Zkne' (NIST Suite: AES Encryption)">;
253def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
254                             AssemblerPredicate<(all_of FeatureStdExtZkne),
255                             "'Zkne' (NIST Suite: AES Encryption)">;
256
257// Some instructions belong to both Zknd and Zkne subextensions.
258// They should be enabled if either has been specified.
259def HasStdExtZkndOrZkne
260    : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
261                AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),
262                                   "'Zknd' (NIST Suite: AES Decryption) or "
263                                   "'Zkne' (NIST Suite: AES Encryption)">;
264
265def FeatureStdExtZknh
266    : SubtargetFeature<"zknh", "HasStdExtZknh", "true",
267                       "'Zknh' (NIST Suite: Hash Function Instructions)">;
268def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
269                             AssemblerPredicate<(all_of FeatureStdExtZknh),
270                             "'Zknh' (NIST Suite: Hash Function Instructions)">;
271
272def FeatureStdExtZksed
273    : SubtargetFeature<"zksed", "HasStdExtZksed", "true",
274                       "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
275def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
276                             AssemblerPredicate<(all_of FeatureStdExtZksed),
277                             "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
278
279def FeatureStdExtZksh
280    : SubtargetFeature<"zksh", "HasStdExtZksh", "true",
281                       "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
282def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
283                             AssemblerPredicate<(all_of FeatureStdExtZksh),
284                             "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
285
286def FeatureStdExtZkr
287    : SubtargetFeature<"zkr", "HasStdExtZkr", "true",
288                       "'Zkr' (Entropy Source Extension)">;
289def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
290                             AssemblerPredicate<(all_of FeatureStdExtZkr),
291                             "'Zkr' (Entropy Source Extension)">;
292
293def FeatureStdExtZkn
294    : SubtargetFeature<"zkn", "HasStdExtZkn", "true",
295                       "'Zkn' (NIST Algorithm Suite)",
296                       [FeatureStdExtZbkb,
297                        FeatureStdExtZbkc,
298                        FeatureStdExtZbkx,
299                        FeatureStdExtZkne,
300                        FeatureStdExtZknd,
301                        FeatureStdExtZknh]>;
302
303def FeatureStdExtZks
304    : SubtargetFeature<"zks", "HasStdExtZks", "true",
305                       "'Zks' (ShangMi Algorithm Suite)",
306                       [FeatureStdExtZbkb,
307                        FeatureStdExtZbkc,
308                        FeatureStdExtZbkx,
309                        FeatureStdExtZksed,
310                        FeatureStdExtZksh]>;
311
312def FeatureStdExtZkt
313    : SubtargetFeature<"zkt", "HasStdExtZkt", "true",
314                       "'Zkt' (Data Independent Execution Latency)">;
315
316def FeatureStdExtZk
317    : SubtargetFeature<"zk", "HasStdExtZk", "true",
318                       "'Zk' (Standard scalar cryptography extension)",
319                       [FeatureStdExtZkn,
320                        FeatureStdExtZkr,
321                        FeatureStdExtZkt]>;
322
323def FeatureNoRVCHints
324    : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
325                       "Disable RVC Hint Instructions.">;
326def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
327                  AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
328                                      "RVC Hint Instructions">;
329
330def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "ExtZvl::Zvl32b",
331                       "'Zvl' (Minimum Vector Length) 32">;
332
333foreach i = { 6-15 } in {
334    defvar I = !shl(1, i);
335    def FeatureStdExtZvl#I#b :
336        SubtargetFeature<"zvl"#I#"b", "ZvlLen", "ExtZvl::Zvl"#I#"b",
337                        "'Zvl' (Minimum Vector Length) "#I,
338                        [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
339}
340
341def FeatureStdExtZve32x
342    : SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
343                       "'Zve32x' (Vector Extensions for Embedded Processors "
344                       "with maximal 32 EEW)",
345                       [FeatureStdExtZvl32b]>;
346
347def FeatureStdExtZve32f
348    : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
349                       "'Zve32f' (Vector Extensions for Embedded Processors "
350                       "with maximal 32 EEW and F extension)",
351                       [FeatureStdExtZve32x]>;
352
353def FeatureStdExtZve64x
354    : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
355                       "'Zve64x' (Vector Extensions for Embedded Processors "
356                       "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
357
358def FeatureStdExtZve64f
359    : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
360                       "'Zve64f' (Vector Extensions for Embedded Processors "
361                       "with maximal 64 EEW and F extension)",
362                       [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
363
364def FeatureStdExtZve64d
365    : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
366                       "'Zve64d' (Vector Extensions for Embedded Processors "
367                       "with maximal 64 EEW, F and D extension)",
368                       [FeatureStdExtZve64f]>;
369
370def FeatureStdExtV
371    : SubtargetFeature<"v", "HasStdExtV", "true",
372                       "'V' (Vector Extension for Application Processors)",
373                       [FeatureStdExtZvl128b, FeatureStdExtF, FeatureStdExtD]>;
374
375def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,
376      AssemblerPredicate<
377          (any_of FeatureStdExtZve32x, FeatureStdExtV),
378          "'V' (Vector Extension for Application Processors), 'Zve32x' or "
379          "'Zve64x' (Vector Extensions for Embedded Processors)">;
380def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
381      AssemblerPredicate<
382          (any_of FeatureStdExtZve64x, FeatureStdExtV),
383          "'V' (Vector Extension for Application Processors) or 'Zve64x' "
384          "(Vector Extensions for Embedded Processors)">;
385def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
386      AssemblerPredicate<
387          (any_of FeatureStdExtZve32f, FeatureStdExtV),
388          "'V' (Vector Extension for Application Processors), 'Zve32f', "
389          "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">;
390
391def Feature64Bit
392    : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
393def IsRV64 : Predicate<"Subtarget->is64Bit()">,
394                       AssemblerPredicate<(all_of Feature64Bit),
395                       "RV64I Base Instruction Set">;
396def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
397                       AssemblerPredicate<(all_of (not Feature64Bit)),
398                       "RV32I Base Instruction Set">;
399
400defvar RV32 = DefaultMode;
401def RV64           : HwMode<"+64bit">;
402
403def FeatureRV32E
404    : SubtargetFeature<"e", "IsRV32E", "true",
405                       "Implements RV32E (provides 16 rather than 32 GPRs)">;
406def IsRV32E : Predicate<"Subtarget->isRV32E()">,
407                        AssemblerPredicate<(all_of FeatureRV32E)>;
408
409def FeatureRelax
410    : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
411                       "Enable Linker relaxation.">;
412
413foreach i = {1-31} in
414    def FeatureReserveX#i :
415        SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
416                         "true", "Reserve X"#i>;
417
418def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
419                                          "true", "Enable save/restore.">;
420
421def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
422                                   "SiFive 7-Series processors">;
423
424//===----------------------------------------------------------------------===//
425// Named operands for CSR instructions.
426//===----------------------------------------------------------------------===//
427
428include "RISCVSystemOperands.td"
429
430//===----------------------------------------------------------------------===//
431// Registers, calling conventions, instruction descriptions.
432//===----------------------------------------------------------------------===//
433
434include "RISCVSchedule.td"
435include "RISCVRegisterInfo.td"
436include "RISCVCallingConv.td"
437include "RISCVInstrInfo.td"
438include "RISCVRegisterBanks.td"
439include "RISCVSchedRocket.td"
440include "RISCVSchedSiFive7.td"
441
442//===----------------------------------------------------------------------===//
443// RISC-V processors supported.
444//===----------------------------------------------------------------------===//
445
446def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
447def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
448
449def : ProcessorModel<"rocket-rv32", RocketModel, []>;
450def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
451
452def : ProcessorModel<"sifive-7-rv32", SiFive7Model, [],
453                     [TuneSiFive7]>;
454def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit],
455                     [TuneSiFive7]>;
456
457def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM,
458                                                 FeatureStdExtC]>;
459
460def : ProcessorModel<"sifive-e21", RocketModel, [FeatureStdExtM,
461                                                 FeatureStdExtA,
462                                                 FeatureStdExtC]>;
463
464def : ProcessorModel<"sifive-e24", RocketModel, [FeatureStdExtM,
465                                                 FeatureStdExtA,
466                                                 FeatureStdExtF,
467                                                 FeatureStdExtC]>;
468
469def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
470                                                 FeatureStdExtA,
471                                                 FeatureStdExtC]>;
472
473def : ProcessorModel<"sifive-e34", RocketModel, [FeatureStdExtM,
474                                                 FeatureStdExtA,
475                                                 FeatureStdExtF,
476                                                 FeatureStdExtC]>;
477
478def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM,
479                                                  FeatureStdExtA,
480                                                  FeatureStdExtF,
481                                                  FeatureStdExtC],
482                     [TuneSiFive7]>;
483
484def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit,
485                                                 FeatureStdExtM,
486                                                 FeatureStdExtA,
487                                                 FeatureStdExtC]>;
488
489def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
490                                                 FeatureStdExtM,
491                                                 FeatureStdExtA,
492                                                 FeatureStdExtC]>;
493
494def : ProcessorModel<"sifive-s54", RocketModel, [Feature64Bit,
495                                                 FeatureStdExtM,
496                                                 FeatureStdExtA,
497                                                 FeatureStdExtF,
498                                                 FeatureStdExtD,
499                                                 FeatureStdExtC]>;
500
501def : ProcessorModel<"sifive-s76", SiFive7Model, [Feature64Bit,
502                                                  FeatureStdExtM,
503                                                  FeatureStdExtA,
504                                                  FeatureStdExtF,
505                                                  FeatureStdExtD,
506                                                  FeatureStdExtC],
507                     [TuneSiFive7]>;
508
509def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
510                                                 FeatureStdExtM,
511                                                 FeatureStdExtA,
512                                                 FeatureStdExtF,
513                                                 FeatureStdExtD,
514                                                 FeatureStdExtC]>;
515
516def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
517                                                  FeatureStdExtM,
518                                                  FeatureStdExtA,
519                                                  FeatureStdExtF,
520                                                  FeatureStdExtD,
521                                                  FeatureStdExtC],
522                     [TuneSiFive7]>;
523
524//===----------------------------------------------------------------------===//
525// Define the RISC-V target.
526//===----------------------------------------------------------------------===//
527
528def RISCVInstrInfo : InstrInfo {
529  let guessInstructionProperties = 0;
530}
531
532def RISCVAsmParser : AsmParser {
533  let ShouldEmitMatchRegisterAltName = 1;
534  let AllowDuplicateRegisterNames = 1;
535}
536
537def RISCVAsmWriter : AsmWriter {
538  int PassSubtarget = 1;
539}
540
541def RISCV : Target {
542  let InstructionSet = RISCVInstrInfo;
543  let AssemblyParsers = [RISCVAsmParser];
544  let AssemblyWriters = [RISCVAsmWriter];
545  let AllowRegisterRenaming = 1;
546}
547