1 //===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the RISCV implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H 15 16 #include "RISCVRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "RISCVGenInstrInfo.inc" 21 22 namespace llvm { 23 24 class RISCVSubtarget; 25 26 class RISCVInstrInfo : public RISCVGenInstrInfo { 27 28 public: 29 explicit RISCVInstrInfo(RISCVSubtarget &STI); 30 31 unsigned isLoadFromStackSlot(const MachineInstr &MI, 32 int &FrameIndex) const override; 33 unsigned isStoreToStackSlot(const MachineInstr &MI, 34 int &FrameIndex) const override; 35 36 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 37 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, 38 bool KillSrc) const override; 39 40 void storeRegToStackSlot(MachineBasicBlock &MBB, 41 MachineBasicBlock::iterator MBBI, Register SrcReg, 42 bool IsKill, int FrameIndex, 43 const TargetRegisterClass *RC, 44 const TargetRegisterInfo *TRI) const override; 45 46 void loadRegFromStackSlot(MachineBasicBlock &MBB, 47 MachineBasicBlock::iterator MBBI, Register DstReg, 48 int FrameIndex, const TargetRegisterClass *RC, 49 const TargetRegisterInfo *TRI) const override; 50 51 // Materializes the given integer Val into DstReg. 52 void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 53 const DebugLoc &DL, Register DstReg, uint64_t Val, 54 MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 55 56 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 57 58 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 59 MachineBasicBlock *&FBB, 60 SmallVectorImpl<MachineOperand> &Cond, 61 bool AllowModify) const override; 62 63 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 64 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 65 const DebugLoc &dl, 66 int *BytesAdded = nullptr) const override; 67 68 unsigned insertIndirectBranch(MachineBasicBlock &MBB, 69 MachineBasicBlock &NewDestBB, 70 const DebugLoc &DL, int64_t BrOffset, 71 RegScavenger *RS = nullptr) const override; 72 73 unsigned removeBranch(MachineBasicBlock &MBB, 74 int *BytesRemoved = nullptr) const override; 75 76 bool 77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 78 79 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 80 81 bool isBranchOffsetInRange(unsigned BranchOpc, 82 int64_t BrOffset) const override; 83 84 bool isAsCheapAsAMove(const MachineInstr &MI) const override; 85 86 bool verifyInstruction(const MachineInstr &MI, 87 StringRef &ErrInfo) const override; 88 89 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 90 const MachineOperand *&BaseOp, 91 int64_t &Offset, unsigned &Width, 92 const TargetRegisterInfo *TRI) const; 93 94 bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 95 const MachineInstr &MIb) const override; 96 97 98 std::pair<unsigned, unsigned> 99 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 100 101 ArrayRef<std::pair<unsigned, const char *>> 102 getSerializableDirectMachineOperandTargetFlags() const override; 103 104 // Return true if the function can safely be outlined from. 105 virtual bool 106 isFunctionSafeToOutlineFrom(MachineFunction &MF, 107 bool OutlineFromLinkOnceODRs) const override; 108 109 // Return true if MBB is safe to outline from, and return any target-specific 110 // information in Flags. 111 virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, 112 unsigned &Flags) const override; 113 114 // Calculate target-specific information for a set of outlining candidates. 115 outliner::OutlinedFunction getOutliningCandidateInfo( 116 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override; 117 118 // Return if/how a given MachineInstr should be outlined. 119 virtual outliner::InstrType 120 getOutliningType(MachineBasicBlock::iterator &MBBI, 121 unsigned Flags) const override; 122 123 // Insert a custom frame for outlined functions. 124 virtual void 125 buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, 126 const outliner::OutlinedFunction &OF) const override; 127 128 // Insert a call to an outlined function into a given basic block. 129 virtual MachineBasicBlock::iterator 130 insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 131 MachineBasicBlock::iterator &It, MachineFunction &MF, 132 const outliner::Candidate &C) const override; 133 protected: 134 const RISCVSubtarget &STI; 135 }; 136 137 namespace RISCV { 138 // Match with the definitions in RISCVInstrFormatsV.td 139 enum RVVConstraintType { 140 NoConstraint = 0, 141 WidenV = 1, 142 WidenW = 2, 143 WidenCvt = 3, 144 Narrow = 4, 145 Iota = 5, 146 SlideUp = 6, 147 Vrgather = 7, 148 Vcompress = 8, 149 150 ConstraintOffset = 5, 151 ConstraintMask = 0b1111 152 }; 153 } // end namespace RISCV 154 155 } // end namespace llvm 156 #endif 157