1//===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'F', 10// Single-Precision Floating-Point instruction set extension. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVFMV_W_X_RV64 19 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>; 20def SDT_RISCVFMV_X_ANYEXTW_RV64 21 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>; 22def STD_RISCVFCVT_W_RV64 23 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisFP<1>]>; 24 25def riscv_fmv_w_x_rv64 26 : SDNode<"RISCVISD::FMV_W_X_RV64", SDT_RISCVFMV_W_X_RV64>; 27def riscv_fmv_x_anyextw_rv64 28 : SDNode<"RISCVISD::FMV_X_ANYEXTW_RV64", SDT_RISCVFMV_X_ANYEXTW_RV64>; 29def riscv_fcvt_w_rv64 30 : SDNode<"RISCVISD::FCVT_W_RV64", STD_RISCVFCVT_W_RV64>; 31def riscv_fcvt_wu_rv64 32 : SDNode<"RISCVISD::FCVT_WU_RV64", STD_RISCVFCVT_W_RV64>; 33 34//===----------------------------------------------------------------------===// 35// Operand and SDNode transformation definitions. 36//===----------------------------------------------------------------------===// 37 38// Floating-point rounding mode 39 40def FRMArg : AsmOperandClass { 41 let Name = "FRMArg"; 42 let RenderMethod = "addFRMArgOperands"; 43 let DiagnosticType = "InvalidFRMArg"; 44} 45 46def frmarg : Operand<XLenVT> { 47 let ParserMatchClass = FRMArg; 48 let PrintMethod = "printFRMArg"; 49 let DecoderMethod = "decodeFRMArg"; 50} 51 52//===----------------------------------------------------------------------===// 53// Instruction class templates 54//===----------------------------------------------------------------------===// 55 56let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 57class FPFMAS_rrr_frm<RISCVOpcode opcode, string opcodestr> 58 : RVInstR4Frm<0b00, opcode, (outs FPR32:$rd), 59 (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3), 60 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 61 62class FPFMASDynFrmAlias<FPFMAS_rrr_frm Inst, string OpcodeStr> 63 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 64 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 65 66let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 67class FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 68 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd), 69 (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">; 70 71let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 72class FPALUS_rr_frm<bits<7> funct7, string opcodestr> 73 : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR32:$rd), 74 (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr, 75 "$rd, $rs1, $rs2, $funct3">; 76 77class FPALUSDynFrmAlias<FPALUS_rr_frm Inst, string OpcodeStr> 78 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 79 (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>; 80 81let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 82class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty, 83 RegisterClass rs1ty, string opcodestr> 84 : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1), 85 opcodestr, "$rd, $rs1">; 86 87let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 88class FPUnaryOp_r_frm<bits<7> funct7, RegisterClass rdty, RegisterClass rs1ty, 89 string opcodestr> 90 : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd), 91 (ins rs1ty:$rs1, frmarg:$funct3), opcodestr, 92 "$rd, $rs1, $funct3">; 93 94class FPUnaryOpDynFrmAlias<FPUnaryOp_r_frm Inst, string OpcodeStr, 95 RegisterClass rdty, RegisterClass rs1ty> 96 : InstAlias<OpcodeStr#" $rd, $rs1", 97 (Inst rdty:$rd, rs1ty:$rs1, 0b111)>; 98 99let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 100class FPCmpS_rr<bits<3> funct3, string opcodestr> 101 : RVInstR<0b1010000, funct3, OPC_OP_FP, (outs GPR:$rd), 102 (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">, 103 Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>; 104 105//===----------------------------------------------------------------------===// 106// Instructions 107//===----------------------------------------------------------------------===// 108 109let Predicates = [HasStdExtF] in { 110let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 111def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd), 112 (ins GPR:$rs1, simm12:$imm12), 113 "flw", "$rd, ${imm12}(${rs1})">, 114 Sched<[WriteFLD32, ReadFMemBase]>; 115 116// Operands for stores are in the order srcreg, base, offset rather than 117// reflecting the order these fields are specified in the instruction 118// encoding. 119let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 120def FSW : RVInstS<0b010, OPC_STORE_FP, (outs), 121 (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12), 122 "fsw", "$rs2, ${imm12}(${rs1})">, 123 Sched<[WriteFST32, ReadStoreData, ReadFMemBase]>; 124 125def FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">, 126 Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; 127def : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">; 128def FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">, 129 Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; 130def : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">; 131def FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">, 132 Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; 133def : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">; 134def FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">, 135 Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>; 136def : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">; 137 138def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">, 139 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; 140def : FPALUSDynFrmAlias<FADD_S, "fadd.s">; 141def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">, 142 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>; 143def : FPALUSDynFrmAlias<FSUB_S, "fsub.s">; 144def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">, 145 Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>; 146def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">; 147def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">, 148 Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>; 149def : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">; 150 151def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">, 152 Sched<[WriteFSqrt32, ReadFSqrt32]> { 153 let rs2 = 0b00000; 154} 155def : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>; 156 157def FSGNJ_S : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">, 158 Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>; 159def FSGNJN_S : FPALUS_rr<0b0010000, 0b001, "fsgnjn.s">, 160 Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>; 161def FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">, 162 Sched<[WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32]>; 163def FMIN_S : FPALUS_rr<0b0010100, 0b000, "fmin.s">, 164 Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>; 165def FMAX_S : FPALUS_rr<0b0010100, 0b001, "fmax.s">, 166 Sched<[WriteFMinMax32, ReadFMinMax32, ReadFMinMax32]>; 167 168def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.w.s">, 169 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> { 170 let rs2 = 0b00000; 171} 172def : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>; 173 174def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.wu.s">, 175 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]> { 176 let rs2 = 0b00001; 177} 178def : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>; 179 180def FMV_X_W : FPUnaryOp_r<0b1110000, 0b000, GPR, FPR32, "fmv.x.w">, 181 Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]> { 182 let rs2 = 0b00000; 183} 184 185def FEQ_S : FPCmpS_rr<0b010, "feq.s">; 186def FLT_S : FPCmpS_rr<0b001, "flt.s">; 187def FLE_S : FPCmpS_rr<0b000, "fle.s">; 188 189def FCLASS_S : FPUnaryOp_r<0b1110000, 0b001, GPR, FPR32, "fclass.s">, 190 Sched<[WriteFClass32, ReadFClass32]> { 191 let rs2 = 0b00000; 192} 193 194def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.w">, 195 Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> { 196 let rs2 = 0b00000; 197} 198def : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>; 199 200def FCVT_S_WU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.wu">, 201 Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]> { 202 let rs2 = 0b00001; 203} 204def : FPUnaryOpDynFrmAlias<FCVT_S_WU, "fcvt.s.wu", FPR32, GPR>; 205 206def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x">, 207 Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]> { 208 let rs2 = 0b00000; 209} 210} // Predicates = [HasStdExtF] 211 212let Predicates = [HasStdExtF, IsRV64] in { 213def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s">, 214 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> { 215 let rs2 = 0b00010; 216} 217def : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>; 218 219def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s">, 220 Sched<[WriteFCvtF32ToI64, ReadFCvtF32ToI64]> { 221 let rs2 = 0b00011; 222} 223def : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>; 224 225def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l">, 226 Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> { 227 let rs2 = 0b00010; 228} 229def : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>; 230 231def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu">, 232 Sched<[WriteFCvtI64ToF32, ReadFCvtI64ToF32]> { 233 let rs2 = 0b00011; 234} 235def : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>; 236} // Predicates = [HasStdExtF, IsRV64] 237 238//===----------------------------------------------------------------------===// 239// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 240//===----------------------------------------------------------------------===// 241 242let Predicates = [HasStdExtF] in { 243def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>; 244def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>; 245 246def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 247def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 248def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; 249 250// fgt.s/fge.s are recognised by the GNU assembler but the canonical 251// flt.s/fle.s forms will always be printed. Therefore, set a zero weight. 252def : InstAlias<"fgt.s $rd, $rs, $rt", 253 (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 254def : InstAlias<"fge.s $rd, $rs, $rt", 255 (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; 256 257// The following csr instructions actually alias instructions from the base ISA. 258// However, it only makes sense to support them when the F extension is enabled. 259// NOTE: "frcsr", "frrm", and "frflags" are more specialized version of "csrr". 260def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 2>; 261def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>; 262def : InstAlias<"fscsr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 2>; 263 264// frsr, fssr are obsolete aliases replaced by frcsr, fscsr, so give them 265// zero weight. 266def : InstAlias<"frsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 0>; 267def : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs), 0>; 268def : InstAlias<"fssr $rs", (CSRRW X0, SysRegFCSR.Encoding, GPR:$rs), 0>; 269 270def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, SysRegFRM.Encoding, X0), 2>; 271def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, SysRegFRM.Encoding, GPR:$rs)>; 272def : InstAlias<"fsrm $rs", (CSRRW X0, SysRegFRM.Encoding, GPR:$rs), 2>; 273def : InstAlias<"fsrmi $rd, $imm", (CSRRWI GPR:$rd, SysRegFRM.Encoding, uimm5:$imm)>; 274def : InstAlias<"fsrmi $imm", (CSRRWI X0, SysRegFRM.Encoding, uimm5:$imm), 2>; 275 276def : InstAlias<"frflags $rd", (CSRRS GPR:$rd, SysRegFFLAGS.Encoding, X0), 2>; 277def : InstAlias<"fsflags $rd, $rs", (CSRRW GPR:$rd, SysRegFFLAGS.Encoding, GPR:$rs)>; 278def : InstAlias<"fsflags $rs", (CSRRW X0, SysRegFFLAGS.Encoding, GPR:$rs), 2>; 279def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, SysRegFFLAGS.Encoding, uimm5:$imm)>; 280def : InstAlias<"fsflagsi $imm", (CSRRWI X0, SysRegFFLAGS.Encoding, uimm5:$imm), 2>; 281 282// fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both 283// spellings should be supported by standard tools. 284def : MnemonicAlias<"fmv.s.x", "fmv.w.x">; 285def : MnemonicAlias<"fmv.x.s", "fmv.x.w">; 286 287def PseudoFLW : PseudoFloatLoad<"flw", FPR32>; 288def PseudoFSW : PseudoStore<"fsw", FPR32>; 289} // Predicates = [HasStdExtF] 290 291//===----------------------------------------------------------------------===// 292// Pseudo-instructions and codegen patterns 293//===----------------------------------------------------------------------===// 294 295/// Floating point constants 296def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 297 298/// Generic pattern classes 299class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst> 300 : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>; 301 302class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst> 303 : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>; 304 305let Predicates = [HasStdExtF] in { 306 307/// Float constants 308def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>; 309 310/// Float conversion operations 311 312// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 313// are defined later. 314 315/// Float arithmetic operations 316 317def : PatFpr32Fpr32DynFrm<fadd, FADD_S>; 318def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>; 319def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>; 320def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>; 321 322def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>; 323 324def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>; 325def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>; 326 327def : PatFpr32Fpr32<fcopysign, FSGNJ_S>; 328def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>; 329 330// fmadd: rs1 * rs2 + rs3 331def : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3), 332 (FMADD_S $rs1, $rs2, $rs3, 0b111)>; 333 334// fmsub: rs1 * rs2 - rs3 335def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)), 336 (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 337 338// fnmsub: -rs1 * rs2 + rs3 339def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3), 340 (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 341 342// fnmadd: -rs1 * rs2 - rs3 343def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), 344 (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; 345 346// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches 347// LLVM's fminnum and fmaxnum 348// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 349def : PatFpr32Fpr32<fminnum, FMIN_S>; 350def : PatFpr32Fpr32<fmaxnum, FMAX_S>; 351 352/// Setcc 353 354def : PatFpr32Fpr32<seteq, FEQ_S>; 355def : PatFpr32Fpr32<setoeq, FEQ_S>; 356def : PatFpr32Fpr32<setlt, FLT_S>; 357def : PatFpr32Fpr32<setolt, FLT_S>; 358def : PatFpr32Fpr32<setle, FLE_S>; 359def : PatFpr32Fpr32<setole, FLE_S>; 360 361def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>; 362 363/// Loads 364 365defm : LdPat<load, FLW, f32>; 366 367/// Stores 368 369defm : StPat<store, FSW, FPR32, f32>; 370 371} // Predicates = [HasStdExtF] 372 373let Predicates = [HasStdExtF, IsRV32] in { 374// Moves (no conversion) 375def : Pat<(bitconvert (i32 GPR:$rs1)), (FMV_W_X GPR:$rs1)>; 376def : Pat<(i32 (bitconvert FPR32:$rs1)), (FMV_X_W FPR32:$rs1)>; 377 378// float->[u]int. Round-to-zero must be used. 379def : Pat<(i32 (fp_to_sint FPR32:$rs1)), (FCVT_W_S $rs1, 0b001)>; 380def : Pat<(i32 (fp_to_uint FPR32:$rs1)), (FCVT_WU_S $rs1, 0b001)>; 381 382// float->int32 with current rounding mode. 383def : Pat<(i32 (lrint FPR32:$rs1)), (FCVT_W_S $rs1, 0b111)>; 384 385// float->int32 rounded to nearest with ties rounded away from zero. 386def : Pat<(i32 (lround FPR32:$rs1)), (FCVT_W_S $rs1, 0b100)>; 387 388// [u]int->float. Match GCC and default to using dynamic rounding mode. 389def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>; 390def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; 391} // Predicates = [HasStdExtF, IsRV32] 392 393let Predicates = [HasStdExtF, IsRV64] in { 394// Moves (no conversion) 395def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>; 396def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>; 397def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32), 398 (FMV_X_W FPR32:$src)>; 399 400// Use target specific isd nodes to help us remember the result is sign 401// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 402// duplicated if it has another user that didn't need the sign_extend. 403def : Pat<(riscv_fcvt_w_rv64 FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>; 404def : Pat<(riscv_fcvt_wu_rv64 FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>; 405 406// float->[u]int64. Round-to-zero must be used. 407def : Pat<(i64 (fp_to_sint FPR32:$rs1)), (FCVT_L_S $rs1, 0b001)>; 408def : Pat<(i64 (fp_to_uint FPR32:$rs1)), (FCVT_LU_S $rs1, 0b001)>; 409 410// float->int64 with current rounding mode. 411def : Pat<(i64 (lrint FPR32:$rs1)), (FCVT_L_S $rs1, 0b111)>; 412def : Pat<(i64 (llrint FPR32:$rs1)), (FCVT_L_S $rs1, 0b111)>; 413 414// float->int64 rounded to neartest with ties rounded away from zero. 415def : Pat<(i64 (lround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>; 416def : Pat<(i64 (llround FPR32:$rs1)), (FCVT_L_S $rs1, 0b100)>; 417 418// [u]int->fp. Match GCC and default to using dynamic rounding mode. 419def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_S_W $rs1, 0b111)>; 420def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_S_WU $rs1, 0b111)>; 421def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_S_L $rs1, 0b111)>; 422def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_S_LU $rs1, 0b111)>; 423} // Predicates = [HasStdExtF, IsRV64] 424