1//===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the RISC-V register files 11//===----------------------------------------------------------------------===// 12 13let Namespace = "RISCV" in { 14class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 15 let HWEncoding{4-0} = Enc; 16 let AltNames = alt; 17} 18 19class RISCVReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 20 let HWEncoding{4-0} = Enc; 21 let AltNames = alt; 22} 23 24// Because RISCVReg64 register have AsmName and AltNames that alias with their 25// 32-bit sub-register, RISCVAsmParser will need to coerce a register number 26// from a RISCVReg32 to the equivalent RISCVReg64 when appropriate. 27def sub_32 : SubRegIndex<32>; 28class RISCVReg64<RISCVReg32 subreg> : Register<""> { 29 let HWEncoding{4-0} = subreg.HWEncoding{4-0}; 30 let SubRegs = [subreg]; 31 let SubRegIndices = [sub_32]; 32 let AsmName = subreg.AsmName; 33 let AltNames = subreg.AltNames; 34} 35 36class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs, 37 list<string> alt = []> 38 : RegisterWithSubRegs<n, subregs> { 39 let HWEncoding{4-0} = Enc; 40 let AltNames = alt; 41} 42 43def ABIRegAltName : RegAltNameIndex; 44 45def sub_vrm2 : SubRegIndex<64, -1>; 46def sub_vrm2_hi : SubRegIndex<64, -1>; 47def sub_vrm4 : SubRegIndex<128, -1>; 48def sub_vrm4_hi : SubRegIndex<128, -1>; 49def sub_vrm8 : SubRegIndex<256, -1>; 50def sub_vrm8_hi : SubRegIndex<256, -1>; 51} // Namespace = "RISCV" 52 53// Integer registers 54// CostPerUse is set higher for registers that may not be compressible as they 55// are not part of GPRC, the most restrictive register class used by the 56// compressed instruction set. This will influence the greedy register 57// allocator to reduce the use of registers that can't be encoded in 16 bit 58// instructions. This affects register allocation even when compressed 59// instruction isn't targeted, we see no major negative codegen impact. 60 61let RegAltNameIndices = [ABIRegAltName] in { 62 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; 63 let CostPerUse = 1 in { 64 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; 65 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; 66 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; 67 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>; 68 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; 69 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; 70 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>; 71 } 72 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>; 73 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>; 74 def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>; 75 def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>; 76 def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>; 77 def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>; 78 def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>; 79 def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>; 80 let CostPerUse = 1 in { 81 def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>; 82 def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>; 83 def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>; 84 def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>; 85 def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>; 86 def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>; 87 def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>; 88 def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>; 89 def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>; 90 def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>; 91 def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>; 92 def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>; 93 def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>; 94 def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>; 95 def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>; 96 def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>; 97 } 98} 99 100def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode], 101 [i32, i64, i32]>; 102 103// The order of registers represents the preferred allocation sequence. 104// Registers are listed in the order caller-save, callee-save, specials. 105def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add 106 (sequence "X%u", 10, 17), 107 (sequence "X%u", 5, 7), 108 (sequence "X%u", 28, 31), 109 (sequence "X%u", 8, 9), 110 (sequence "X%u", 18, 27), 111 (sequence "X%u", 0, 4) 112 )> { 113 let RegInfos = RegInfoByHwMode< 114 [RV32, RV64, DefaultMode], 115 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 116} 117 118def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> { 119 let RegInfos = RegInfoByHwMode< 120 [RV32, RV64, DefaultMode], 121 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 122} 123 124// The order of registers represents the preferred allocation sequence. 125// Registers are listed in the order caller-save, callee-save, specials. 126def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add 127 (sequence "X%u", 10, 17), 128 (sequence "X%u", 5, 7), 129 (sequence "X%u", 28, 31), 130 (sequence "X%u", 8, 9), 131 (sequence "X%u", 18, 27), 132 (sequence "X%u", 1, 4) 133 )> { 134 let RegInfos = RegInfoByHwMode< 135 [RV32, RV64, DefaultMode], 136 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 137} 138 139def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add 140 (sequence "X%u", 10, 17), 141 (sequence "X%u", 5, 7), 142 (sequence "X%u", 28, 31), 143 (sequence "X%u", 8, 9), 144 (sequence "X%u", 18, 27), 145 X1, X3, X4 146 )> { 147 let RegInfos = RegInfoByHwMode< 148 [RV32, RV64, DefaultMode], 149 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 150} 151 152def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add 153 (sequence "X%u", 10, 15), 154 (sequence "X%u", 8, 9) 155 )> { 156 let RegInfos = RegInfoByHwMode< 157 [RV32, RV64, DefaultMode], 158 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 159} 160 161// For indirect tail calls, we can't use callee-saved registers, as they are 162// restored to the saved value before the tail call, which would clobber a call 163// address. 164def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add 165 (sequence "X%u", 5, 7), 166 (sequence "X%u", 10, 17), 167 (sequence "X%u", 28, 31) 168 )> { 169 let RegInfos = RegInfoByHwMode< 170 [RV32, RV64, DefaultMode], 171 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 172} 173 174def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> { 175 let RegInfos = RegInfoByHwMode< 176 [RV32, RV64, DefaultMode], 177 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 178} 179 180// Floating point registers 181let RegAltNameIndices = [ABIRegAltName] in { 182 def F0_F : RISCVReg32<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; 183 def F1_F : RISCVReg32<1, "f1", ["ft1"]>, DwarfRegNum<[33]>; 184 def F2_F : RISCVReg32<2, "f2", ["ft2"]>, DwarfRegNum<[34]>; 185 def F3_F : RISCVReg32<3, "f3", ["ft3"]>, DwarfRegNum<[35]>; 186 def F4_F : RISCVReg32<4, "f4", ["ft4"]>, DwarfRegNum<[36]>; 187 def F5_F : RISCVReg32<5, "f5", ["ft5"]>, DwarfRegNum<[37]>; 188 def F6_F : RISCVReg32<6, "f6", ["ft6"]>, DwarfRegNum<[38]>; 189 def F7_F : RISCVReg32<7, "f7", ["ft7"]>, DwarfRegNum<[39]>; 190 def F8_F : RISCVReg32<8, "f8", ["fs0"]>, DwarfRegNum<[40]>; 191 def F9_F : RISCVReg32<9, "f9", ["fs1"]>, DwarfRegNum<[41]>; 192 def F10_F : RISCVReg32<10,"f10", ["fa0"]>, DwarfRegNum<[42]>; 193 def F11_F : RISCVReg32<11,"f11", ["fa1"]>, DwarfRegNum<[43]>; 194 def F12_F : RISCVReg32<12,"f12", ["fa2"]>, DwarfRegNum<[44]>; 195 def F13_F : RISCVReg32<13,"f13", ["fa3"]>, DwarfRegNum<[45]>; 196 def F14_F : RISCVReg32<14,"f14", ["fa4"]>, DwarfRegNum<[46]>; 197 def F15_F : RISCVReg32<15,"f15", ["fa5"]>, DwarfRegNum<[47]>; 198 def F16_F : RISCVReg32<16,"f16", ["fa6"]>, DwarfRegNum<[48]>; 199 def F17_F : RISCVReg32<17,"f17", ["fa7"]>, DwarfRegNum<[49]>; 200 def F18_F : RISCVReg32<18,"f18", ["fs2"]>, DwarfRegNum<[50]>; 201 def F19_F : RISCVReg32<19,"f19", ["fs3"]>, DwarfRegNum<[51]>; 202 def F20_F : RISCVReg32<20,"f20", ["fs4"]>, DwarfRegNum<[52]>; 203 def F21_F : RISCVReg32<21,"f21", ["fs5"]>, DwarfRegNum<[53]>; 204 def F22_F : RISCVReg32<22,"f22", ["fs6"]>, DwarfRegNum<[54]>; 205 def F23_F : RISCVReg32<23,"f23", ["fs7"]>, DwarfRegNum<[55]>; 206 def F24_F : RISCVReg32<24,"f24", ["fs8"]>, DwarfRegNum<[56]>; 207 def F25_F : RISCVReg32<25,"f25", ["fs9"]>, DwarfRegNum<[57]>; 208 def F26_F : RISCVReg32<26,"f26", ["fs10"]>, DwarfRegNum<[58]>; 209 def F27_F : RISCVReg32<27,"f27", ["fs11"]>, DwarfRegNum<[59]>; 210 def F28_F : RISCVReg32<28,"f28", ["ft8"]>, DwarfRegNum<[60]>; 211 def F29_F : RISCVReg32<29,"f29", ["ft9"]>, DwarfRegNum<[61]>; 212 def F30_F : RISCVReg32<30,"f30", ["ft10"]>, DwarfRegNum<[62]>; 213 def F31_F : RISCVReg32<31,"f31", ["ft11"]>, DwarfRegNum<[63]>; 214 215 foreach Index = 0-31 in { 216 def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>, 217 DwarfRegNum<[!add(Index, 32)]>; 218 } 219} 220 221// The order of registers represents the preferred allocation sequence, 222// meaning caller-save regs are listed before callee-save. 223def FPR32 : RegisterClass<"RISCV", [f32], 32, (add 224 (sequence "F%u_F", 0, 7), 225 (sequence "F%u_F", 10, 17), 226 (sequence "F%u_F", 28, 31), 227 (sequence "F%u_F", 8, 9), 228 (sequence "F%u_F", 18, 27) 229)>; 230 231def FPR32C : RegisterClass<"RISCV", [f32], 32, (add 232 (sequence "F%u_F", 10, 15), 233 (sequence "F%u_F", 8, 9) 234)>; 235 236// The order of registers represents the preferred allocation sequence, 237// meaning caller-save regs are listed before callee-save. 238def FPR64 : RegisterClass<"RISCV", [f64], 64, (add 239 (sequence "F%u_D", 0, 7), 240 (sequence "F%u_D", 10, 17), 241 (sequence "F%u_D", 28, 31), 242 (sequence "F%u_D", 8, 9), 243 (sequence "F%u_D", 18, 27) 244)>; 245 246def FPR64C : RegisterClass<"RISCV", [f64], 64, (add 247 (sequence "F%u_D", 10, 15), 248 (sequence "F%u_D", 8, 9) 249)>; 250 251// Vector registers 252let RegAltNameIndices = [ABIRegAltName] in { 253 foreach Index = 0-31 in { 254 def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 64)]>; 255 } 256 257 foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 258 24, 26, 28, 30] in { 259 def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index, 260 [!cast<Register>("V"#Index), 261 !cast<Register>("V"#!add(Index, 1))], 262 ["v"#Index]>, 263 DwarfRegAlias<!cast<Register>("V"#Index)> { 264 let SubRegIndices = [sub_vrm2, sub_vrm2_hi]; 265 } 266 } 267 268 foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in { 269 def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index, 270 [!cast<Register>("V"#Index#"M2"), 271 !cast<Register>("V"#!add(Index, 2)#"M2")], 272 ["v"#Index]>, 273 DwarfRegAlias<!cast<Register>("V"#Index)> { 274 let SubRegIndices = [sub_vrm4, sub_vrm4_hi]; 275 } 276 } 277 278 foreach Index = [0, 8, 16, 24] in { 279 def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index, 280 [!cast<Register>("V"#Index#"M4"), 281 !cast<Register>("V"#!add(Index, 4)#"M4")], 282 ["v"#Index]>, 283 DwarfRegAlias<!cast<Register>("V"#Index)> { 284 let SubRegIndices = [sub_vrm8, sub_vrm8_hi]; 285 } 286 } 287 288 def VTYPE : RISCVReg<0, "vtype", ["vtype"]>; 289 def VL : RISCVReg<0, "vl", ["vl"]>; 290} 291 292class RegisterTypes<list<ValueType> reg_types> { 293 list<ValueType> types = reg_types; 294} 295 296// The order of registers represents the preferred allocation sequence, 297// meaning caller-save regs are listed before callee-save. 298def VR : RegisterClass<"RISCV", [nxv8i8, nxv4i16, nxv2i32, nxv1i64], 299 64, (add 300 (sequence "V%u", 25, 31), 301 (sequence "V%u", 8, 24), 302 (sequence "V%u", 0, 7) 303 )> { 304 let Size = 64; 305} 306 307def VRM2 : RegisterClass<"RISCV", [nxv16i8, nxv8i16, nxv4i32, nxv2i64], 64, 308 (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2, 309 V18M2, V20M2, V22M2, V24M2, V0M2, V2M2, V4M2, V6M2)> { 310 let Size = 128; 311} 312 313def VRM4 : RegisterClass<"RISCV", [nxv32i8, nxv16i16, nxv8i32, nxv4i64], 64, 314 (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V0M4, V4M4)> { 315 let Size = 256; 316} 317 318def VRM8 : RegisterClass<"RISCV", [nxv32i16, nxv16i32, nxv8i64], 64, 319 (add V8M8, V16M8, V24M8, V0M8)> { 320 let Size = 512; 321} 322 323def VMaskVT : RegisterTypes<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, nxv32i1]>; 324 325def VM : RegisterClass<"RISCV", VMaskVT.types, 64, (add 326 (sequence "V%u", 25, 31), 327 (sequence "V%u", 8, 24), 328 (sequence "V%u", 0, 7))> { 329 let Size = 64; 330} 331 332def VMV0 : RegisterClass<"RISCV", VMaskVT.types, 64, (add V0)> { 333 let Size = 64; 334} 335