1//===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the RISC-V register files 11//===----------------------------------------------------------------------===// 12 13let Namespace = "RISCV" in { 14class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 15 let HWEncoding{4-0} = Enc; 16 let AltNames = alt; 17} 18 19class RISCVReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 20 let HWEncoding{4-0} = Enc; 21 let AltNames = alt; 22} 23 24// Because RISCVReg64 register have AsmName and AltNames that alias with their 25// 32-bit sub-register, RISCVAsmParser will need to coerce a register number 26// from a RISCVReg32 to the equivalent RISCVReg64 when appropriate. 27def sub_32 : SubRegIndex<32>; 28class RISCVReg64<RISCVReg32 subreg> : Register<""> { 29 let HWEncoding{4-0} = subreg.HWEncoding{4-0}; 30 let SubRegs = [subreg]; 31 let SubRegIndices = [sub_32]; 32 let AsmName = subreg.AsmName; 33 let AltNames = subreg.AltNames; 34} 35 36def ABIRegAltName : RegAltNameIndex; 37} // Namespace = "RISCV" 38 39// Integer registers 40// CostPerUse is set higher for registers that may not be compressible as they 41// are not part of GPRC, the most restrictive register class used by the 42// compressed instruction set. This will influence the greedy register 43// allocator to reduce the use of registers that can't be encoded in 16 bit 44// instructions. This affects register allocation even when compressed 45// instruction isn't targeted, we see no major negative codegen impact. 46 47let RegAltNameIndices = [ABIRegAltName] in { 48 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; 49 let CostPerUse = 1 in { 50 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; 51 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; 52 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; 53 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>; 54 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; 55 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; 56 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>; 57 } 58 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>; 59 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>; 60 def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>; 61 def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>; 62 def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>; 63 def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>; 64 def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>; 65 def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>; 66 let CostPerUse = 1 in { 67 def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>; 68 def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>; 69 def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>; 70 def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>; 71 def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>; 72 def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>; 73 def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>; 74 def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>; 75 def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>; 76 def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>; 77 def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>; 78 def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>; 79 def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>; 80 def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>; 81 def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>; 82 def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>; 83 } 84} 85 86def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode], 87 [i32, i64, i32]>; 88 89// The order of registers represents the preferred allocation sequence. 90// Registers are listed in the order caller-save, callee-save, specials. 91def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add 92 (sequence "X%u", 10, 17), 93 (sequence "X%u", 5, 7), 94 (sequence "X%u", 28, 31), 95 (sequence "X%u", 8, 9), 96 (sequence "X%u", 18, 27), 97 (sequence "X%u", 0, 4) 98 )> { 99 let RegInfos = RegInfoByHwMode< 100 [RV32, RV64, DefaultMode], 101 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 102} 103 104// The order of registers represents the preferred allocation sequence. 105// Registers are listed in the order caller-save, callee-save, specials. 106def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add 107 (sequence "X%u", 10, 17), 108 (sequence "X%u", 5, 7), 109 (sequence "X%u", 28, 31), 110 (sequence "X%u", 8, 9), 111 (sequence "X%u", 18, 27), 112 (sequence "X%u", 1, 4) 113 )> { 114 let RegInfos = RegInfoByHwMode< 115 [RV32, RV64, DefaultMode], 116 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 117} 118 119def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add 120 (sequence "X%u", 10, 17), 121 (sequence "X%u", 5, 7), 122 (sequence "X%u", 28, 31), 123 (sequence "X%u", 8, 9), 124 (sequence "X%u", 18, 27), 125 X1, X3, X4 126 )> { 127 let RegInfos = RegInfoByHwMode< 128 [RV32, RV64, DefaultMode], 129 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 130} 131 132def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add 133 (sequence "X%u", 10, 15), 134 (sequence "X%u", 8, 9) 135 )> { 136 let RegInfos = RegInfoByHwMode< 137 [RV32, RV64, DefaultMode], 138 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 139} 140 141// For indirect tail calls, we can't use callee-saved registers, as they are 142// restored to the saved value before the tail call, which would clobber a call 143// address. 144def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add 145 (sequence "X%u", 5, 7), 146 (sequence "X%u", 10, 17), 147 (sequence "X%u", 28, 31) 148 )> { 149 let RegInfos = RegInfoByHwMode< 150 [RV32, RV64, DefaultMode], 151 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 152} 153 154def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> { 155 let RegInfos = RegInfoByHwMode< 156 [RV32, RV64, DefaultMode], 157 [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; 158} 159 160// Floating point registers 161let RegAltNameIndices = [ABIRegAltName] in { 162 def F0_32 : RISCVReg32<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; 163 def F1_32 : RISCVReg32<1, "f1", ["ft1"]>, DwarfRegNum<[33]>; 164 def F2_32 : RISCVReg32<2, "f2", ["ft2"]>, DwarfRegNum<[34]>; 165 def F3_32 : RISCVReg32<3, "f3", ["ft3"]>, DwarfRegNum<[35]>; 166 def F4_32 : RISCVReg32<4, "f4", ["ft4"]>, DwarfRegNum<[36]>; 167 def F5_32 : RISCVReg32<5, "f5", ["ft5"]>, DwarfRegNum<[37]>; 168 def F6_32 : RISCVReg32<6, "f6", ["ft6"]>, DwarfRegNum<[38]>; 169 def F7_32 : RISCVReg32<7, "f7", ["ft7"]>, DwarfRegNum<[39]>; 170 def F8_32 : RISCVReg32<8, "f8", ["fs0"]>, DwarfRegNum<[40]>; 171 def F9_32 : RISCVReg32<9, "f9", ["fs1"]>, DwarfRegNum<[41]>; 172 def F10_32 : RISCVReg32<10,"f10", ["fa0"]>, DwarfRegNum<[42]>; 173 def F11_32 : RISCVReg32<11,"f11", ["fa1"]>, DwarfRegNum<[43]>; 174 def F12_32 : RISCVReg32<12,"f12", ["fa2"]>, DwarfRegNum<[44]>; 175 def F13_32 : RISCVReg32<13,"f13", ["fa3"]>, DwarfRegNum<[45]>; 176 def F14_32 : RISCVReg32<14,"f14", ["fa4"]>, DwarfRegNum<[46]>; 177 def F15_32 : RISCVReg32<15,"f15", ["fa5"]>, DwarfRegNum<[47]>; 178 def F16_32 : RISCVReg32<16,"f16", ["fa6"]>, DwarfRegNum<[48]>; 179 def F17_32 : RISCVReg32<17,"f17", ["fa7"]>, DwarfRegNum<[49]>; 180 def F18_32 : RISCVReg32<18,"f18", ["fs2"]>, DwarfRegNum<[50]>; 181 def F19_32 : RISCVReg32<19,"f19", ["fs3"]>, DwarfRegNum<[51]>; 182 def F20_32 : RISCVReg32<20,"f20", ["fs4"]>, DwarfRegNum<[52]>; 183 def F21_32 : RISCVReg32<21,"f21", ["fs5"]>, DwarfRegNum<[53]>; 184 def F22_32 : RISCVReg32<22,"f22", ["fs6"]>, DwarfRegNum<[54]>; 185 def F23_32 : RISCVReg32<23,"f23", ["fs7"]>, DwarfRegNum<[55]>; 186 def F24_32 : RISCVReg32<24,"f24", ["fs8"]>, DwarfRegNum<[56]>; 187 def F25_32 : RISCVReg32<25,"f25", ["fs9"]>, DwarfRegNum<[57]>; 188 def F26_32 : RISCVReg32<26,"f26", ["fs10"]>, DwarfRegNum<[58]>; 189 def F27_32 : RISCVReg32<27,"f27", ["fs11"]>, DwarfRegNum<[59]>; 190 def F28_32 : RISCVReg32<28,"f28", ["ft8"]>, DwarfRegNum<[60]>; 191 def F29_32 : RISCVReg32<29,"f29", ["ft9"]>, DwarfRegNum<[61]>; 192 def F30_32 : RISCVReg32<30,"f30", ["ft10"]>, DwarfRegNum<[62]>; 193 def F31_32 : RISCVReg32<31,"f31", ["ft11"]>, DwarfRegNum<[63]>; 194 195 foreach Index = 0-31 in { 196 def F#Index#_64 : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_32")>, 197 DwarfRegNum<[!add(Index, 32)]>; 198 } 199} 200 201// The order of registers represents the preferred allocation sequence, 202// meaning caller-save regs are listed before callee-save. 203def FPR32 : RegisterClass<"RISCV", [f32], 32, (add 204 (sequence "F%u_32", 0, 7), 205 (sequence "F%u_32", 10, 17), 206 (sequence "F%u_32", 28, 31), 207 (sequence "F%u_32", 8, 9), 208 (sequence "F%u_32", 18, 27) 209)>; 210 211def FPR32C : RegisterClass<"RISCV", [f32], 32, (add 212 (sequence "F%u_32", 10, 15), 213 (sequence "F%u_32", 8, 9) 214)>; 215 216// The order of registers represents the preferred allocation sequence, 217// meaning caller-save regs are listed before callee-save. 218def FPR64 : RegisterClass<"RISCV", [f64], 64, (add 219 (sequence "F%u_64", 0, 7), 220 (sequence "F%u_64", 10, 17), 221 (sequence "F%u_64", 28, 31), 222 (sequence "F%u_64", 8, 9), 223 (sequence "F%u_64", 18, 27) 224)>; 225 226def FPR64C : RegisterClass<"RISCV", [f64], 64, (add 227 (sequence "F%u_64", 10, 15), 228 (sequence "F%u_64", 8, 9) 229)>; 230