1//===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the RISC-V register files 11//===----------------------------------------------------------------------===// 12 13let Namespace = "RISCV" in { 14class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 15 let HWEncoding{4-0} = Enc; 16 let AltNames = alt; 17} 18 19class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> { 20 let HWEncoding{4-0} = Enc; 21 let AltNames = alt; 22} 23 24def sub_16 : SubRegIndex<16>; 25class RISCVReg32<RISCVReg16 subreg> : Register<""> { 26 let HWEncoding{4-0} = subreg.HWEncoding{4-0}; 27 let SubRegs = [subreg]; 28 let SubRegIndices = [sub_16]; 29 let AsmName = subreg.AsmName; 30 let AltNames = subreg.AltNames; 31} 32 33// Because RISCVReg64 register have AsmName and AltNames that alias with their 34// 16/32-bit sub-register, RISCVAsmParser will need to coerce a register number 35// from a RISCVReg16/RISCVReg32 to the equivalent RISCVReg64 when appropriate. 36def sub_32 : SubRegIndex<32>; 37class RISCVReg64<RISCVReg32 subreg> : Register<""> { 38 let HWEncoding{4-0} = subreg.HWEncoding{4-0}; 39 let SubRegs = [subreg]; 40 let SubRegIndices = [sub_32]; 41 let AsmName = subreg.AsmName; 42 let AltNames = subreg.AltNames; 43} 44 45class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs, 46 list<string> alt = []> 47 : RegisterWithSubRegs<n, subregs> { 48 let HWEncoding{4-0} = Enc; 49 let AltNames = alt; 50} 51 52def ABIRegAltName : RegAltNameIndex; 53 54def sub_vrm4_0 : SubRegIndex<256>; 55def sub_vrm4_1 : SubRegIndex<256, 256>; 56def sub_vrm2_0 : SubRegIndex<128>; 57def sub_vrm2_1 : SubRegIndex<128, 128>; 58def sub_vrm2_2 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_0>; 59def sub_vrm2_3 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_1>; 60def sub_vrm1_0 : SubRegIndex<64>; 61def sub_vrm1_1 : SubRegIndex<64, 64>; 62def sub_vrm1_2 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_0>; 63def sub_vrm1_3 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_1>; 64def sub_vrm1_4 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_0>; 65def sub_vrm1_5 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_1>; 66def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>; 67def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>; 68 69def sub_32_hi : SubRegIndex<32, 32>; 70} // Namespace = "RISCV" 71 72// Integer registers 73// CostPerUse is set higher for registers that may not be compressible as they 74// are not part of GPRC, the most restrictive register class used by the 75// compressed instruction set. This will influence the greedy register 76// allocator to reduce the use of registers that can't be encoded in 16 bit 77// instructions. 78 79let RegAltNameIndices = [ABIRegAltName] in { 80 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; 81 let CostPerUse = [0, 1] in { 82 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; 83 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; 84 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; 85 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>; 86 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; 87 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; 88 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>; 89 } 90 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>; 91 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>; 92 def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>; 93 def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>; 94 def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>; 95 def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>; 96 def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>; 97 def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>; 98 let CostPerUse = [0, 1] in { 99 def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>; 100 def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>; 101 def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>; 102 def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>; 103 def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>; 104 def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>; 105 def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>; 106 def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>; 107 def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>; 108 def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>; 109 def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>; 110 def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>; 111 def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>; 112 def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>; 113 def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>; 114 def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>; 115 } 116} 117 118def XLenVT : ValueTypeByHwMode<[RV32, RV64], 119 [i32, i64]>; 120def XLenRI : RegInfoByHwMode< 121 [RV32, RV64], 122 [RegInfo<32,32,32>, RegInfo<64,64,64>]>; 123 124// The order of registers represents the preferred allocation sequence. 125// Registers are listed in the order caller-save, callee-save, specials. 126def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add 127 (sequence "X%u", 10, 17), 128 (sequence "X%u", 5, 7), 129 (sequence "X%u", 28, 31), 130 (sequence "X%u", 8, 9), 131 (sequence "X%u", 18, 27), 132 (sequence "X%u", 0, 4) 133 )> { 134 let RegInfos = XLenRI; 135} 136 137def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> { 138 let RegInfos = XLenRI; 139} 140 141def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X0)> { 142 let RegInfos = XLenRI; 143} 144 145def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, X0, X2)> { 146 let RegInfos = XLenRI; 147} 148 149// Don't use X1 or X5 for JALR since that is a hint to pop the return address 150// stack on some microarchitectures. Also remove the reserved registers X0, X2, 151// X3, and X4 as it reduces the number of register classes that get synthesized 152// by tablegen. 153def GPRJALR : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, (sequence "X%u", 0, 5))> { 154 let RegInfos = XLenRI; 155} 156 157def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add 158 (sequence "X%u", 10, 15), 159 (sequence "X%u", 8, 9) 160 )> { 161 let RegInfos = XLenRI; 162} 163 164// For indirect tail calls, we can't use callee-saved registers, as they are 165// restored to the saved value before the tail call, which would clobber a call 166// address. We shouldn't use x5 since that is a hint for to pop the return 167// address stack on some microarchitectures. 168def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add 169 (sequence "X%u", 6, 7), 170 (sequence "X%u", 10, 17), 171 (sequence "X%u", 28, 31) 172 )> { 173 let RegInfos = XLenRI; 174} 175 176def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> { 177 let RegInfos = XLenRI; 178} 179 180// Floating point registers 181let RegAltNameIndices = [ABIRegAltName] in { 182 def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; 183 def F1_H : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>; 184 def F2_H : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>; 185 def F3_H : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>; 186 def F4_H : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>; 187 def F5_H : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>; 188 def F6_H : RISCVReg16<6, "f6", ["ft6"]>, DwarfRegNum<[38]>; 189 def F7_H : RISCVReg16<7, "f7", ["ft7"]>, DwarfRegNum<[39]>; 190 def F8_H : RISCVReg16<8, "f8", ["fs0"]>, DwarfRegNum<[40]>; 191 def F9_H : RISCVReg16<9, "f9", ["fs1"]>, DwarfRegNum<[41]>; 192 def F10_H : RISCVReg16<10,"f10", ["fa0"]>, DwarfRegNum<[42]>; 193 def F11_H : RISCVReg16<11,"f11", ["fa1"]>, DwarfRegNum<[43]>; 194 def F12_H : RISCVReg16<12,"f12", ["fa2"]>, DwarfRegNum<[44]>; 195 def F13_H : RISCVReg16<13,"f13", ["fa3"]>, DwarfRegNum<[45]>; 196 def F14_H : RISCVReg16<14,"f14", ["fa4"]>, DwarfRegNum<[46]>; 197 def F15_H : RISCVReg16<15,"f15", ["fa5"]>, DwarfRegNum<[47]>; 198 def F16_H : RISCVReg16<16,"f16", ["fa6"]>, DwarfRegNum<[48]>; 199 def F17_H : RISCVReg16<17,"f17", ["fa7"]>, DwarfRegNum<[49]>; 200 def F18_H : RISCVReg16<18,"f18", ["fs2"]>, DwarfRegNum<[50]>; 201 def F19_H : RISCVReg16<19,"f19", ["fs3"]>, DwarfRegNum<[51]>; 202 def F20_H : RISCVReg16<20,"f20", ["fs4"]>, DwarfRegNum<[52]>; 203 def F21_H : RISCVReg16<21,"f21", ["fs5"]>, DwarfRegNum<[53]>; 204 def F22_H : RISCVReg16<22,"f22", ["fs6"]>, DwarfRegNum<[54]>; 205 def F23_H : RISCVReg16<23,"f23", ["fs7"]>, DwarfRegNum<[55]>; 206 def F24_H : RISCVReg16<24,"f24", ["fs8"]>, DwarfRegNum<[56]>; 207 def F25_H : RISCVReg16<25,"f25", ["fs9"]>, DwarfRegNum<[57]>; 208 def F26_H : RISCVReg16<26,"f26", ["fs10"]>, DwarfRegNum<[58]>; 209 def F27_H : RISCVReg16<27,"f27", ["fs11"]>, DwarfRegNum<[59]>; 210 def F28_H : RISCVReg16<28,"f28", ["ft8"]>, DwarfRegNum<[60]>; 211 def F29_H : RISCVReg16<29,"f29", ["ft9"]>, DwarfRegNum<[61]>; 212 def F30_H : RISCVReg16<30,"f30", ["ft10"]>, DwarfRegNum<[62]>; 213 def F31_H : RISCVReg16<31,"f31", ["ft11"]>, DwarfRegNum<[63]>; 214 215 foreach Index = 0-31 in { 216 def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>, 217 DwarfRegNum<[!add(Index, 32)]>; 218 } 219 220 foreach Index = 0-31 in { 221 def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>, 222 DwarfRegNum<[!add(Index, 32)]>; 223 } 224} 225 226// The order of registers represents the preferred allocation sequence, 227// meaning caller-save regs are listed before callee-save. 228def FPR16 : RegisterClass<"RISCV", [f16], 16, (add 229 (sequence "F%u_H", 0, 7), 230 (sequence "F%u_H", 10, 17), 231 (sequence "F%u_H", 28, 31), 232 (sequence "F%u_H", 8, 9), 233 (sequence "F%u_H", 18, 27) 234)>; 235 236def FPR32 : RegisterClass<"RISCV", [f32], 32, (add 237 (sequence "F%u_F", 0, 7), 238 (sequence "F%u_F", 10, 17), 239 (sequence "F%u_F", 28, 31), 240 (sequence "F%u_F", 8, 9), 241 (sequence "F%u_F", 18, 27) 242)>; 243 244def FPR32C : RegisterClass<"RISCV", [f32], 32, (add 245 (sequence "F%u_F", 10, 15), 246 (sequence "F%u_F", 8, 9) 247)>; 248 249// The order of registers represents the preferred allocation sequence, 250// meaning caller-save regs are listed before callee-save. 251def FPR64 : RegisterClass<"RISCV", [f64], 64, (add 252 (sequence "F%u_D", 0, 7), 253 (sequence "F%u_D", 10, 17), 254 (sequence "F%u_D", 28, 31), 255 (sequence "F%u_D", 8, 9), 256 (sequence "F%u_D", 18, 27) 257)>; 258 259def FPR64C : RegisterClass<"RISCV", [f64], 64, (add 260 (sequence "F%u_D", 10, 15), 261 (sequence "F%u_D", 8, 9) 262)>; 263 264// Vector type mapping to LLVM types. 265// 266// The V vector extension requires that VLEN >= 128 and <= 65536. 267// Additionally, the only supported ELEN values are 32 and 64, 268// thus `vscale` can be defined as VLEN/64, 269// allowing the same types with either ELEN value. 270// 271// MF8 MF4 MF2 M1 M2 M4 M8 272// i64* N/A N/A N/A nxv1i64 nxv2i64 nxv4i64 nxv8i64 273// i32 N/A N/A nxv1i32 nxv2i32 nxv4i32 nxv8i32 nxv16i32 274// i16 N/A nxv1i16 nxv2i16 nxv4i16 nxv8i16 nxv16i16 nxv32i16 275// i8 nxv1i8 nxv2i8 nxv4i8 nxv8i8 nxv16i8 nxv32i8 nxv64i8 276// double* N/A N/A N/A nxv1f64 nxv2f64 nxv4f64 nxv8f64 277// float N/A N/A nxv1f32 nxv2f32 nxv4f32 nxv8f32 nxv16f32 278// half N/A nxv1f16 nxv2f16 nxv4f16 nxv8f16 nxv16f16 nxv32f16 279// * ELEN=64 280 281defvar vint8mf8_t = nxv1i8; 282defvar vint8mf4_t = nxv2i8; 283defvar vint8mf2_t = nxv4i8; 284defvar vint8m1_t = nxv8i8; 285defvar vint8m2_t = nxv16i8; 286defvar vint8m4_t = nxv32i8; 287defvar vint8m8_t = nxv64i8; 288 289defvar vint16mf4_t = nxv1i16; 290defvar vint16mf2_t = nxv2i16; 291defvar vint16m1_t = nxv4i16; 292defvar vint16m2_t = nxv8i16; 293defvar vint16m4_t = nxv16i16; 294defvar vint16m8_t = nxv32i16; 295 296defvar vint32mf2_t = nxv1i32; 297defvar vint32m1_t = nxv2i32; 298defvar vint32m2_t = nxv4i32; 299defvar vint32m4_t = nxv8i32; 300defvar vint32m8_t = nxv16i32; 301 302defvar vint64m1_t = nxv1i64; 303defvar vint64m2_t = nxv2i64; 304defvar vint64m4_t = nxv4i64; 305defvar vint64m8_t = nxv8i64; 306 307defvar vfloat16mf4_t = nxv1f16; 308defvar vfloat16mf2_t = nxv2f16; 309defvar vfloat16m1_t = nxv4f16; 310defvar vfloat16m2_t = nxv8f16; 311defvar vfloat16m4_t = nxv16f16; 312defvar vfloat16m8_t = nxv32f16; 313 314defvar vfloat32mf2_t = nxv1f32; 315defvar vfloat32m1_t = nxv2f32; 316defvar vfloat32m2_t = nxv4f32; 317defvar vfloat32m4_t = nxv8f32; 318defvar vfloat32m8_t = nxv16f32; 319 320defvar vfloat64m1_t = nxv1f64; 321defvar vfloat64m2_t = nxv2f64; 322defvar vfloat64m4_t = nxv4f64; 323defvar vfloat64m8_t = nxv8f64; 324 325defvar vbool1_t = nxv64i1; 326defvar vbool2_t = nxv32i1; 327defvar vbool4_t = nxv16i1; 328defvar vbool8_t = nxv8i1; 329defvar vbool16_t = nxv4i1; 330defvar vbool32_t = nxv2i1; 331defvar vbool64_t = nxv1i1; 332 333// There is no need to define register classes for fractional LMUL. 334def LMULList { 335 list<int> m = [1, 2, 4, 8]; 336} 337 338//===----------------------------------------------------------------------===// 339// Utility classes for segment load/store. 340//===----------------------------------------------------------------------===// 341// The set of legal NF for LMUL = lmul. 342// LMUL == 1, NF = 2, 3, 4, 5, 6, 7, 8 343// LMUL == 2, NF = 2, 3, 4 344// LMUL == 4, NF = 2 345class NFList<int lmul> { 346 list<int> L = !cond(!eq(lmul, 1): [2, 3, 4, 5, 6, 7, 8], 347 !eq(lmul, 2): [2, 3, 4], 348 !eq(lmul, 4): [2], 349 !eq(lmul, 8): []); 350} 351 352// Generate [start, end) SubRegIndex list. 353class SubRegSet<int nf, int lmul> { 354 list<SubRegIndex> L = !foldl([]<SubRegIndex>, 355 [0, 1, 2, 3, 4, 5, 6, 7], 356 AccList, i, 357 !listconcat(AccList, 358 !if(!lt(i, nf), 359 [!cast<SubRegIndex>("sub_vrm" # lmul # "_" # i)], 360 []))); 361} 362 363// Collect the valid indexes into 'R' under NF and LMUL values from TUPLE_INDEX. 364// When NF = 2, the valid TUPLE_INDEX is 0 and 1. 365// For example, when LMUL = 4, the potential valid indexes is 366// [8, 12, 16, 20, 24, 28, 4]. However, not all these indexes are valid under 367// NF = 2. For example, 28 is not valid under LMUL = 4, NF = 2 and TUPLE_INDEX = 0. 368// The filter is 369// (tuple_index + i) x lmul <= (tuple_index x lmul) + 32 - (nf x lmul) 370// 371// Use START = 0, LMUL = 4 and NF = 2 as the example, 372// i x 4 <= 24 373// The class will return [8, 12, 16, 20, 24, 4]. 374// Use START = 1, LMUL = 4 and NF = 2 as the example, 375// (1 + i) x 4 <= 28 376// The class will return [12, 16, 20, 24, 28, 8]. 377// 378class IndexSet<int tuple_index, int nf, int lmul, bit isV0 = false> { 379 list<int> R = 380 !foldl([]<int>, 381 !if(isV0, [0], 382 !cond( 383 !eq(lmul, 1): 384 [8, 9, 10, 11, 12, 13, 14, 15, 385 16, 17, 18, 19, 20, 21, 22, 23, 386 24, 25, 26, 27, 28, 29, 30, 31, 387 1, 2, 3, 4, 5, 6, 7], 388 !eq(lmul, 2): 389 [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 1, 2, 3], 390 !eq(lmul, 4): 391 [2, 3, 4, 5, 6, 7, 1])), 392 L, i, 393 !listconcat(L, 394 !if(!le(!mul(!add(i, tuple_index), lmul), 395 !sub(!add(32, !mul(tuple_index, lmul)), !mul(nf, lmul))), 396 [!mul(!add(i, tuple_index), lmul)], []))); 397} 398 399// This class returns a list of vector register collections. 400// For example, for NF = 2 and LMUL = 4, 401// it will return 402// ([ V8M4, V12M4, V16M4, V20M4, V24M4, V4M4], 403// [V12M4, V16M4, V20M4, V24M4, V28M4, V8M4]) 404// 405class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> { 406 list<dag> L = 407 !if(!ge(start, nf), 408 LIn, 409 !listconcat( 410 [!dag(add, 411 !foreach(i, IndexSet<start, nf, lmul, isV0>.R, 412 !cast<Register>("V" # i # !cond(!eq(lmul, 2): "M2", 413 !eq(lmul, 4): "M4", 414 true: ""))), 415 !listsplat("", 416 !size(IndexSet<start, nf, lmul, isV0>.R)))], 417 VRegList<LIn, !add(start, 1), nf, lmul, isV0>.L)); 418} 419 420// Vector registers 421let RegAltNameIndices = [ABIRegAltName] in { 422 foreach Index = 0-31 in { 423 def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 96)]>; 424 } 425 426 foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 427 24, 26, 28, 30] in { 428 def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index, 429 [!cast<Register>("V"#Index), 430 !cast<Register>("V"#!add(Index, 1))], 431 ["v"#Index]>, 432 DwarfRegAlias<!cast<Register>("V"#Index)> { 433 let SubRegIndices = [sub_vrm1_0, sub_vrm1_1]; 434 } 435 } 436 437 foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in { 438 def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index, 439 [!cast<Register>("V"#Index#"M2"), 440 !cast<Register>("V"#!add(Index, 2)#"M2")], 441 ["v"#Index]>, 442 DwarfRegAlias<!cast<Register>("V"#Index)> { 443 let SubRegIndices = [sub_vrm2_0, sub_vrm2_1]; 444 } 445 } 446 447 foreach Index = [0, 8, 16, 24] in { 448 def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index, 449 [!cast<Register>("V"#Index#"M4"), 450 !cast<Register>("V"#!add(Index, 4)#"M4")], 451 ["v"#Index]>, 452 DwarfRegAlias<!cast<Register>("V"#Index)> { 453 let SubRegIndices = [sub_vrm4_0, sub_vrm4_1]; 454 } 455 } 456 457 def VTYPE : RISCVReg<0, "vtype", ["vtype"]>; 458 def VL : RISCVReg<0, "vl", ["vl"]>; 459 def VXSAT : RISCVReg<0, "vxsat", ["vxsat"]>; 460 def VXRM : RISCVReg<0, "vxrm", ["vxrm"]>; 461 def VLENB : RISCVReg<0, "vlenb", ["vlenb"]>, 462 DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>; 463} 464 465def VCSR : RegisterClass<"RISCV", [XLenVT], 32, 466 (add VTYPE, VL, VLENB)> { 467 let RegInfos = XLenRI; 468} 469 470 471foreach m = [1, 2, 4] in { 472 foreach n = NFList<m>.L in { 473 def "VN" # n # "M" # m # "NoV0": RegisterTuples< 474 SubRegSet<n, m>.L, 475 VRegList<[], 0, n, m, false>.L>; 476 def "VN" # n # "M" # m # "V0" : RegisterTuples< 477 SubRegSet<n, m>.L, 478 VRegList<[], 0, n, m, true>.L>; 479 } 480} 481 482class VReg<list<ValueType> regTypes, dag regList, int Vlmul> 483 : RegisterClass<"RISCV", 484 regTypes, 485 64, // The maximum supported ELEN is 64. 486 regList> { 487 int VLMul = Vlmul; 488 int Size = !mul(Vlmul, 64); 489} 490 491def VR : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, 492 vfloat16m1_t, vfloat32m1_t, vfloat64m1_t, 493 vint8mf2_t, vint8mf4_t, vint8mf8_t, 494 vint16mf2_t, vint16mf4_t, vint32mf2_t, 495 vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t, 496 vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t, 497 vbool2_t, vbool1_t], 498 (add (sequence "V%u", 8, 31), 499 (sequence "V%u", 0, 7)), 1>; 500 501def VRNoV0 : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, 502 vfloat16m1_t, vfloat32m1_t, vfloat64m1_t, 503 vint8mf2_t, vint8mf4_t, vint8mf8_t, 504 vint16mf2_t, vint16mf4_t, vint32mf2_t, 505 vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t, 506 vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t, 507 vbool2_t, vbool1_t], 508 (add (sequence "V%u", 8, 31), 509 (sequence "V%u", 1, 7)), 1>; 510 511def VRM2 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, 512 vfloat16m2_t, vfloat32m2_t, vfloat64m2_t], 513 (add (sequence "V%uM2", 8, 31, 2), 514 (sequence "V%uM2", 0, 7, 2)), 2>; 515 516def VRM2NoV0 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, 517 vfloat16m2_t, vfloat32m2_t, vfloat64m2_t], 518 (add (sequence "V%uM2", 8, 31, 2), 519 (sequence "V%uM2", 2, 7, 2)), 2>; 520 521def VRM4 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, 522 vfloat16m4_t, vfloat32m4_t, vfloat64m4_t], 523 (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V0M4, V4M4), 4>; 524 525def VRM4NoV0 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, 526 vfloat16m4_t, vfloat32m4_t, vfloat64m4_t], 527 (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V4M4), 4>; 528 529def VRM8 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, 530 vfloat16m8_t, vfloat32m8_t, vfloat64m8_t], 531 (add V8M8, V16M8, V24M8, V0M8), 8>; 532 533def VRM8NoV0 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, 534 vfloat16m8_t, vfloat32m8_t, vfloat64m8_t], 535 (add V8M8, V16M8, V24M8), 8>; 536 537defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t, 538 vbool32_t, vbool64_t]; 539 540def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> { 541 let Size = 64; 542} 543 544let RegInfos = XLenRI in { 545def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add GPR)>; 546def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add GPR)>; 547def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add GPR)>; 548} // RegInfos = XLenRI 549 550let RegAltNameIndices = [ABIRegAltName] in { 551 foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 552 24, 26, 28, 30] in { 553 defvar Reg = !cast<Register>("X"#Index); 554 def X#Index#_PD : RISCVRegWithSubRegs<Index, Reg.AsmName, 555 [!cast<Register>("X"#Index), 556 !cast<Register>("X"#!add(Index, 1))], 557 Reg.AltNames> { 558 let SubRegIndices = [sub_32, sub_32_hi]; 559 } 560 } 561} 562 563let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in 564def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add 565 X10_PD, X12_PD, X14_PD, X16_PD, 566 X6_PD, 567 X28_PD, X30_PD, 568 X8_PD, 569 X18_PD, X20_PD, X22_PD, X24_PD, X26_PD, 570 X0_PD, X2_PD, X4_PD 571)>; 572 573// The register class is added for inline assembly for vector mask types. 574def VM : VReg<VMaskVTs, 575 (add (sequence "V%u", 8, 31), 576 (sequence "V%u", 0, 7)), 1>; 577 578foreach m = LMULList.m in { 579 foreach nf = NFList<m>.L in { 580 def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped], 581 (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")), 582 !mul(nf, m)>; 583 def "VRN" # nf # "M" # m: VReg<[untyped], 584 (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0"), 585 !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")), 586 !mul(nf, m)>; 587 } 588} 589 590// Special registers 591def FFLAGS : RISCVReg<0, "fflags">; 592def FRM : RISCVReg<0, "frm">; 593 594// Any type register. Used for .insn directives when we don't know what the 595// register types could be. 596// NOTE: The alignment and size are bogus values. The Size needs to be non-zero 597// or tablegen will use "untyped" to determine the size which will assert. 598let isAllocatable = 0 in 599def AnyReg : RegisterClass<"RISCV", [untyped], 32, 600 (add (sequence "X%u", 0, 31), 601 (sequence "F%u_D", 0, 31), 602 (sequence "V%u", 0, 31))> { 603 let Size = 32; 604} 605