1//==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions --------*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10
11// SCR1: https://github.com/syntacore/scr1
12
13// This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max).
14// SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration has essentially
15// same scheduling characteristics.
16
17// SCR1 is single-issue in-order processor
18def SyntacoreSCR1Model : SchedMachineModel {
19  let MicroOpBufferSize = 0;
20  let IssueWidth = 1;
21  let LoadLatency = 2;
22  let MispredictPenalty = 3;
23  let CompleteModel = 0;
24  let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
25                             HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
26                             HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
27                             HasVInstructions];
28}
29
30let SchedModel = SyntacoreSCR1Model in {
31
32let BufferSize = 0 in {
33def SCR1_ALU : ProcResource<1>;
34def SCR1_LSU : ProcResource<1>;
35def SCR1_MUL : ProcResource<1>;
36def SCR1_DIV : ProcResource<1>;
37def SCR1_CFU : ProcResource<1>;
38}
39
40// Branching
41def : WriteRes<WriteJmp, [SCR1_CFU]>;
42def : WriteRes<WriteJal, [SCR1_CFU]>;
43def : WriteRes<WriteJalr, [SCR1_CFU]>;
44def : WriteRes<WriteJmpReg, [SCR1_CFU]>;
45
46// Integer arithmetic and logic
47def : WriteRes<WriteIALU32, [SCR1_ALU]>;
48def : WriteRes<WriteIALU, [SCR1_ALU]>;
49def : WriteRes<WriteShiftImm32, [SCR1_ALU]>;
50def : WriteRes<WriteShiftImm, [SCR1_ALU]>;
51def : WriteRes<WriteShiftReg32, [SCR1_ALU]>;
52def : WriteRes<WriteShiftReg, [SCR1_ALU]>;
53
54// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX
55def : WriteRes<WriteIMul, [SCR1_MUL]>;
56def : WriteRes<WriteIMul32, [SCR1_MUL]>;
57
58// Integer division: latency 33, inverse throughput 33
59let Latency = 33, ResourceCycles = [33] in {
60def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
61def : WriteRes<WriteIDiv, [SCR1_DIV]>;
62}
63
64// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
65// (SCR1_CFG_RV32IMC_MAX includes TCM)
66let Latency = 2, ResourceCycles=[2] in {
67// Memory
68def : WriteRes<WriteSTB, [SCR1_LSU]>;
69def : WriteRes<WriteSTH, [SCR1_LSU]>;
70def : WriteRes<WriteSTW, [SCR1_LSU]>;
71def : WriteRes<WriteSTD, [SCR1_LSU]>;
72def : WriteRes<WriteLDB, [SCR1_LSU]>;
73def : WriteRes<WriteLDH, [SCR1_LSU]>;
74def : WriteRes<WriteLDW, [SCR1_LSU]>;
75def : WriteRes<WriteLDD, [SCR1_LSU]>;
76}
77
78let Unsupported = true in {
79// Atomic memory
80def : WriteRes<WriteAtomicW, [SCR1_LSU]>;
81def : WriteRes<WriteAtomicD, [SCR1_LSU]>;
82def : WriteRes<WriteAtomicLDW, [SCR1_LSU]>;
83def : WriteRes<WriteAtomicLDD, [SCR1_LSU]>;
84def : WriteRes<WriteAtomicSTW, [SCR1_LSU]>;
85def : WriteRes<WriteAtomicSTD, [SCR1_LSU]>;
86
87// FP load/store
88def : WriteRes<WriteFST32, [SCR1_LSU]>;
89def : WriteRes<WriteFST64, [SCR1_LSU]>;
90def : WriteRes<WriteFLD32, [SCR1_LSU]>;
91def : WriteRes<WriteFLD64, [SCR1_LSU]>;
92
93// FP instructions
94def : WriteRes<WriteFAdd32, []>;
95def : WriteRes<WriteFSGNJ32, []>;
96def : WriteRes<WriteFMinMax32, []>;
97def : WriteRes<WriteFAdd64, []>;
98def : WriteRes<WriteFSGNJ64, []>;
99def : WriteRes<WriteFMinMax64, []>;
100def : WriteRes<WriteFCvtI32ToF32, []>;
101def : WriteRes<WriteFCvtI32ToF64, []>;
102def : WriteRes<WriteFCvtI64ToF32, []>;
103def : WriteRes<WriteFCvtI64ToF64, []>;
104def : WriteRes<WriteFCvtF32ToI32, []>;
105def : WriteRes<WriteFCvtF32ToI64, []>;
106def : WriteRes<WriteFCvtF64ToI32, []>;
107def : WriteRes<WriteFCvtF64ToI64, []>;
108def : WriteRes<WriteFCvtF32ToF64, []>;
109def : WriteRes<WriteFCvtF64ToF32, []>;
110def : WriteRes<WriteFClass32, []>;
111def : WriteRes<WriteFClass64, []>;
112def : WriteRes<WriteFCmp32, []>;
113def : WriteRes<WriteFCmp64, []>;
114def : WriteRes<WriteFMovF32ToI32, []>;
115def : WriteRes<WriteFMovI32ToF32, []>;
116def : WriteRes<WriteFMovF64ToI64, []>;
117def : WriteRes<WriteFMovI64ToF64, []>;
118def : WriteRes<WriteFMul32, []>;
119def : WriteRes<WriteFMA32, []>;
120def : WriteRes<WriteFMul64, []>;
121def : WriteRes<WriteFMA64, []>;
122def : WriteRes<WriteFDiv32, []>;
123def : WriteRes<WriteFDiv64, []>;
124def : WriteRes<WriteFSqrt32, []>;
125def : WriteRes<WriteFSqrt64, []>;
126
127def : WriteRes<WriteSFB, []>;
128}
129
130// Others
131def : WriteRes<WriteCSR, []>;
132def : WriteRes<WriteNop, []>;
133
134def : InstRW<[WriteIALU], (instrs COPY)>;
135
136//===----------------------------------------------------------------------===//
137// Bypasses (none)
138def : ReadAdvance<ReadJmp, 0>;
139def : ReadAdvance<ReadJalr, 0>;
140def : ReadAdvance<ReadCSR, 0>;
141def : ReadAdvance<ReadStoreData, 0>;
142def : ReadAdvance<ReadMemBase, 0>;
143def : ReadAdvance<ReadIALU, 0>;
144def : ReadAdvance<ReadIALU32, 0>;
145def : ReadAdvance<ReadShiftImm, 0>;
146def : ReadAdvance<ReadShiftImm32, 0>;
147def : ReadAdvance<ReadShiftReg, 0>;
148def : ReadAdvance<ReadShiftReg32, 0>;
149def : ReadAdvance<ReadIDiv, 0>;
150def : ReadAdvance<ReadIDiv32, 0>;
151def : ReadAdvance<ReadIMul, 0>;
152def : ReadAdvance<ReadIMul32, 0>;
153def : ReadAdvance<ReadAtomicWA, 0>;
154def : ReadAdvance<ReadAtomicWD, 0>;
155def : ReadAdvance<ReadAtomicDA, 0>;
156def : ReadAdvance<ReadAtomicDD, 0>;
157def : ReadAdvance<ReadAtomicLDW, 0>;
158def : ReadAdvance<ReadAtomicLDD, 0>;
159def : ReadAdvance<ReadAtomicSTW, 0>;
160def : ReadAdvance<ReadAtomicSTD, 0>;
161def : ReadAdvance<ReadFStoreData, 0>;
162def : ReadAdvance<ReadFMemBase, 0>;
163def : ReadAdvance<ReadFAdd32, 0>;
164def : ReadAdvance<ReadFAdd64, 0>;
165def : ReadAdvance<ReadFMul32, 0>;
166def : ReadAdvance<ReadFMul64, 0>;
167def : ReadAdvance<ReadFMA32, 0>;
168def : ReadAdvance<ReadFMA64, 0>;
169def : ReadAdvance<ReadFDiv32, 0>;
170def : ReadAdvance<ReadFDiv64, 0>;
171def : ReadAdvance<ReadFSqrt32, 0>;
172def : ReadAdvance<ReadFSqrt64, 0>;
173def : ReadAdvance<ReadFCmp32, 0>;
174def : ReadAdvance<ReadFCmp64, 0>;
175def : ReadAdvance<ReadFSGNJ32, 0>;
176def : ReadAdvance<ReadFSGNJ64, 0>;
177def : ReadAdvance<ReadFMinMax32, 0>;
178def : ReadAdvance<ReadFMinMax64, 0>;
179def : ReadAdvance<ReadFCvtF32ToI32, 0>;
180def : ReadAdvance<ReadFCvtF32ToI64, 0>;
181def : ReadAdvance<ReadFCvtF64ToI32, 0>;
182def : ReadAdvance<ReadFCvtF64ToI64, 0>;
183def : ReadAdvance<ReadFCvtI32ToF32, 0>;
184def : ReadAdvance<ReadFCvtI32ToF64, 0>;
185def : ReadAdvance<ReadFCvtI64ToF32, 0>;
186def : ReadAdvance<ReadFCvtI64ToF64, 0>;
187def : ReadAdvance<ReadFCvtF32ToF64, 0>;
188def : ReadAdvance<ReadFCvtF64ToF32, 0>;
189def : ReadAdvance<ReadFMovF32ToI32, 0>;
190def : ReadAdvance<ReadFMovI32ToF32, 0>;
191def : ReadAdvance<ReadFMovF64ToI64, 0>;
192def : ReadAdvance<ReadFMovI64ToF64, 0>;
193def : ReadAdvance<ReadFClass32, 0>;
194def : ReadAdvance<ReadFClass64, 0>;
195def : ReadAdvance<ReadSFB, 0>;
196
197//===----------------------------------------------------------------------===//
198// Unsupported extensions
199defm : UnsupportedSchedV;
200defm : UnsupportedSchedZba;
201defm : UnsupportedSchedZbb;
202defm : UnsupportedSchedZbc;
203defm : UnsupportedSchedZbs;
204defm : UnsupportedSchedZbkb;
205defm : UnsupportedSchedZbkx;
206defm : UnsupportedSchedZfh;
207}
208