1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
14 #include "RISCV.h"
15 #include "RISCVTargetObjectFile.h"
16 #include "RISCVTargetTransformInfo.h"
17 #include "TargetInfo/RISCVTargetInfo.h"
18 #include "Utils/RISCVBaseInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
22 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
23 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
24 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/CodeGen/TargetPassConfig.h"
28 #include "llvm/IR/LegacyPassManager.h"
29 #include "llvm/InitializePasses.h"
30 #include "llvm/Support/FormattedStream.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Target/TargetOptions.h"
33 using namespace llvm;
34 
35 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
36   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
37   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
38   auto PR = PassRegistry::getPassRegistry();
39   initializeGlobalISel(*PR);
40   initializeRISCVExpandPseudoPass(*PR);
41 }
42 
43 static StringRef computeDataLayout(const Triple &TT) {
44   if (TT.isArch64Bit()) {
45     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
46   } else {
47     assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
48     return "e-m:e-p:32:32-i64:64-n32-S128";
49   }
50 }
51 
52 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
53                                            Optional<Reloc::Model> RM) {
54   if (!RM.hasValue())
55     return Reloc::Static;
56   return *RM;
57 }
58 
59 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
60                                        StringRef CPU, StringRef FS,
61                                        const TargetOptions &Options,
62                                        Optional<Reloc::Model> RM,
63                                        Optional<CodeModel::Model> CM,
64                                        CodeGenOpt::Level OL, bool JIT)
65     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
66                         getEffectiveRelocModel(TT, RM),
67                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
68       TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
69   initAsmInfo();
70 
71   // RISC-V supports the MachineOutliner.
72   setMachineOutliner(true);
73 }
74 
75 const RISCVSubtarget *
76 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
77   Attribute CPUAttr = F.getFnAttribute("target-cpu");
78   Attribute FSAttr = F.getFnAttribute("target-features");
79 
80   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
81                         ? CPUAttr.getValueAsString().str()
82                         : TargetCPU;
83   std::string FS = !FSAttr.hasAttribute(Attribute::None)
84                        ? FSAttr.getValueAsString().str()
85                        : TargetFS;
86   std::string Key = CPU + FS;
87   auto &I = SubtargetMap[Key];
88   if (!I) {
89     // This needs to be done before we create a new subtarget since any
90     // creation will depend on the TM and the code generation flags on the
91     // function that reside in TargetOptions.
92     resetTargetOptions(F);
93     auto ABIName = Options.MCOptions.getABIName();
94     if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
95             F.getParent()->getModuleFlag("target-abi"))) {
96       auto TargetABI = RISCVABI::getTargetABI(ABIName);
97       if (TargetABI != RISCVABI::ABI_Unknown &&
98           ModuleTargetABI->getString() != ABIName) {
99         report_fatal_error("-target-abi option != target-abi module flag");
100       }
101       ABIName = ModuleTargetABI->getString();
102     }
103     I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, FS, ABIName, *this);
104   }
105   return I.get();
106 }
107 
108 TargetTransformInfo
109 RISCVTargetMachine::getTargetTransformInfo(const Function &F) {
110   return TargetTransformInfo(RISCVTTIImpl(this, F));
111 }
112 
113 namespace {
114 class RISCVPassConfig : public TargetPassConfig {
115 public:
116   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
117       : TargetPassConfig(TM, PM) {}
118 
119   RISCVTargetMachine &getRISCVTargetMachine() const {
120     return getTM<RISCVTargetMachine>();
121   }
122 
123   void addIRPasses() override;
124   bool addInstSelector() override;
125   bool addIRTranslator() override;
126   bool addLegalizeMachineIR() override;
127   bool addRegBankSelect() override;
128   bool addGlobalInstructionSelect() override;
129   void addPreEmitPass() override;
130   void addPreEmitPass2() override;
131   void addPreSched2() override;
132   void addPreRegAlloc() override;
133 };
134 }
135 
136 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
137   return new RISCVPassConfig(*this, PM);
138 }
139 
140 void RISCVPassConfig::addIRPasses() {
141   addPass(createAtomicExpandPass());
142   TargetPassConfig::addIRPasses();
143 }
144 
145 bool RISCVPassConfig::addInstSelector() {
146   addPass(createRISCVISelDag(getRISCVTargetMachine()));
147 
148   return false;
149 }
150 
151 bool RISCVPassConfig::addIRTranslator() {
152   addPass(new IRTranslator());
153   return false;
154 }
155 
156 bool RISCVPassConfig::addLegalizeMachineIR() {
157   addPass(new Legalizer());
158   return false;
159 }
160 
161 bool RISCVPassConfig::addRegBankSelect() {
162   addPass(new RegBankSelect());
163   return false;
164 }
165 
166 bool RISCVPassConfig::addGlobalInstructionSelect() {
167   addPass(new InstructionSelect());
168   return false;
169 }
170 
171 void RISCVPassConfig::addPreSched2() {}
172 
173 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
174 
175 void RISCVPassConfig::addPreEmitPass2() {
176   addPass(createRISCVExpandPseudoPass());
177   // Schedule the expansion of AMOs at the last possible moment, avoiding the
178   // possibility for other passes to break the requirements for forward
179   // progress in the LR/SC block.
180   addPass(createRISCVExpandAtomicPseudoPass());
181 }
182 
183 void RISCVPassConfig::addPreRegAlloc() {
184   addPass(createRISCVMergeBaseOffsetOptPass());
185 }
186