1//===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the Sparc register file 11//===----------------------------------------------------------------------===// 12 13class SparcReg<bits<16> Enc, string n> : Register<n> { 14 let HWEncoding = Enc; 15 let Namespace = "SP"; 16} 17 18class SparcCtrlReg<bits<16> Enc, string n>: Register<n> { 19 let HWEncoding = Enc; 20 let Namespace = "SP"; 21} 22 23let Namespace = "SP" in { 24def sub_even : SubRegIndex<32>; 25def sub_odd : SubRegIndex<32, 32>; 26def sub_even64 : SubRegIndex<64>; 27def sub_odd64 : SubRegIndex<64, 64>; 28} 29 30// Registers are identified with 5-bit ID numbers. 31// Ri - 32-bit integer registers 32class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>; 33 34// Rdi - pairs of 32-bit integer registers 35class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 36 let SubRegs = subregs; 37 let SubRegIndices = [sub_even, sub_odd]; 38 let CoveredBySubRegs = 1; 39} 40// Rf - 32-bit floating-point registers 41class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>; 42 43// Rd - Slots in the FP register file for 64-bit floating-point values. 44class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 45 let SubRegs = subregs; 46 let SubRegIndices = [sub_even, sub_odd]; 47 let CoveredBySubRegs = 1; 48} 49 50// Rq - Slots in the FP register file for 128-bit floating-point values. 51class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 52 let SubRegs = subregs; 53 let SubRegIndices = [sub_even64, sub_odd64]; 54 let CoveredBySubRegs = 1; 55} 56 57// Control Registers 58def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code. 59foreach I = 0-3 in 60 def FCC#I : SparcCtrlReg<I, "FCC"#I>; 61 62def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register. 63 64def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue. 65 66def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register. 67 68def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue. 69 70// Y register 71def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>; 72// Ancillary state registers (implementation defined) 73def ASR1 : SparcCtrlReg<1, "ASR1">; 74def ASR2 : SparcCtrlReg<2, "ASR2">; 75def ASR3 : SparcCtrlReg<3, "ASR3">; 76def ASR4 : SparcCtrlReg<4, "ASR4">; 77def ASR5 : SparcCtrlReg<5, "ASR5">; 78def ASR6 : SparcCtrlReg<6, "ASR6">; 79def ASR7 : SparcCtrlReg<7, "ASR7">; 80def ASR8 : SparcCtrlReg<8, "ASR8">; 81def ASR9 : SparcCtrlReg<9, "ASR9">; 82def ASR10 : SparcCtrlReg<10, "ASR10">; 83def ASR11 : SparcCtrlReg<11, "ASR11">; 84def ASR12 : SparcCtrlReg<12, "ASR12">; 85def ASR13 : SparcCtrlReg<13, "ASR13">; 86def ASR14 : SparcCtrlReg<14, "ASR14">; 87def ASR15 : SparcCtrlReg<15, "ASR15">; 88def ASR16 : SparcCtrlReg<16, "ASR16">; 89def ASR17 : SparcCtrlReg<17, "ASR17">; 90def ASR18 : SparcCtrlReg<18, "ASR18">; 91def ASR19 : SparcCtrlReg<19, "ASR19">; 92def ASR20 : SparcCtrlReg<20, "ASR20">; 93def ASR21 : SparcCtrlReg<21, "ASR21">; 94def ASR22 : SparcCtrlReg<22, "ASR22">; 95def ASR23 : SparcCtrlReg<23, "ASR23">; 96def ASR24 : SparcCtrlReg<24, "ASR24">; 97def ASR25 : SparcCtrlReg<25, "ASR25">; 98def ASR26 : SparcCtrlReg<26, "ASR26">; 99def ASR27 : SparcCtrlReg<27, "ASR27">; 100def ASR28 : SparcCtrlReg<28, "ASR28">; 101def ASR29 : SparcCtrlReg<29, "ASR29">; 102def ASR30 : SparcCtrlReg<30, "ASR30">; 103def ASR31 : SparcCtrlReg<31, "ASR31">; 104 105// Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8. 106def PSR : SparcCtrlReg<0, "PSR">; 107def WIM : SparcCtrlReg<0, "WIM">; 108def TBR : SparcCtrlReg<0, "TBR">; 109 110def TPC : SparcCtrlReg<0, "TPC">; 111def TNPC : SparcCtrlReg<1, "TNPC">; 112def TSTATE : SparcCtrlReg<2, "TSTATE">; 113def TT : SparcCtrlReg<3, "TT">; 114def TICK : SparcCtrlReg<4, "TICK">; 115def TBA : SparcCtrlReg<5, "TBA">; 116def PSTATE : SparcCtrlReg<6, "PSTATE">; 117def TL : SparcCtrlReg<7, "TL">; 118def PIL : SparcCtrlReg<8, "PIL">; 119def CWP : SparcCtrlReg<9, "CWP">; 120def CANSAVE : SparcCtrlReg<10, "CANSAVE">; 121def CANRESTORE : SparcCtrlReg<11, "CANRESTORE">; 122def CLEANWIN : SparcCtrlReg<12, "CLEANWIN">; 123def OTHERWIN : SparcCtrlReg<13, "OTHERWIN">; 124def WSTATE : SparcCtrlReg<14, "WSTATE">; 125 126// Integer registers 127def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; 128def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; 129def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; 130def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>; 131def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>; 132def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; 133def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>; 134def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>; 135def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>; 136def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>; 137def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; 138def O3 : Ri<11, "O3">, DwarfRegNum<[11]>; 139def O4 : Ri<12, "O4">, DwarfRegNum<[12]>; 140def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; 141def O6 : Ri<14, "SP">, DwarfRegNum<[14]>; 142def O7 : Ri<15, "O7">, DwarfRegNum<[15]>; 143def L0 : Ri<16, "L0">, DwarfRegNum<[16]>; 144def L1 : Ri<17, "L1">, DwarfRegNum<[17]>; 145def L2 : Ri<18, "L2">, DwarfRegNum<[18]>; 146def L3 : Ri<19, "L3">, DwarfRegNum<[19]>; 147def L4 : Ri<20, "L4">, DwarfRegNum<[20]>; 148def L5 : Ri<21, "L5">, DwarfRegNum<[21]>; 149def L6 : Ri<22, "L6">, DwarfRegNum<[22]>; 150def L7 : Ri<23, "L7">, DwarfRegNum<[23]>; 151def I0 : Ri<24, "I0">, DwarfRegNum<[24]>; 152def I1 : Ri<25, "I1">, DwarfRegNum<[25]>; 153def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; 154def I3 : Ri<27, "I3">, DwarfRegNum<[27]>; 155def I4 : Ri<28, "I4">, DwarfRegNum<[28]>; 156def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; 157def I6 : Ri<30, "FP">, DwarfRegNum<[30]>; 158def I7 : Ri<31, "I7">, DwarfRegNum<[31]>; 159 160// Floating-point registers 161def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>; 162def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>; 163def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; 164def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>; 165def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>; 166def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; 167def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>; 168def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>; 169def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; 170def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>; 171def F10 : Rf<10, "F10">, DwarfRegNum<[42]>; 172def F11 : Rf<11, "F11">, DwarfRegNum<[43]>; 173def F12 : Rf<12, "F12">, DwarfRegNum<[44]>; 174def F13 : Rf<13, "F13">, DwarfRegNum<[45]>; 175def F14 : Rf<14, "F14">, DwarfRegNum<[46]>; 176def F15 : Rf<15, "F15">, DwarfRegNum<[47]>; 177def F16 : Rf<16, "F16">, DwarfRegNum<[48]>; 178def F17 : Rf<17, "F17">, DwarfRegNum<[49]>; 179def F18 : Rf<18, "F18">, DwarfRegNum<[50]>; 180def F19 : Rf<19, "F19">, DwarfRegNum<[51]>; 181def F20 : Rf<20, "F20">, DwarfRegNum<[52]>; 182def F21 : Rf<21, "F21">, DwarfRegNum<[53]>; 183def F22 : Rf<22, "F22">, DwarfRegNum<[54]>; 184def F23 : Rf<23, "F23">, DwarfRegNum<[55]>; 185def F24 : Rf<24, "F24">, DwarfRegNum<[56]>; 186def F25 : Rf<25, "F25">, DwarfRegNum<[57]>; 187def F26 : Rf<26, "F26">, DwarfRegNum<[58]>; 188def F27 : Rf<27, "F27">, DwarfRegNum<[59]>; 189def F28 : Rf<28, "F28">, DwarfRegNum<[60]>; 190def F29 : Rf<29, "F29">, DwarfRegNum<[61]>; 191def F30 : Rf<30, "F30">, DwarfRegNum<[62]>; 192def F31 : Rf<31, "F31">, DwarfRegNum<[63]>; 193 194// Aliases of the F* registers used to hold 64-bit fp values (doubles) 195def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>; 196def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>; 197def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>; 198def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>; 199def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>; 200def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>; 201def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>; 202def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>; 203def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>; 204def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>; 205def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>; 206def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[83]>; 207def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[84]>; 208def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>; 209def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>; 210def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>; 211 212// Co-processor registers 213def C0 : Ri< 0, "C0">; 214def C1 : Ri< 1, "C1">; 215def C2 : Ri< 2, "C2">; 216def C3 : Ri< 3, "C3">; 217def C4 : Ri< 4, "C4">; 218def C5 : Ri< 5, "C5">; 219def C6 : Ri< 6, "C6">; 220def C7 : Ri< 7, "C7">; 221def C8 : Ri< 8, "C8">; 222def C9 : Ri< 9, "C9">; 223def C10 : Ri< 10, "C10">; 224def C11 : Ri< 11, "C11">; 225def C12 : Ri< 12, "C12">; 226def C13 : Ri< 13, "C13">; 227def C14 : Ri< 14, "C14">; 228def C15 : Ri< 15, "C15">; 229def C16 : Ri< 16, "C16">; 230def C17 : Ri< 17, "C17">; 231def C18 : Ri< 18, "C18">; 232def C19 : Ri< 19, "C19">; 233def C20 : Ri< 20, "C20">; 234def C21 : Ri< 21, "C21">; 235def C22 : Ri< 22, "C22">; 236def C23 : Ri< 23, "C23">; 237def C24 : Ri< 24, "C24">; 238def C25 : Ri< 25, "C25">; 239def C26 : Ri< 26, "C26">; 240def C27 : Ri< 27, "C27">; 241def C28 : Ri< 28, "C28">; 242def C29 : Ri< 29, "C29">; 243def C30 : Ri< 30, "C30">; 244def C31 : Ri< 31, "C31">; 245 246// Unaliased double precision floating point registers. 247// FIXME: Define DwarfRegNum for these registers. 248def D16 : SparcReg< 1, "F32">; 249def D17 : SparcReg< 3, "F34">; 250def D18 : SparcReg< 5, "F36">; 251def D19 : SparcReg< 7, "F38">; 252def D20 : SparcReg< 9, "F40">; 253def D21 : SparcReg<11, "F42">; 254def D22 : SparcReg<13, "F44">; 255def D23 : SparcReg<15, "F46">; 256def D24 : SparcReg<17, "F48">; 257def D25 : SparcReg<19, "F50">; 258def D26 : SparcReg<21, "F52">; 259def D27 : SparcReg<23, "F54">; 260def D28 : SparcReg<25, "F56">; 261def D29 : SparcReg<27, "F58">; 262def D30 : SparcReg<29, "F60">; 263def D31 : SparcReg<31, "F62">; 264 265// Aliases of the F* registers used to hold 128-bit for values (long doubles). 266def Q0 : Rq< 0, "F0", [D0, D1]>; 267def Q1 : Rq< 4, "F4", [D2, D3]>; 268def Q2 : Rq< 8, "F8", [D4, D5]>; 269def Q3 : Rq<12, "F12", [D6, D7]>; 270def Q4 : Rq<16, "F16", [D8, D9]>; 271def Q5 : Rq<20, "F20", [D10, D11]>; 272def Q6 : Rq<24, "F24", [D12, D13]>; 273def Q7 : Rq<28, "F28", [D14, D15]>; 274def Q8 : Rq< 1, "F32", [D16, D17]>; 275def Q9 : Rq< 5, "F36", [D18, D19]>; 276def Q10 : Rq< 9, "F40", [D20, D21]>; 277def Q11 : Rq<13, "F44", [D22, D23]>; 278def Q12 : Rq<17, "F48", [D24, D25]>; 279def Q13 : Rq<21, "F52", [D26, D27]>; 280def Q14 : Rq<25, "F56", [D28, D29]>; 281def Q15 : Rq<29, "F60", [D30, D31]>; 282 283// Aliases of the integer registers used for LDD/STD double-word operations 284def G0_G1 : Rdi<0, "G0", [G0, G1]>; 285def G2_G3 : Rdi<2, "G2", [G2, G3]>; 286def G4_G5 : Rdi<4, "G4", [G4, G5]>; 287def G6_G7 : Rdi<6, "G6", [G6, G7]>; 288def O0_O1 : Rdi<8, "O0", [O0, O1]>; 289def O2_O3 : Rdi<10, "O2", [O2, O3]>; 290def O4_O5 : Rdi<12, "O4", [O4, O5]>; 291def O6_O7 : Rdi<14, "O6", [O6, O7]>; 292def L0_L1 : Rdi<16, "L0", [L0, L1]>; 293def L2_L3 : Rdi<18, "L2", [L2, L3]>; 294def L4_L5 : Rdi<20, "L4", [L4, L5]>; 295def L6_L7 : Rdi<22, "L6", [L6, L7]>; 296def I0_I1 : Rdi<24, "I0", [I0, I1]>; 297def I2_I3 : Rdi<26, "I2", [I2, I3]>; 298def I4_I5 : Rdi<28, "I4", [I4, I5]>; 299def I6_I7 : Rdi<30, "I6", [I6, I7]>; 300 301// Aliases of the co-processor registers used for LDD/STD double-word operations 302def C0_C1 : Rdi<0, "C0", [C0, C1]>; 303def C2_C3 : Rdi<2, "C2", [C2, C3]>; 304def C4_C5 : Rdi<4, "C4", [C4, C5]>; 305def C6_C7 : Rdi<6, "C6", [C6, C7]>; 306def C8_C9 : Rdi<8, "C8", [C8, C9]>; 307def C10_C11 : Rdi<10, "C10", [C10, C11]>; 308def C12_C13 : Rdi<12, "C12", [C12, C13]>; 309def C14_C15 : Rdi<14, "C14", [C14, C15]>; 310def C16_C17 : Rdi<16, "C16", [C16, C17]>; 311def C18_C19 : Rdi<18, "C18", [C18, C19]>; 312def C20_C21 : Rdi<20, "C20", [C20, C21]>; 313def C22_C23 : Rdi<22, "C22", [C22, C23]>; 314def C24_C25 : Rdi<24, "C24", [C24, C25]>; 315def C26_C27 : Rdi<26, "C26", [C26, C27]>; 316def C28_C29 : Rdi<28, "C28", [C28, C29]>; 317def C30_C31 : Rdi<30, "C30", [C30, C31]>; 318 319// Register classes. 320// 321// FIXME: the register order should be defined in terms of the preferred 322// allocation order... 323// 324// This register class should not be used to hold i64 values, use the I64Regs 325// register class for that. The i64 type is included here to allow i64 patterns 326// using the integer instructions. 327def IntRegs : RegisterClass<"SP", [i32, i64], 32, 328 (add (sequence "I%u", 0, 7), 329 (sequence "G%u", 0, 7), 330 (sequence "L%u", 0, 7), 331 (sequence "O%u", 0, 7))>; 332 333// Should be in the same order as IntRegs. 334def IntPair : RegisterClass<"SP", [v2i32], 64, 335 (add I0_I1, I2_I3, I4_I5, I6_I7, 336 G0_G1, G2_G3, G4_G5, G6_G7, 337 L0_L1, L2_L3, L4_L5, L6_L7, 338 O0_O1, O2_O3, O4_O5, O6_O7)>; 339 340// Register class for 64-bit mode, with a 64-bit spill slot size. 341// These are the same as the 32-bit registers, so TableGen will consider this 342// to be a sub-class of IntRegs. That works out because requiring a 64-bit 343// spill slot is a stricter constraint than only requiring a 32-bit spill slot. 344def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>; 345 346// Floating point register classes. 347def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>; 348def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>; 349def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>; 350 351// The Low?FPRegs classes are used only for inline-asm constraints. 352def LowDFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 15)>; 353def LowQFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 7)>; 354 355// Floating point control register classes. 356def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>; 357 358let isAllocatable = 0 in { 359 // Ancillary state registers 360 def ASRRegs : RegisterClass<"SP", [i32], 32, 361 (add Y, (sequence "ASR%u", 1, 31))>; 362 363 // This register class should not be used to hold i64 values. 364 def CoprocRegs : RegisterClass<"SP", [i32], 32, 365 (add (sequence "C%u", 0, 31))>; 366 367 // Should be in the same order as CoprocRegs. 368 def CoprocPair : RegisterClass<"SP", [v2i32], 64, 369 (add C0_C1, C2_C3, C4_C5, C6_C7, 370 C8_C9, C10_C11, C12_C13, C14_C15, 371 C16_C17, C18_C19, C20_C21, C22_C23, 372 C24_C25, C26_C27, C28_C29, C30_C31)>; 373} 374 375// Privileged Registers 376def PRRegs : RegisterClass<"SP", [i64], 64, 377 (add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP, 378 CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE)>; 379