1//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This is a target description file for the WebAssembly architecture,
11/// which is also known as "wasm".
12///
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Target-independent interfaces which we are implementing
17//===----------------------------------------------------------------------===//
18
19include "llvm/Target/Target.td"
20
21//===----------------------------------------------------------------------===//
22// WebAssembly Subtarget features.
23//===----------------------------------------------------------------------===//
24
25def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128",
26                                      "Enable 128-bit SIMD">;
27
28def FeatureRelaxedSIMD : SubtargetFeature<"relaxed-simd", "SIMDLevel", "RelaxedSIMD",
29                                      "Enable relaxed-simd instructions">;
30
31def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
32                                      "Enable Atomics">;
33
34def FeatureNontrappingFPToInt :
35      SubtargetFeature<"nontrapping-fptoint",
36                       "HasNontrappingFPToInt", "true",
37                       "Enable non-trapping float-to-int conversion operators">;
38
39def FeatureSignExt :
40      SubtargetFeature<"sign-ext",
41                       "HasSignExt", "true",
42                       "Enable sign extension operators">;
43
44def FeatureTailCall :
45      SubtargetFeature<"tail-call",
46                       "HasTailCall", "true",
47                       "Enable tail call instructions">;
48
49def FeatureExceptionHandling :
50      SubtargetFeature<"exception-handling", "HasExceptionHandling", "true",
51                       "Enable Wasm exception handling">;
52
53def FeatureBulkMemory :
54      SubtargetFeature<"bulk-memory", "HasBulkMemory", "true",
55                       "Enable bulk memory operations">;
56
57def FeatureMultivalue :
58      SubtargetFeature<"multivalue",
59                       "HasMultivalue", "true",
60                       "Enable multivalue blocks, instructions, and functions">;
61
62def FeatureMutableGlobals :
63      SubtargetFeature<"mutable-globals", "HasMutableGlobals", "true",
64                       "Enable mutable globals">;
65
66def FeatureReferenceTypes :
67      SubtargetFeature<"reference-types", "HasReferenceTypes", "true",
68                       "Enable reference types">;
69
70//===----------------------------------------------------------------------===//
71// Architectures.
72//===----------------------------------------------------------------------===//
73
74//===----------------------------------------------------------------------===//
75// Register File Description
76//===----------------------------------------------------------------------===//
77
78include "WebAssemblyRegisterInfo.td"
79
80//===----------------------------------------------------------------------===//
81// Instruction Descriptions
82//===----------------------------------------------------------------------===//
83
84include "WebAssemblyInstrInfo.td"
85
86def WebAssemblyInstrInfo : InstrInfo;
87
88//===----------------------------------------------------------------------===//
89// WebAssembly Processors supported.
90//===----------------------------------------------------------------------===//
91
92// Minimal Viable Product.
93def : ProcessorModel<"mvp", NoSchedModel, []>;
94
95// Generic processor: latest stable version.
96def : ProcessorModel<"generic", NoSchedModel, []>;
97
98// Latest and greatest experimental version of WebAssembly. Bugs included!
99def : ProcessorModel<"bleeding-edge", NoSchedModel,
100                      [FeatureSIMD128, FeatureAtomics,
101                       FeatureNontrappingFPToInt, FeatureSignExt,
102                       FeatureMutableGlobals, FeatureBulkMemory,
103                       FeatureTailCall]>;
104
105//===----------------------------------------------------------------------===//
106// Target Declaration
107//===----------------------------------------------------------------------===//
108
109def WebAssemblyAsmParser : AsmParser {
110  // The physical register names are not in the binary format or asm text
111  let ShouldEmitMatchRegisterName = 0;
112}
113
114def WebAssemblyAsmWriter : AsmWriter {
115  string AsmWriterClassName  = "InstPrinter";
116  int PassSubtarget = 0;
117  int Variant = 0;
118  bit isMCAsmWriter = 1;
119}
120
121def WebAssembly : Target {
122  let InstructionSet = WebAssemblyInstrInfo;
123  let AssemblyParsers  = [WebAssemblyAsmParser];
124  let AssemblyWriters = [WebAssemblyAsmWriter];
125}
126