1//=- WebAssemblyInstrFormats.td - WebAssembly Instr. Formats -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// WebAssembly instruction format definitions.
11///
12//===----------------------------------------------------------------------===//
13
14// WebAssembly Instruction Format.
15// We instantiate 2 of these for every actual instruction (register based
16// and stack based), see below.
17class WebAssemblyInst<bits<32> inst, string asmstr, bit stack, bit is64>
18  : StackRel, RegisterRel, Wasm64Rel, Instruction {
19  bits<32> Inst = inst; // Instruction encoding.
20  bit StackBased = stack;
21  string BaseName = NAME;
22  bit IsWasm64 = is64;
23  string Wasm32Name = !subst("_A64", "_A32", NAME);
24  let Namespace   = "WebAssembly";
25  let Pattern     = [];
26  let AsmString   = asmstr;
27  // When there are multiple instructions that map to the same encoding (in
28  // e.g. the disassembler use case) prefer the one where IsCanonical == 1.
29  bit IsCanonical = 0;
30}
31
32// Normal instructions. Default instantiation of a WebAssemblyInst.
33class NI<dag oops, dag iops, list<dag> pattern, bit stack,
34         string asmstr = "", bits<32> inst = -1, bit is64 = false>
35    : WebAssemblyInst<inst, asmstr, stack, is64> {
36  dag OutOperandList = oops;
37  dag InOperandList  = iops;
38  let Pattern        = pattern;
39  let Defs           = [ARGUMENTS];
40}
41
42// Generates both register and stack based versions of one actual instruction.
43// We have 2 sets of operands (oops & iops) for the register and stack
44// based version of this instruction, as well as the corresponding asmstr.
45// The register versions have virtual-register operands which correspond to wasm
46// locals or stack locations. Each use and def of the register corresponds to an
47// implicit local.get / local.set or access of stack operands in wasm. These
48// instructions are used for ISel and all MI passes. The stack versions of the
49// instructions do not have register operands (they implicitly operate on the
50// stack), and local.gets and local.sets are explicit. The register instructions
51// are converted to their corresponding stack instructions before lowering to
52// MC.
53// Every instruction should want to be based on this multi-class to guarantee
54// there is always an equivalent pair of instructions.
55multiclass I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
56             list<dag> pattern_r, string asmstr_r = "", string asmstr_s = "",
57             bits<32> inst = -1, bit is64 = false> {
58  let isCodeGenOnly = 1 in
59  def "" : NI<oops_r, iops_r, pattern_r, false, asmstr_r, inst, is64>;
60  let BaseName = NAME in
61  def _S : NI<oops_s, iops_s, [], true, asmstr_s, inst, is64>;
62}
63
64// For instructions that have no register ops, so both sets are the same.
65multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
66               bits<32> inst = -1> {
67  defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;
68}
69