1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains the WebAssembly implementation of the
11 /// TargetInstrInfo class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyInstrInfo.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "Utils/WebAssemblyUtilities.h"
18 #include "WebAssembly.h"
19 #include "WebAssemblyMachineFunctionInfo.h"
20 #include "WebAssemblySubtarget.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "wasm-instr-info"
28 
29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "WebAssemblyGenInstrInfo.inc"
31 
32 // defines WebAssembly::getNamedOperandIdx
33 #define GET_INSTRINFO_NAMED_OPS
34 #include "WebAssemblyGenInstrInfo.inc"
35 
36 WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
37     : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
38                               WebAssembly::ADJCALLSTACKUP,
39                               WebAssembly::CATCHRET),
40       RI(STI.getTargetTriple()) {}
41 
42 bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
43     const MachineInstr &MI) const {
44   switch (MI.getOpcode()) {
45   case WebAssembly::CONST_I32:
46   case WebAssembly::CONST_I64:
47   case WebAssembly::CONST_F32:
48   case WebAssembly::CONST_F64:
49     // isReallyTriviallyReMaterializableGeneric misses these because of the
50     // ARGUMENTS implicit def, so we manualy override it here.
51     return true;
52   default:
53     return false;
54   }
55 }
56 
57 void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
58                                        MachineBasicBlock::iterator I,
59                                        const DebugLoc &DL, MCRegister DestReg,
60                                        MCRegister SrcReg, bool KillSrc) const {
61   // This method is called by post-RA expansion, which expects only pregs to
62   // exist. However we need to handle both here.
63   auto &MRI = MBB.getParent()->getRegInfo();
64   const TargetRegisterClass *RC =
65       Register::isVirtualRegister(DestReg)
66           ? MRI.getRegClass(DestReg)
67           : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
68 
69   unsigned CopyOpcode = WebAssembly::getCopyOpcodeForRegClass(RC);
70 
71   BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
72       .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
73 }
74 
75 MachineInstr *WebAssemblyInstrInfo::commuteInstructionImpl(
76     MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
77   // If the operands are stackified, we can't reorder them.
78   WebAssemblyFunctionInfo &MFI =
79       *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
80   if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
81       MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
82     return nullptr;
83 
84   // Otherwise use the default implementation.
85   return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
86 }
87 
88 // Branch analysis.
89 bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
90                                          MachineBasicBlock *&TBB,
91                                          MachineBasicBlock *&FBB,
92                                          SmallVectorImpl<MachineOperand> &Cond,
93                                          bool /*AllowModify*/) const {
94   const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
95   // WebAssembly has control flow that doesn't have explicit branches or direct
96   // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
97   // is created after CFGStackify.
98   if (MFI.isCFGStackified())
99     return true;
100 
101   bool HaveCond = false;
102   for (MachineInstr &MI : MBB.terminators()) {
103     switch (MI.getOpcode()) {
104     default:
105       // Unhandled instruction; bail out.
106       return true;
107     case WebAssembly::BR_IF:
108       if (HaveCond)
109         return true;
110       Cond.push_back(MachineOperand::CreateImm(true));
111       Cond.push_back(MI.getOperand(1));
112       TBB = MI.getOperand(0).getMBB();
113       HaveCond = true;
114       break;
115     case WebAssembly::BR_UNLESS:
116       if (HaveCond)
117         return true;
118       Cond.push_back(MachineOperand::CreateImm(false));
119       Cond.push_back(MI.getOperand(1));
120       TBB = MI.getOperand(0).getMBB();
121       HaveCond = true;
122       break;
123     case WebAssembly::BR:
124       if (!HaveCond)
125         TBB = MI.getOperand(0).getMBB();
126       else
127         FBB = MI.getOperand(0).getMBB();
128       break;
129     }
130     if (MI.isBarrier())
131       break;
132   }
133 
134   return false;
135 }
136 
137 unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
138                                             int *BytesRemoved) const {
139   assert(!BytesRemoved && "code size not handled");
140 
141   MachineBasicBlock::instr_iterator I = MBB.instr_end();
142   unsigned Count = 0;
143 
144   while (I != MBB.instr_begin()) {
145     --I;
146     if (I->isDebugInstr())
147       continue;
148     if (!I->isTerminator())
149       break;
150     // Remove the branch.
151     I->eraseFromParent();
152     I = MBB.instr_end();
153     ++Count;
154   }
155 
156   return Count;
157 }
158 
159 unsigned WebAssemblyInstrInfo::insertBranch(
160     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
161     ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
162   assert(!BytesAdded && "code size not handled");
163 
164   if (Cond.empty()) {
165     if (!TBB)
166       return 0;
167 
168     BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
169     return 1;
170   }
171 
172   assert(Cond.size() == 2 && "Expected a flag and a successor block");
173 
174   if (Cond[0].getImm())
175     BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
176   else
177     BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
178   if (!FBB)
179     return 1;
180 
181   BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
182   return 2;
183 }
184 
185 bool WebAssemblyInstrInfo::reverseBranchCondition(
186     SmallVectorImpl<MachineOperand> &Cond) const {
187   assert(Cond.size() == 2 && "Expected a flag and a condition expression");
188   Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
189   return false;
190 }
191 
192 ArrayRef<std::pair<int, const char *>>
193 WebAssemblyInstrInfo::getSerializableTargetIndices() const {
194   static const std::pair<int, const char *> TargetIndices[] = {
195       {WebAssembly::TI_LOCAL, "wasm-local"},
196       {WebAssembly::TI_GLOBAL_FIXED, "wasm-global-fixed"},
197       {WebAssembly::TI_OPERAND_STACK, "wasm-operand-stack"},
198       {WebAssembly::TI_GLOBAL_RELOC, "wasm-global-reloc"},
199       {WebAssembly::TI_LOCAL_INDIRECT, "wasm-local-indirect"}};
200   return makeArrayRef(TargetIndices);
201 }
202 
203 const MachineOperand &
204 WebAssemblyInstrInfo::getCalleeOperand(const MachineInstr &MI) const {
205   return WebAssembly::getCalleeOp(MI);
206 }
207