1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file includes code for rendering MCInst instances as AT&T-style
10 // assembly.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86ATTInstPrinter.h"
15 #include "X86BaseInfo.h"
16 #include "X86InstComments.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrAnalysis.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/Casting.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/Format.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include <cassert>
27 #include <cinttypes>
28 #include <cstdint>
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "asm-printer"
33 
34 // Include the auto-generated portion of the assembly writer.
35 #define PRINT_ALIAS_INSTR
36 #include "X86GenAsmWriter.inc"
37 
38 void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
39   OS << markup("<reg:") << '%' << getRegisterName(RegNo) << markup(">");
40 }
41 
42 void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
43                                   StringRef Annot, const MCSubtargetInfo &STI,
44                                   raw_ostream &OS) {
45   // If verbose assembly is enabled, we can print some informative comments.
46   if (CommentStream)
47     HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII);
48 
49   printInstFlags(MI, OS);
50 
51   // Output CALLpcrel32 as "callq" in 64-bit mode.
52   // In Intel annotation it's always emitted as "call".
53   //
54   // TODO: Probably this hack should be redesigned via InstAlias in
55   // InstrInfo.td as soon as Requires clause is supported properly
56   // for InstAlias.
57   if (MI->getOpcode() == X86::CALLpcrel32 &&
58       (STI.getFeatureBits()[X86::Mode64Bit])) {
59     OS << "\tcallq\t";
60     printPCRelImm(MI, Address, 0, OS);
61   }
62   // data16 and data32 both have the same encoding of 0x66. While data32 is
63   // valid only in 16 bit systems, data16 is valid in the rest.
64   // There seems to be some lack of support of the Requires clause that causes
65   // 0x66 to be interpreted as "data16" by the asm printer.
66   // Thus we add an adjustment here in order to print the "right" instruction.
67   else if (MI->getOpcode() == X86::DATA16_PREFIX &&
68            STI.getFeatureBits()[X86::Mode16Bit]) {
69    OS << "\tdata32";
70   }
71   // Try to print any aliases first.
72   else if (!printAliasInstr(MI, Address, OS) && !printVecCompareInstr(MI, OS))
73     printInstruction(MI, Address, OS);
74 
75   // Next always print the annotation.
76   printAnnotation(OS, Annot);
77 }
78 
79 bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
80                                              raw_ostream &OS) {
81   if (MI->getNumOperands() == 0 ||
82       !MI->getOperand(MI->getNumOperands() - 1).isImm())
83     return false;
84 
85   int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
86 
87   const MCInstrDesc &Desc = MII.get(MI->getOpcode());
88 
89   // Custom print the vector compare instructions to get the immediate
90   // translated into the mnemonic.
91   switch (MI->getOpcode()) {
92   case X86::CMPPDrmi:    case X86::CMPPDrri:
93   case X86::CMPPSrmi:    case X86::CMPPSrri:
94   case X86::CMPSDrm:     case X86::CMPSDrr:
95   case X86::CMPSDrm_Int: case X86::CMPSDrr_Int:
96   case X86::CMPSSrm:     case X86::CMPSSrr:
97   case X86::CMPSSrm_Int: case X86::CMPSSrr_Int:
98     if (Imm >= 0 && Imm <= 7) {
99       OS << '\t';
100       printCMPMnemonic(MI, /*IsVCMP*/false, OS);
101 
102       if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
103         if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
104           printdwordmem(MI, 2, OS);
105         else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
106           printqwordmem(MI, 2, OS);
107         else
108           printxmmwordmem(MI, 2, OS);
109       } else
110         printOperand(MI, 2, OS);
111 
112       // Skip operand 1 as its tied to the dest.
113 
114       OS << ", ";
115       printOperand(MI, 0, OS);
116       return true;
117     }
118     break;
119 
120   case X86::VCMPPDrmi:      case X86::VCMPPDrri:
121   case X86::VCMPPDYrmi:     case X86::VCMPPDYrri:
122   case X86::VCMPPDZ128rmi:  case X86::VCMPPDZ128rri:
123   case X86::VCMPPDZ256rmi:  case X86::VCMPPDZ256rri:
124   case X86::VCMPPDZrmi:     case X86::VCMPPDZrri:
125   case X86::VCMPPSrmi:      case X86::VCMPPSrri:
126   case X86::VCMPPSYrmi:     case X86::VCMPPSYrri:
127   case X86::VCMPPSZ128rmi:  case X86::VCMPPSZ128rri:
128   case X86::VCMPPSZ256rmi:  case X86::VCMPPSZ256rri:
129   case X86::VCMPPSZrmi:     case X86::VCMPPSZrri:
130   case X86::VCMPSDrm:       case X86::VCMPSDrr:
131   case X86::VCMPSDZrm:      case X86::VCMPSDZrr:
132   case X86::VCMPSDrm_Int:   case X86::VCMPSDrr_Int:
133   case X86::VCMPSDZrm_Int:  case X86::VCMPSDZrr_Int:
134   case X86::VCMPSSrm:       case X86::VCMPSSrr:
135   case X86::VCMPSSZrm:      case X86::VCMPSSZrr:
136   case X86::VCMPSSrm_Int:   case X86::VCMPSSrr_Int:
137   case X86::VCMPSSZrm_Int:  case X86::VCMPSSZrr_Int:
138   case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
139   case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
140   case X86::VCMPPDZrmik:    case X86::VCMPPDZrrik:
141   case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
142   case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
143   case X86::VCMPPSZrmik:    case X86::VCMPPSZrrik:
144   case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk:
145   case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk:
146   case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
147   case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
148   case X86::VCMPPDZrmbi:    case X86::VCMPPDZrmbik:
149   case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
150   case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
151   case X86::VCMPPSZrmbi:    case X86::VCMPPSZrmbik:
152   case X86::VCMPPDZrrib:    case X86::VCMPPDZrribk:
153   case X86::VCMPPSZrrib:    case X86::VCMPPSZrribk:
154   case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk:
155   case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk:
156     if (Imm >= 0 && Imm <= 31) {
157       OS << '\t';
158       printCMPMnemonic(MI, /*IsVCMP*/true, OS);
159 
160       unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2;
161 
162       if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
163         if (Desc.TSFlags & X86II::EVEX_B) {
164           // Broadcast form.
165           // Load size is based on W-bit.
166           if (Desc.TSFlags & X86II::VEX_W)
167             printqwordmem(MI, CurOp--, OS);
168           else
169             printdwordmem(MI, CurOp--, OS);
170 
171           // Print the number of elements broadcasted.
172           unsigned NumElts;
173           if (Desc.TSFlags & X86II::EVEX_L2)
174             NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
175           else if (Desc.TSFlags & X86II::VEX_L)
176             NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
177           else
178             NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
179           OS << "{1to" << NumElts << "}";
180         } else {
181           if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
182             printdwordmem(MI, CurOp--, OS);
183           else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
184             printqwordmem(MI, CurOp--, OS);
185           else if (Desc.TSFlags & X86II::EVEX_L2)
186             printzmmwordmem(MI, CurOp--, OS);
187           else if (Desc.TSFlags & X86II::VEX_L)
188             printymmwordmem(MI, CurOp--, OS);
189           else
190             printxmmwordmem(MI, CurOp--, OS);
191         }
192       } else {
193         if (Desc.TSFlags & X86II::EVEX_B)
194           OS << "{sae}, ";
195         printOperand(MI, CurOp--, OS);
196       }
197 
198       OS << ", ";
199       printOperand(MI, CurOp--, OS);
200       OS << ", ";
201       printOperand(MI, 0, OS);
202       if (CurOp > 0) {
203         // Print mask operand.
204         OS << " {";
205         printOperand(MI, CurOp--, OS);
206         OS << "}";
207       }
208 
209       return true;
210     }
211     break;
212 
213   case X86::VPCOMBmi:  case X86::VPCOMBri:
214   case X86::VPCOMDmi:  case X86::VPCOMDri:
215   case X86::VPCOMQmi:  case X86::VPCOMQri:
216   case X86::VPCOMUBmi: case X86::VPCOMUBri:
217   case X86::VPCOMUDmi: case X86::VPCOMUDri:
218   case X86::VPCOMUQmi: case X86::VPCOMUQri:
219   case X86::VPCOMUWmi: case X86::VPCOMUWri:
220   case X86::VPCOMWmi:  case X86::VPCOMWri:
221     if (Imm >= 0 && Imm <= 7) {
222       OS << '\t';
223       printVPCOMMnemonic(MI, OS);
224 
225       if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem)
226         printxmmwordmem(MI, 2, OS);
227       else
228         printOperand(MI, 2, OS);
229 
230       OS << ", ";
231       printOperand(MI, 1, OS);
232       OS << ", ";
233       printOperand(MI, 0, OS);
234       return true;
235     }
236     break;
237 
238   case X86::VPCMPBZ128rmi:   case X86::VPCMPBZ128rri:
239   case X86::VPCMPBZ256rmi:   case X86::VPCMPBZ256rri:
240   case X86::VPCMPBZrmi:      case X86::VPCMPBZrri:
241   case X86::VPCMPDZ128rmi:   case X86::VPCMPDZ128rri:
242   case X86::VPCMPDZ256rmi:   case X86::VPCMPDZ256rri:
243   case X86::VPCMPDZrmi:      case X86::VPCMPDZrri:
244   case X86::VPCMPQZ128rmi:   case X86::VPCMPQZ128rri:
245   case X86::VPCMPQZ256rmi:   case X86::VPCMPQZ256rri:
246   case X86::VPCMPQZrmi:      case X86::VPCMPQZrri:
247   case X86::VPCMPUBZ128rmi:  case X86::VPCMPUBZ128rri:
248   case X86::VPCMPUBZ256rmi:  case X86::VPCMPUBZ256rri:
249   case X86::VPCMPUBZrmi:     case X86::VPCMPUBZrri:
250   case X86::VPCMPUDZ128rmi:  case X86::VPCMPUDZ128rri:
251   case X86::VPCMPUDZ256rmi:  case X86::VPCMPUDZ256rri:
252   case X86::VPCMPUDZrmi:     case X86::VPCMPUDZrri:
253   case X86::VPCMPUQZ128rmi:  case X86::VPCMPUQZ128rri:
254   case X86::VPCMPUQZ256rmi:  case X86::VPCMPUQZ256rri:
255   case X86::VPCMPUQZrmi:     case X86::VPCMPUQZrri:
256   case X86::VPCMPUWZ128rmi:  case X86::VPCMPUWZ128rri:
257   case X86::VPCMPUWZ256rmi:  case X86::VPCMPUWZ256rri:
258   case X86::VPCMPUWZrmi:     case X86::VPCMPUWZrri:
259   case X86::VPCMPWZ128rmi:   case X86::VPCMPWZ128rri:
260   case X86::VPCMPWZ256rmi:   case X86::VPCMPWZ256rri:
261   case X86::VPCMPWZrmi:      case X86::VPCMPWZrri:
262   case X86::VPCMPBZ128rmik:  case X86::VPCMPBZ128rrik:
263   case X86::VPCMPBZ256rmik:  case X86::VPCMPBZ256rrik:
264   case X86::VPCMPBZrmik:     case X86::VPCMPBZrrik:
265   case X86::VPCMPDZ128rmik:  case X86::VPCMPDZ128rrik:
266   case X86::VPCMPDZ256rmik:  case X86::VPCMPDZ256rrik:
267   case X86::VPCMPDZrmik:     case X86::VPCMPDZrrik:
268   case X86::VPCMPQZ128rmik:  case X86::VPCMPQZ128rrik:
269   case X86::VPCMPQZ256rmik:  case X86::VPCMPQZ256rrik:
270   case X86::VPCMPQZrmik:     case X86::VPCMPQZrrik:
271   case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
272   case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
273   case X86::VPCMPUBZrmik:    case X86::VPCMPUBZrrik:
274   case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
275   case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
276   case X86::VPCMPUDZrmik:    case X86::VPCMPUDZrrik:
277   case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
278   case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
279   case X86::VPCMPUQZrmik:    case X86::VPCMPUQZrrik:
280   case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
281   case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik:
282   case X86::VPCMPUWZrmik:    case X86::VPCMPUWZrrik:
283   case X86::VPCMPWZ128rmik:  case X86::VPCMPWZ128rrik:
284   case X86::VPCMPWZ256rmik:  case X86::VPCMPWZ256rrik:
285   case X86::VPCMPWZrmik:     case X86::VPCMPWZrrik:
286   case X86::VPCMPDZ128rmib:  case X86::VPCMPDZ128rmibk:
287   case X86::VPCMPDZ256rmib:  case X86::VPCMPDZ256rmibk:
288   case X86::VPCMPDZrmib:     case X86::VPCMPDZrmibk:
289   case X86::VPCMPQZ128rmib:  case X86::VPCMPQZ128rmibk:
290   case X86::VPCMPQZ256rmib:  case X86::VPCMPQZ256rmibk:
291   case X86::VPCMPQZrmib:     case X86::VPCMPQZrmibk:
292   case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk:
293   case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk:
294   case X86::VPCMPUDZrmib:    case X86::VPCMPUDZrmibk:
295   case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk:
296   case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk:
297   case X86::VPCMPUQZrmib:    case X86::VPCMPUQZrmibk:
298     if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) {
299       OS << '\t';
300       printVPCMPMnemonic(MI, OS);
301 
302       unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2;
303 
304       if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
305         if (Desc.TSFlags & X86II::EVEX_B) {
306           // Broadcast form.
307           // Load size is based on W-bit as only D and Q are supported.
308           if (Desc.TSFlags & X86II::VEX_W)
309             printqwordmem(MI, CurOp--, OS);
310           else
311             printdwordmem(MI, CurOp--, OS);
312 
313           // Print the number of elements broadcasted.
314           unsigned NumElts;
315           if (Desc.TSFlags & X86II::EVEX_L2)
316             NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
317           else if (Desc.TSFlags & X86II::VEX_L)
318             NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
319           else
320             NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
321           OS << "{1to" << NumElts << "}";
322         } else {
323           if (Desc.TSFlags & X86II::EVEX_L2)
324             printzmmwordmem(MI, CurOp--, OS);
325           else if (Desc.TSFlags & X86II::VEX_L)
326             printymmwordmem(MI, CurOp--, OS);
327           else
328             printxmmwordmem(MI, CurOp--, OS);
329         }
330       } else {
331         printOperand(MI, CurOp--, OS);
332       }
333 
334       OS << ", ";
335       printOperand(MI, CurOp--, OS);
336       OS << ", ";
337       printOperand(MI, 0, OS);
338       if (CurOp > 0) {
339         // Print mask operand.
340         OS << " {";
341         printOperand(MI, CurOp--, OS);
342         OS << "}";
343       }
344 
345       return true;
346     }
347     break;
348   }
349 
350   return false;
351 }
352 
353 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
354                                      raw_ostream &O) {
355   const MCOperand &Op = MI->getOperand(OpNo);
356   if (Op.isReg()) {
357     printRegName(O, Op.getReg());
358   } else if (Op.isImm()) {
359     // Print immediates as signed values.
360     int64_t Imm = Op.getImm();
361     O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
362 
363     // TODO: This should be in a helper function in the base class, so it can
364     // be used by other printers.
365 
366     // If there are no instruction-specific comments, add a comment clarifying
367     // the hex value of the immediate operand when it isn't in the range
368     // [-256,255].
369     if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) {
370       // Don't print unnecessary hex sign bits.
371       if (Imm == (int16_t)(Imm))
372         *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm);
373       else if (Imm == (int32_t)(Imm))
374         *CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm);
375       else
376         *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm);
377     }
378   } else {
379     assert(Op.isExpr() && "unknown operand kind in printOperand");
380     O << markup("<imm:") << '$';
381     Op.getExpr()->print(O, &MAI);
382     O << markup(">");
383   }
384 }
385 
386 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
387                                           raw_ostream &O) {
388   // Do not print the exact form of the memory operand if it references a known
389   // binary object.
390   if (SymbolizeOperands && MIA) {
391     uint64_t Target;
392     if (MIA->evaluateBranch(*MI, 0, 0, Target))
393       return;
394     if (MIA->evaluateMemoryOperandAddress(*MI, 0, 0))
395       return;
396   }
397 
398   const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
399   const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
400   const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
401 
402   O << markup("<mem:");
403 
404   // If this has a segment register, print it.
405   printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
406 
407   if (DispSpec.isImm()) {
408     int64_t DispVal = DispSpec.getImm();
409     if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
410       O << formatImm(DispVal);
411   } else {
412     assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
413     DispSpec.getExpr()->print(O, &MAI);
414   }
415 
416   if (IndexReg.getReg() || BaseReg.getReg()) {
417     O << '(';
418     if (BaseReg.getReg())
419       printOperand(MI, Op + X86::AddrBaseReg, O);
420 
421     if (IndexReg.getReg()) {
422       O << ',';
423       printOperand(MI, Op + X86::AddrIndexReg, O);
424       unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
425       if (ScaleVal != 1) {
426         O << ',' << markup("<imm:") << ScaleVal // never printed in hex.
427           << markup(">");
428       }
429     }
430     O << ')';
431   }
432 
433   O << markup(">");
434 }
435 
436 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
437                                     raw_ostream &O) {
438   O << markup("<mem:");
439 
440   // If this has a segment register, print it.
441   printOptionalSegReg(MI, Op + 1, O);
442 
443   O << "(";
444   printOperand(MI, Op, O);
445   O << ")";
446 
447   O << markup(">");
448 }
449 
450 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
451                                     raw_ostream &O) {
452   O << markup("<mem:");
453 
454   O << "%es:(";
455   printOperand(MI, Op, O);
456   O << ")";
457 
458   O << markup(">");
459 }
460 
461 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
462                                        raw_ostream &O) {
463   const MCOperand &DispSpec = MI->getOperand(Op);
464 
465   O << markup("<mem:");
466 
467   // If this has a segment register, print it.
468   printOptionalSegReg(MI, Op + 1, O);
469 
470   if (DispSpec.isImm()) {
471     O << formatImm(DispSpec.getImm());
472   } else {
473     assert(DispSpec.isExpr() && "non-immediate displacement?");
474     DispSpec.getExpr()->print(O, &MAI);
475   }
476 
477   O << markup(">");
478 }
479 
480 void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
481                                    raw_ostream &O) {
482   if (MI->getOperand(Op).isExpr())
483     return printOperand(MI, Op, O);
484 
485   O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
486     << markup(">");
487 }
488 
489 void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
490                                            raw_ostream &OS) {
491   const MCOperand &Op = MI->getOperand(OpNo);
492   unsigned Reg = Op.getReg();
493   // Override the default printing to print st(0) instead st.
494   if (Reg == X86::ST0)
495     OS << markup("<reg:") << "%st(0)" << markup(">");
496   else
497     printRegName(OS, Reg);
498 }
499