1 //===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file exposes functions that may be used with BuildMI from the
10 // MachineInstrBuilder.h file to handle X86'isms in a clean way.
11 //
12 // The BuildMem function may be used with the BuildMI function to add entire
13 // memory references in a single, typed, function call.  X86 memory references
14 // can be very complex expressions (described in the README), so wrapping them
15 // up behind an easier to use interface makes sense.  Descriptions of the
16 // functions are included below.
17 //
18 // For reference, the order of operands for memory references is:
19 // (Operand), Base, Scale, Index, Displacement.
20 //
21 //===----------------------------------------------------------------------===//
22 
23 #ifndef LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
24 #define LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
25 
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineOperand.h"
33 #include "llvm/MC/MCInstrDesc.h"
34 #include <cassert>
35 
36 namespace llvm {
37 
38 /// X86AddressMode - This struct holds a generalized full x86 address mode.
39 /// The base register can be a frame index, which will eventually be replaced
40 /// with BP or SP and Disp being offsetted accordingly.  The displacement may
41 /// also include the offset of a global value.
42 struct X86AddressMode {
43   enum {
44     RegBase,
45     FrameIndexBase
46   } BaseType;
47 
48   union {
49     unsigned Reg;
50     int FrameIndex;
51   } Base;
52 
53   unsigned Scale;
54   unsigned IndexReg;
55   int Disp;
56   const GlobalValue *GV;
57   unsigned GVOpFlags;
58 
59   X86AddressMode()
60     : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
61       GVOpFlags(0) {
62     Base.Reg = 0;
63   }
64 
65   void getFullAddress(SmallVectorImpl<MachineOperand> &MO) {
66     assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);
67 
68     if (BaseType == X86AddressMode::RegBase)
69       MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false,
70                                              false, false, false, 0, false));
71     else {
72       assert(BaseType == X86AddressMode::FrameIndexBase);
73       MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
74     }
75 
76     MO.push_back(MachineOperand::CreateImm(Scale));
77     MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false,
78                                            false, false, 0, false));
79 
80     if (GV)
81       MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
82     else
83       MO.push_back(MachineOperand::CreateImm(Disp));
84 
85     MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false,
86                                            false, 0, false));
87   }
88 };
89 
90 /// Compute the addressing mode from an machine instruction starting with the
91 /// given operand.
92 static inline X86AddressMode getAddressFromInstr(const MachineInstr *MI,
93                                                  unsigned Operand) {
94   X86AddressMode AM;
95   const MachineOperand &Op0 = MI->getOperand(Operand);
96   if (Op0.isReg()) {
97     AM.BaseType = X86AddressMode::RegBase;
98     AM.Base.Reg = Op0.getReg();
99   } else {
100     AM.BaseType = X86AddressMode::FrameIndexBase;
101     AM.Base.FrameIndex = Op0.getIndex();
102   }
103 
104   const MachineOperand &Op1 = MI->getOperand(Operand + 1);
105   AM.Scale = Op1.getImm();
106 
107   const MachineOperand &Op2 = MI->getOperand(Operand + 2);
108   AM.IndexReg = Op2.getReg();
109 
110   const MachineOperand &Op3 = MI->getOperand(Operand + 3);
111   if (Op3.isGlobal())
112     AM.GV = Op3.getGlobal();
113   else
114     AM.Disp = Op3.getImm();
115 
116   return AM;
117 }
118 
119 /// addDirectMem - This function is used to add a direct memory reference to the
120 /// current instruction -- that is, a dereference of an address in a register,
121 /// with no scale, index or displacement. An example is: DWORD PTR [EAX].
122 ///
123 static inline const MachineInstrBuilder &
124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
125   // Because memory references are always represented with five
126   // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
127   return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
128 }
129 
130 /// Replace the address used in the instruction with the direct memory
131 /// reference.
132 static inline void setDirectAddressInInstr(MachineInstr *MI, unsigned Operand,
133                                            unsigned Reg) {
134   // Direct memory address is in a form of: Reg, 1 (Scale), NoReg, 0, NoReg.
135   MI->getOperand(Operand).setReg(Reg);
136   MI->getOperand(Operand + 1).setImm(1);
137   MI->getOperand(Operand + 2).setReg(0);
138   MI->getOperand(Operand + 3).setImm(0);
139   MI->getOperand(Operand + 4).setReg(0);
140 }
141 
142 static inline const MachineInstrBuilder &
143 addOffset(const MachineInstrBuilder &MIB, int Offset) {
144   return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
145 }
146 
147 static inline const MachineInstrBuilder &
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) {
149   return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
150 }
151 
152 /// addRegOffset - This function is used to add a memory reference of the form
153 /// [Reg + Offset], i.e., one with no scale or index, but with a
154 /// displacement. An example is: DWORD PTR [EAX + 4].
155 ///
156 static inline const MachineInstrBuilder &
157 addRegOffset(const MachineInstrBuilder &MIB,
158              unsigned Reg, bool isKill, int Offset) {
159   return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
160 }
161 
162 /// addRegReg - This function is used to add a memory reference of the form:
163 /// [Reg + Reg].
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
165                                             unsigned Reg1, bool isKill1,
166                                             unsigned Reg2, bool isKill2) {
167   return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168     .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
169 }
170 
171 static inline const MachineInstrBuilder &
172 addFullAddress(const MachineInstrBuilder &MIB,
173                const X86AddressMode &AM) {
174   assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
175 
176   if (AM.BaseType == X86AddressMode::RegBase)
177     MIB.addReg(AM.Base.Reg);
178   else {
179     assert(AM.BaseType == X86AddressMode::FrameIndexBase);
180     MIB.addFrameIndex(AM.Base.FrameIndex);
181   }
182 
183   MIB.addImm(AM.Scale).addReg(AM.IndexReg);
184   if (AM.GV)
185     MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
186   else
187     MIB.addImm(AM.Disp);
188 
189   return MIB.addReg(0);
190 }
191 
192 /// addFrameReference - This function is used to add a reference to the base of
193 /// an abstract object on the stack frame of the current function.  This
194 /// reference has base register as the FrameIndex offset until it is resolved.
195 /// This allows a constant offset to be specified as well...
196 ///
197 static inline const MachineInstrBuilder &
198 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
199   MachineInstr *MI = MIB;
200   MachineFunction &MF = *MI->getParent()->getParent();
201   MachineFrameInfo &MFI = MF.getFrameInfo();
202   const MCInstrDesc &MCID = MI->getDesc();
203   auto Flags = MachineMemOperand::MONone;
204   if (MCID.mayLoad())
205     Flags |= MachineMemOperand::MOLoad;
206   if (MCID.mayStore())
207     Flags |= MachineMemOperand::MOStore;
208   MachineMemOperand *MMO = MF.getMachineMemOperand(
209       MachinePointerInfo::getFixedStack(MF, FI, Offset), Flags,
210       MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
211   return addOffset(MIB.addFrameIndex(FI), Offset)
212             .addMemOperand(MMO);
213 }
214 
215 /// addConstantPoolReference - This function is used to add a reference to the
216 /// base of a constant value spilled to the per-function constant pool.  The
217 /// reference uses the abstract ConstantPoolIndex which is retained until
218 /// either machine code emission or assembly output. In PIC mode on x86-32,
219 /// the GlobalBaseReg parameter can be used to make this a
220 /// GlobalBaseReg-relative reference.
221 ///
222 static inline const MachineInstrBuilder &
223 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
224                          unsigned GlobalBaseReg, unsigned char OpFlags) {
225   //FIXME: factor this
226   return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
227     .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
228 }
229 
230 } // end namespace llvm
231 
232 #endif // LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
233