1//===-- X86SchedPredicates.td - X86 Scheduling Predicates --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines scheduling predicate definitions that are common to
10// all X86 subtargets.
11//
12//===----------------------------------------------------------------------===//
13
14// A predicate used to identify dependency-breaking instructions that clear the
15// content of the destination register. Note that this predicate only checks if
16// input registers are the same. This predicate doesn't make any assumptions on
17// the expected instruction opcodes, because different processors may implement
18// different zero-idioms.
19def ZeroIdiomPredicate : CheckSameRegOperand<1, 2>;
20
21// A predicate used to identify VPERM that have bits 3 and 7 of their mask set.
22// On some processors, these VPERM instructions are zero-idioms.
23def ZeroIdiomVPERMPredicate : CheckAll<[
24  ZeroIdiomPredicate,
25  CheckImmOperand<3, 0x88>
26]>;
27
28// A predicate used to check if a LEA instruction uses all three source
29// operands: base, index, and offset.
30def IsThreeOperandsLEAPredicate: CheckAll<[
31  // isRegOperand(Base)
32  CheckIsRegOperand<1>,
33  CheckNot<CheckInvalidRegOperand<1>>,
34
35  // isRegOperand(Index)
36  CheckIsRegOperand<3>,
37  CheckNot<CheckInvalidRegOperand<3>>,
38
39  // hasLEAOffset(Offset)
40  CheckAny<[
41    CheckAll<[
42      CheckIsImmOperand<4>,
43      CheckNot<CheckZeroOperand<4>>
44    ]>,
45    CheckNonPortable<"MI.getOperand(4).isGlobal()">
46  ]>
47]>;
48
49def LEACases : MCOpcodeSwitchCase<
50    [LEA32r, LEA64r, LEA64_32r, LEA16r],
51    MCReturnStatement<IsThreeOperandsLEAPredicate>
52>;
53
54// Used to generate the body of a TII member function.
55def IsThreeOperandsLEABody :
56    MCOpcodeSwitchStatement<[LEACases], MCReturnStatement<FalsePred>>;
57
58// This predicate evaluates to true only if the input machine instruction is a
59// 3-operands LEA.  Tablegen automatically generates a new method for it in
60// X86GenInstrInfo.
61def IsThreeOperandsLEAFn :
62    TIIPredicate<"isThreeOperandsLEA", IsThreeOperandsLEABody>;
63
64// A predicate to check for COND_A and COND_BE CMOVs which have an extra uop
65// on recent Intel CPUs.
66def IsCMOVArr_Or_CMOVBErr : CheckAny<[
67  CheckImmOperand_s<3, "X86::COND_A">,
68  CheckImmOperand_s<3, "X86::COND_BE">
69]>;
70
71def IsCMOVArm_Or_CMOVBErm : CheckAny<[
72  CheckImmOperand_s<7, "X86::COND_A">,
73  CheckImmOperand_s<7, "X86::COND_BE">
74]>;
75
76// A predicate to check for COND_A and COND_BE SETCCs which have an extra uop
77// on recent Intel CPUs.
78def IsSETAr_Or_SETBEr : CheckAny<[
79  CheckImmOperand_s<1, "X86::COND_A">,
80  CheckImmOperand_s<1, "X86::COND_BE">
81]>;
82
83def IsSETAm_Or_SETBEm : CheckAny<[
84  CheckImmOperand_s<5, "X86::COND_A">,
85  CheckImmOperand_s<5, "X86::COND_BE">
86]>;
87
88// A predicate used to check if an instruction has a LOCK prefix.
89def CheckLockPrefix : CheckFunctionPredicate<
90  "X86_MC::hasLockPrefix",
91  "X86InstrInfo::hasLockPrefix"
92>;
93
94def IsRegRegCompareAndSwap_8 : CheckOpcode<[ CMPXCHG8rr ]>;
95
96def IsRegMemCompareAndSwap_8 : CheckOpcode<[
97  LCMPXCHG8, CMPXCHG8rm
98]>;
99
100def IsRegRegCompareAndSwap_16_32_64  : CheckOpcode<[
101  CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr
102]>;
103
104def IsRegMemCompareAndSwap_16_32_64  : CheckOpcode<[
105  CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm,
106  LCMPXCHG16, LCMPXCHG32, LCMPXCHG64,
107  LCMPXCHG8B, LCMPXCHG16B
108]>;
109
110def IsCompareAndSwap8B  : CheckOpcode<[ CMPXCHG8B, LCMPXCHG8B ]>;
111def IsCompareAndSwap16B : CheckOpcode<[ CMPXCHG16B, LCMPXCHG16B ]>;
112
113def IsRegMemCompareAndSwap  : CheckOpcode<
114  !listconcat(
115    IsRegMemCompareAndSwap_8.ValidOpcodes,
116    IsRegMemCompareAndSwap_16_32_64.ValidOpcodes
117  )>;
118
119def IsRegRegCompareAndSwap  : CheckOpcode<
120  !listconcat(
121    IsRegRegCompareAndSwap_8.ValidOpcodes,
122    IsRegRegCompareAndSwap_16_32_64.ValidOpcodes
123  )>;
124
125def IsAtomicCompareAndSwap_8 : CheckAll<[
126  CheckLockPrefix,
127  IsRegMemCompareAndSwap_8
128]>;
129
130def IsAtomicCompareAndSwap : CheckAll<[
131  CheckLockPrefix,
132  IsRegMemCompareAndSwap
133]>;
134
135def IsAtomicCompareAndSwap8B : CheckAll<[
136  CheckLockPrefix,
137  IsCompareAndSwap8B
138]>;
139
140def IsAtomicCompareAndSwap16B : CheckAll<[
141  CheckLockPrefix,
142  IsCompareAndSwap16B
143]>;
144