10b57cec5SDimitry Andric //===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the XCore implementation of the TargetInstrInfo class. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "XCoreRegisterInfo.h" 170b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 180b57cec5SDimitry Andric 190b57cec5SDimitry Andric #define GET_INSTRINFO_HEADER 200b57cec5SDimitry Andric #include "XCoreGenInstrInfo.inc" 210b57cec5SDimitry Andric 220b57cec5SDimitry Andric namespace llvm { 230b57cec5SDimitry Andric 240b57cec5SDimitry Andric class XCoreInstrInfo : public XCoreGenInstrInfo { 250b57cec5SDimitry Andric const XCoreRegisterInfo RI; 260b57cec5SDimitry Andric virtual void anchor(); 270b57cec5SDimitry Andric public: 280b57cec5SDimitry Andric XCoreInstrInfo(); 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 310b57cec5SDimitry Andric /// such, whenever a client has an instance of instruction info, it should 320b57cec5SDimitry Andric /// always be able to get register info as well (through this method). 330b57cec5SDimitry Andric /// getRegisterInfo()340b57cec5SDimitry Andric const TargetRegisterInfo &getRegisterInfo() const { return RI; } 350b57cec5SDimitry Andric 360b57cec5SDimitry Andric /// isLoadFromStackSlot - If the specified machine instruction is a direct 370b57cec5SDimitry Andric /// load from a stack slot, return the virtual or physical register number of 380b57cec5SDimitry Andric /// the destination along with the FrameIndex of the loaded stack slot. If 390b57cec5SDimitry Andric /// not, return 0. This predicate must return 0 if the instruction has 400b57cec5SDimitry Andric /// any side effects other than loading from the stack slot. 410b57cec5SDimitry Andric unsigned isLoadFromStackSlot(const MachineInstr &MI, 420b57cec5SDimitry Andric int &FrameIndex) const override; 430b57cec5SDimitry Andric 440b57cec5SDimitry Andric /// isStoreToStackSlot - If the specified machine instruction is a direct 450b57cec5SDimitry Andric /// store to a stack slot, return the virtual or physical register number of 460b57cec5SDimitry Andric /// the source reg along with the FrameIndex of the loaded stack slot. If 470b57cec5SDimitry Andric /// not, return 0. This predicate must return 0 if the instruction has 480b57cec5SDimitry Andric /// any side effects other than storing to the stack slot. 490b57cec5SDimitry Andric unsigned isStoreToStackSlot(const MachineInstr &MI, 500b57cec5SDimitry Andric int &FrameIndex) const override; 510b57cec5SDimitry Andric 520b57cec5SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 530b57cec5SDimitry Andric MachineBasicBlock *&FBB, 540b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 550b57cec5SDimitry Andric bool AllowModify) const override; 560b57cec5SDimitry Andric 570b57cec5SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 580b57cec5SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 590b57cec5SDimitry Andric const DebugLoc &DL, 600b57cec5SDimitry Andric int *BytesAdded = nullptr) const override; 610b57cec5SDimitry Andric 620b57cec5SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 630b57cec5SDimitry Andric int *BytesRemoved = nullptr) const override; 640b57cec5SDimitry Andric 650b57cec5SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 66480093f4SDimitry Andric const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 670b57cec5SDimitry Andric bool KillSrc) const override; 680b57cec5SDimitry Andric 690b57cec5SDimitry Andric void storeRegToStackSlot(MachineBasicBlock &MBB, 70bdd1243dSDimitry Andric MachineBasicBlock::iterator MI, Register SrcReg, 71bdd1243dSDimitry Andric bool isKill, int FrameIndex, 720b57cec5SDimitry Andric const TargetRegisterClass *RC, 73bdd1243dSDimitry Andric const TargetRegisterInfo *TRI, 74bdd1243dSDimitry Andric Register VReg) const override; 750b57cec5SDimitry Andric 760b57cec5SDimitry Andric void loadRegFromStackSlot(MachineBasicBlock &MBB, 77bdd1243dSDimitry Andric MachineBasicBlock::iterator MI, Register DestReg, 78bdd1243dSDimitry Andric int FrameIndex, const TargetRegisterClass *RC, 79bdd1243dSDimitry Andric const TargetRegisterInfo *TRI, 80bdd1243dSDimitry Andric Register VReg) const override; 810b57cec5SDimitry Andric 820b57cec5SDimitry Andric bool reverseBranchCondition( 830b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond) const override; 840b57cec5SDimitry Andric 850b57cec5SDimitry Andric // Emit code before MBBI to load immediate value into physical register Reg. 860b57cec5SDimitry Andric // Returns an iterator to the new instruction. 870b57cec5SDimitry Andric MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, 880b57cec5SDimitry Andric MachineBasicBlock::iterator MI, 890b57cec5SDimitry Andric unsigned Reg, uint64_t Value) const; 900b57cec5SDimitry Andric }; 910b57cec5SDimitry Andric 920b57cec5SDimitry Andric } 930b57cec5SDimitry Andric 940b57cec5SDimitry Andric #endif 95