1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines structures to encapsulate information gleaned from the 10 // target register and register class definitions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H 15 #define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H 16 17 #include "CodeGenHwModes.h" 18 #include "InfoByHwMode.h" 19 #include "llvm/ADT/ArrayRef.h" 20 #include "llvm/ADT/BitVector.h" 21 #include "llvm/ADT/DenseMap.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/ADT/SetVector.h" 24 #include "llvm/ADT/SmallPtrSet.h" 25 #include "llvm/ADT/SmallVector.h" 26 #include "llvm/ADT/SparseBitVector.h" 27 #include "llvm/ADT/StringMap.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/MC/LaneBitmask.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/TableGen/Record.h" 32 #include "llvm/TableGen/SetTheory.h" 33 #include <cassert> 34 #include <cstdint> 35 #include <deque> 36 #include <functional> 37 #include <list> 38 #include <map> 39 #include <memory> 40 #include <optional> 41 #include <string> 42 #include <utility> 43 #include <vector> 44 45 namespace llvm { 46 47 class CodeGenRegBank; 48 49 /// Used to encode a step in a register lane mask transformation. 50 /// Mask the bits specified in Mask, then rotate them Rol bits to the left 51 /// assuming a wraparound at 32bits. 52 struct MaskRolPair { 53 LaneBitmask Mask; 54 uint8_t RotateLeft; 55 56 bool operator==(const MaskRolPair Other) const { 57 return Mask == Other.Mask && RotateLeft == Other.RotateLeft; 58 } 59 bool operator!=(const MaskRolPair Other) const { 60 return Mask != Other.Mask || RotateLeft != Other.RotateLeft; 61 } 62 }; 63 64 /// CodeGenSubRegIndex - Represents a sub-register index. 65 class CodeGenSubRegIndex { 66 Record *const TheDef; 67 std::string Name; 68 std::string Namespace; 69 70 public: 71 uint16_t Size; 72 uint16_t Offset; 73 const unsigned EnumValue; 74 mutable LaneBitmask LaneMask; 75 mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform; 76 77 /// A list of subregister indexes concatenated resulting in this 78 /// subregister index. This is the reverse of CodeGenRegBank::ConcatIdx. 79 SmallVector<CodeGenSubRegIndex*,4> ConcatenationOf; 80 81 // Are all super-registers containing this SubRegIndex covered by their 82 // sub-registers? 83 bool AllSuperRegsCovered; 84 // A subregister index is "artificial" if every subregister obtained 85 // from applying this index is artificial. Artificial subregister 86 // indexes are not used to create new register classes. 87 bool Artificial; 88 89 CodeGenSubRegIndex(Record *R, unsigned Enum); 90 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum); 91 CodeGenSubRegIndex(CodeGenSubRegIndex&) = delete; 92 93 const std::string &getName() const { return Name; } 94 const std::string &getNamespace() const { return Namespace; } 95 std::string getQualifiedName() const; 96 97 // Map of composite subreg indices. 98 typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *, 99 deref<std::less<>>> 100 CompMap; 101 102 // Returns the subreg index that results from composing this with Idx. 103 // Returns NULL if this and Idx don't compose. 104 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const { 105 CompMap::const_iterator I = Composed.find(Idx); 106 return I == Composed.end() ? nullptr : I->second; 107 } 108 109 // Add a composite subreg index: this+A = B. 110 // Return a conflicting composite, or NULL 111 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A, 112 CodeGenSubRegIndex *B) { 113 assert(A && B); 114 std::pair<CompMap::iterator, bool> Ins = 115 Composed.insert(std::make_pair(A, B)); 116 // Synthetic subreg indices that aren't contiguous (for instance ARM 117 // register tuples) don't have a bit range, so it's OK to let 118 // B->Offset == -1. For the other cases, accumulate the offset and set 119 // the size here. Only do so if there is no offset yet though. 120 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) && 121 (B->Offset == (uint16_t)-1)) { 122 B->Offset = Offset + A->Offset; 123 B->Size = A->Size; 124 } 125 return (Ins.second || Ins.first->second == B) ? nullptr 126 : Ins.first->second; 127 } 128 129 // Update the composite maps of components specified in 'ComposedOf'. 130 void updateComponents(CodeGenRegBank&); 131 132 // Return the map of composites. 133 const CompMap &getComposites() const { return Composed; } 134 135 // Compute LaneMask from Composed. Return LaneMask. 136 LaneBitmask computeLaneMask() const; 137 138 void setConcatenationOf(ArrayRef<CodeGenSubRegIndex*> Parts); 139 140 /// Replaces subregister indexes in the `ConcatenationOf` list with 141 /// list of subregisters they are composed of (if any). Do this recursively. 142 void computeConcatTransitiveClosure(); 143 144 bool operator<(const CodeGenSubRegIndex &RHS) const { 145 return this->EnumValue < RHS.EnumValue; 146 } 147 148 private: 149 CompMap Composed; 150 }; 151 152 /// CodeGenRegister - Represents a register definition. 153 class CodeGenRegister { 154 public: 155 Record *TheDef; 156 unsigned EnumValue; 157 std::vector<int64_t> CostPerUse; 158 bool CoveredBySubRegs = true; 159 bool HasDisjunctSubRegs = false; 160 bool Artificial = true; 161 bool Constant = false; 162 163 // Map SubRegIndex -> Register. 164 typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, 165 deref<std::less<>>> 166 SubRegMap; 167 168 CodeGenRegister(Record *R, unsigned Enum); 169 170 StringRef getName() const; 171 172 // Extract more information from TheDef. This is used to build an object 173 // graph after all CodeGenRegister objects have been created. 174 void buildObjectGraph(CodeGenRegBank&); 175 176 // Lazily compute a map of all sub-registers. 177 // This includes unique entries for all sub-sub-registers. 178 const SubRegMap &computeSubRegs(CodeGenRegBank&); 179 180 // Compute extra sub-registers by combining the existing sub-registers. 181 void computeSecondarySubRegs(CodeGenRegBank&); 182 183 // Add this as a super-register to all sub-registers after the sub-register 184 // graph has been built. 185 void computeSuperRegs(CodeGenRegBank&); 186 187 const SubRegMap &getSubRegs() const { 188 assert(SubRegsComplete && "Must precompute sub-registers"); 189 return SubRegs; 190 } 191 192 // Add sub-registers to OSet following a pre-order defined by the .td file. 193 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet, 194 CodeGenRegBank&) const; 195 196 // Return the sub-register index naming Reg as a sub-register of this 197 // register. Returns NULL if Reg is not a sub-register. 198 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const { 199 return SubReg2Idx.lookup(Reg); 200 } 201 202 typedef std::vector<const CodeGenRegister*> SuperRegList; 203 204 // Get the list of super-registers in topological order, small to large. 205 // This is valid after computeSubRegs visits all registers during RegBank 206 // construction. 207 const SuperRegList &getSuperRegs() const { 208 assert(SubRegsComplete && "Must precompute sub-registers"); 209 return SuperRegs; 210 } 211 212 // Get the list of ad hoc aliases. The graph is symmetric, so the list 213 // contains all registers in 'Aliases', and all registers that mention this 214 // register in 'Aliases'. 215 ArrayRef<CodeGenRegister*> getExplicitAliases() const { 216 return ExplicitAliases; 217 } 218 219 // Get the topological signature of this register. This is a small integer 220 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have 221 // identical sub-register structure. That is, they support the same set of 222 // sub-register indices mapping to the same kind of sub-registers 223 // (TopoSig-wise). 224 unsigned getTopoSig() const { 225 assert(SuperRegsComplete && "TopoSigs haven't been computed yet."); 226 return TopoSig; 227 } 228 229 // List of register units in ascending order. 230 typedef SparseBitVector<> RegUnitList; 231 typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList; 232 233 // How many entries in RegUnitList are native? 234 RegUnitList NativeRegUnits; 235 236 // Get the list of register units. 237 // This is only valid after computeSubRegs() completes. 238 const RegUnitList &getRegUnits() const { return RegUnits; } 239 240 ArrayRef<LaneBitmask> getRegUnitLaneMasks() const { 241 return ArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count()); 242 } 243 244 // Get the native register units. This is a prefix of getRegUnits(). 245 RegUnitList getNativeRegUnits() const { 246 return NativeRegUnits; 247 } 248 249 void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) { 250 RegUnitLaneMasks = LaneMasks; 251 } 252 253 // Inherit register units from subregisters. 254 // Return true if the RegUnits changed. 255 bool inheritRegUnits(CodeGenRegBank &RegBank); 256 257 // Adopt a register unit for pressure tracking. 258 // A unit is adopted iff its unit number is >= NativeRegUnits.count(). 259 void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); } 260 261 // Get the sum of this register's register unit weights. 262 unsigned getWeight(const CodeGenRegBank &RegBank) const; 263 264 // Canonically ordered set. 265 typedef std::vector<const CodeGenRegister*> Vec; 266 267 private: 268 bool SubRegsComplete; 269 bool SuperRegsComplete; 270 unsigned TopoSig; 271 272 // The sub-registers explicit in the .td file form a tree. 273 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices; 274 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs; 275 276 // Explicit ad hoc aliases, symmetrized to form an undirected graph. 277 SmallVector<CodeGenRegister*, 8> ExplicitAliases; 278 279 // Super-registers where this is the first explicit sub-register. 280 SuperRegList LeadingSuperRegs; 281 282 SubRegMap SubRegs; 283 SuperRegList SuperRegs; 284 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx; 285 RegUnitList RegUnits; 286 RegUnitLaneMaskList RegUnitLaneMasks; 287 }; 288 289 inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) { 290 return A.EnumValue < B.EnumValue; 291 } 292 293 inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) { 294 return A.EnumValue == B.EnumValue; 295 } 296 297 class CodeGenRegisterClass { 298 CodeGenRegister::Vec Members; 299 // Allocation orders. Order[0] always contains all registers in Members. 300 std::vector<SmallVector<Record*, 16>> Orders; 301 // Bit mask of sub-classes including this, indexed by their EnumValue. 302 BitVector SubClasses; 303 // List of super-classes, topologocally ordered to have the larger classes 304 // first. This is the same as sorting by EnumValue. 305 SmallVector<CodeGenRegisterClass*, 4> SuperClasses; 306 Record *TheDef; 307 std::string Name; 308 309 // For a synthesized class, inherit missing properties from the nearest 310 // super-class. 311 void inheritProperties(CodeGenRegBank&); 312 313 // Map SubRegIndex -> sub-class. This is the largest sub-class where all 314 // registers have a SubRegIndex sub-register. 315 DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *> 316 SubClassWithSubReg; 317 318 // Map SubRegIndex -> set of super-reg classes. This is all register 319 // classes SuperRC such that: 320 // 321 // R:SubRegIndex in this RC for all R in SuperRC. 322 // 323 DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>> 324 SuperRegClasses; 325 326 // Bit vector of TopoSigs for the registers in this class. This will be 327 // very sparse on regular architectures. 328 BitVector TopoSigs; 329 330 public: 331 unsigned EnumValue; 332 StringRef Namespace; 333 SmallVector<ValueTypeByHwMode, 4> VTs; 334 RegSizeInfoByHwMode RSI; 335 int CopyCost; 336 bool Allocatable; 337 StringRef AltOrderSelect; 338 uint8_t AllocationPriority; 339 bool GlobalPriority; 340 uint8_t TSFlags; 341 /// Contains the combination of the lane masks of all subregisters. 342 LaneBitmask LaneMask; 343 /// True if there are at least 2 subregisters which do not interfere. 344 bool HasDisjunctSubRegs; 345 bool CoveredBySubRegs; 346 /// A register class is artificial if all its members are artificial. 347 bool Artificial; 348 /// Generate register pressure set for this register class and any class 349 /// synthesized from it. 350 bool GeneratePressureSet; 351 352 // Return the Record that defined this class, or NULL if the class was 353 // created by TableGen. 354 Record *getDef() const { return TheDef; } 355 356 const std::string &getName() const { return Name; } 357 std::string getQualifiedName() const; 358 ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; } 359 unsigned getNumValueTypes() const { return VTs.size(); } 360 bool hasType(const ValueTypeByHwMode &VT) const; 361 362 const ValueTypeByHwMode &getValueTypeNum(unsigned VTNum) const { 363 if (VTNum < VTs.size()) 364 return VTs[VTNum]; 365 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!"); 366 } 367 368 // Return true if this this class contains the register. 369 bool contains(const CodeGenRegister*) const; 370 371 // Returns true if RC is a subclass. 372 // RC is a sub-class of this class if it is a valid replacement for any 373 // instruction operand where a register of this classis required. It must 374 // satisfy these conditions: 375 // 376 // 1. All RC registers are also in this. 377 // 2. The RC spill size must not be smaller than our spill size. 378 // 3. RC spill alignment must be compatible with ours. 379 // 380 bool hasSubClass(const CodeGenRegisterClass *RC) const { 381 return SubClasses.test(RC->EnumValue); 382 } 383 384 // getSubClassWithSubReg - Returns the largest sub-class where all 385 // registers have a SubIdx sub-register. 386 CodeGenRegisterClass * 387 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { 388 return SubClassWithSubReg.lookup(SubIdx); 389 } 390 391 /// Find largest subclass where all registers have SubIdx subregisters in 392 /// SubRegClass and the largest subregister class that contains those 393 /// subregisters without (as far as possible) also containing additional registers. 394 /// 395 /// This can be used to find a suitable pair of classes for subregister copies. 396 /// \return std::pair<SubClass, SubRegClass> where SubClass is a SubClass is 397 /// a class where every register has SubIdx and SubRegClass is a class where 398 /// every register is covered by the SubIdx subregister of SubClass. 399 std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>> 400 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank, 401 const CodeGenSubRegIndex *SubIdx) const; 402 403 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, 404 CodeGenRegisterClass *SubRC) { 405 SubClassWithSubReg[SubIdx] = SubRC; 406 } 407 408 // getSuperRegClasses - Returns a bit vector of all register classes 409 // containing only SubIdx super-registers of this class. 410 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, 411 BitVector &Out) const; 412 413 // addSuperRegClass - Add a class containing only SubIdx super-registers. 414 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, 415 CodeGenRegisterClass *SuperRC) { 416 SuperRegClasses[SubIdx].insert(SuperRC); 417 } 418 419 // getSubClasses - Returns a constant BitVector of subclasses indexed by 420 // EnumValue. 421 // The SubClasses vector includes an entry for this class. 422 const BitVector &getSubClasses() const { return SubClasses; } 423 424 // getSuperClasses - Returns a list of super classes ordered by EnumValue. 425 // The array does not include an entry for this class. 426 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const { 427 return SuperClasses; 428 } 429 430 // Returns an ordered list of class members. 431 // The order of registers is the same as in the .td file. 432 // No = 0 is the default allocation order, No = 1 is the first alternative. 433 ArrayRef<Record*> getOrder(unsigned No = 0) const { 434 return Orders[No]; 435 } 436 437 // Return the total number of allocation orders available. 438 unsigned getNumOrders() const { return Orders.size(); } 439 440 // Get the set of registers. This set contains the same registers as 441 // getOrder(0). 442 const CodeGenRegister::Vec &getMembers() const { return Members; } 443 444 // Get a bit vector of TopoSigs present in this register class. 445 const BitVector &getTopoSigs() const { return TopoSigs; } 446 447 // Get a weight of this register class. 448 unsigned getWeight(const CodeGenRegBank&) const; 449 450 // Populate a unique sorted list of units from a register set. 451 void buildRegUnitSet(const CodeGenRegBank &RegBank, 452 std::vector<unsigned> &RegUnits) const; 453 454 CodeGenRegisterClass(CodeGenRegBank&, Record *R); 455 CodeGenRegisterClass(CodeGenRegisterClass&) = delete; 456 457 // A key representing the parts of a register class used for forming 458 // sub-classes. Note the ordering provided by this key is not the same as 459 // the topological order used for the EnumValues. 460 struct Key { 461 const CodeGenRegister::Vec *Members; 462 RegSizeInfoByHwMode RSI; 463 464 Key(const CodeGenRegister::Vec *M, const RegSizeInfoByHwMode &I) 465 : Members(M), RSI(I) {} 466 467 Key(const CodeGenRegisterClass &RC) 468 : Members(&RC.getMembers()), RSI(RC.RSI) {} 469 470 // Lexicographical order of (Members, RegSizeInfoByHwMode). 471 bool operator<(const Key&) const; 472 }; 473 474 // Create a non-user defined register class. 475 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props); 476 477 // Called by CodeGenRegBank::CodeGenRegBank(). 478 static void computeSubClasses(CodeGenRegBank&); 479 480 // Get ordering value among register base classes. 481 std::optional<int> getBaseClassOrder() const { 482 if (TheDef && !TheDef->isValueUnset("BaseClassOrder")) 483 return TheDef->getValueAsInt("BaseClassOrder"); 484 return {}; 485 } 486 }; 487 488 // Register categories are used when we need to deterine the category a 489 // register falls into (GPR, vector, fixed, etc.) without having to know 490 // specific information about the target architecture. 491 class CodeGenRegisterCategory { 492 Record *TheDef; 493 std::string Name; 494 std::list<CodeGenRegisterClass *> Classes; 495 496 public: 497 CodeGenRegisterCategory(CodeGenRegBank &, Record *R); 498 CodeGenRegisterCategory(CodeGenRegisterCategory &) = delete; 499 500 // Return the Record that defined this class, or NULL if the class was 501 // created by TableGen. 502 Record *getDef() const { return TheDef; } 503 504 std::string getName() const { return Name; } 505 std::list<CodeGenRegisterClass *> getClasses() const { return Classes; } 506 }; 507 508 // Register units are used to model interference and register pressure. 509 // Every register is assigned one or more register units such that two 510 // registers overlap if and only if they have a register unit in common. 511 // 512 // Normally, one register unit is created per leaf register. Non-leaf 513 // registers inherit the units of their sub-registers. 514 struct RegUnit { 515 // Weight assigned to this RegUnit for estimating register pressure. 516 // This is useful when equalizing weights in register classes with mixed 517 // register topologies. 518 unsigned Weight; 519 520 // Each native RegUnit corresponds to one or two root registers. The full 521 // set of registers containing this unit can be computed as the union of 522 // these two registers and their super-registers. 523 const CodeGenRegister *Roots[2]; 524 525 // Index into RegClassUnitSets where we can find the list of UnitSets that 526 // contain this unit. 527 unsigned RegClassUnitSetsIdx; 528 // A register unit is artificial if at least one of its roots is 529 // artificial. 530 bool Artificial; 531 532 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) { 533 Roots[0] = Roots[1] = nullptr; 534 } 535 536 ArrayRef<const CodeGenRegister*> getRoots() const { 537 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array"); 538 return ArrayRef(Roots, !!Roots[0] + !!Roots[1]); 539 } 540 }; 541 542 // Each RegUnitSet is a sorted vector with a name. 543 struct RegUnitSet { 544 typedef std::vector<unsigned>::const_iterator iterator; 545 546 std::string Name; 547 std::vector<unsigned> Units; 548 unsigned Weight = 0; // Cache the sum of all unit weights. 549 unsigned Order = 0; // Cache the sort key. 550 551 RegUnitSet() = default; 552 }; 553 554 // Base vector for identifying TopoSigs. The contents uniquely identify a 555 // TopoSig, only computeSuperRegs needs to know how. 556 typedef SmallVector<unsigned, 16> TopoSigId; 557 558 // CodeGenRegBank - Represent a target's registers and the relations between 559 // them. 560 class CodeGenRegBank { 561 SetTheory Sets; 562 563 const CodeGenHwModes &CGH; 564 565 std::deque<CodeGenSubRegIndex> SubRegIndices; 566 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx; 567 568 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace); 569 570 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>, 571 CodeGenSubRegIndex*> ConcatIdxMap; 572 ConcatIdxMap ConcatIdx; 573 574 // Registers. 575 std::deque<CodeGenRegister> Registers; 576 StringMap<CodeGenRegister*> RegistersByName; 577 DenseMap<Record*, CodeGenRegister*> Def2Reg; 578 unsigned NumNativeRegUnits; 579 580 std::map<TopoSigId, unsigned> TopoSigs; 581 582 // Includes native (0..NumNativeRegUnits-1) and adopted register units. 583 SmallVector<RegUnit, 8> RegUnits; 584 585 // Register classes. 586 std::list<CodeGenRegisterClass> RegClasses; 587 DenseMap<Record*, CodeGenRegisterClass*> Def2RC; 588 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap; 589 RCKeyMap Key2RC; 590 591 // Register categories. 592 std::list<CodeGenRegisterCategory> RegCategories; 593 DenseMap<Record *, CodeGenRegisterCategory *> Def2RCat; 594 using RCatKeyMap = 595 std::map<CodeGenRegisterClass::Key, CodeGenRegisterCategory *>; 596 RCatKeyMap Key2RCat; 597 598 // Remember each unique set of register units. Initially, this contains a 599 // unique set for each register class. Simliar sets are coalesced with 600 // pruneUnitSets and new supersets are inferred during computeRegUnitSets. 601 std::vector<RegUnitSet> RegUnitSets; 602 603 // Map RegisterClass index to the index of the RegUnitSet that contains the 604 // class's units and any inferred RegUnit supersets. 605 // 606 // NOTE: This could grow beyond the number of register classes when we map 607 // register units to lists of unit sets. If the list of unit sets does not 608 // already exist for a register class, we create a new entry in this vector. 609 std::vector<std::vector<unsigned>> RegClassUnitSets; 610 611 // Give each register unit set an order based on sorting criteria. 612 std::vector<unsigned> RegUnitSetOrder; 613 614 // Keep track of synthesized definitions generated in TupleExpander. 615 std::vector<std::unique_ptr<Record>> SynthDefs; 616 617 // Add RC to *2RC maps. 618 void addToMaps(CodeGenRegisterClass*); 619 620 // Create a synthetic sub-class if it is missing. 621 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC, 622 const CodeGenRegister::Vec *Membs, 623 StringRef Name); 624 625 // Infer missing register classes. 626 void computeInferredRegisterClasses(); 627 void inferCommonSubClass(CodeGenRegisterClass *RC); 628 void inferSubClassWithSubReg(CodeGenRegisterClass *RC); 629 630 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) { 631 inferMatchingSuperRegClass(RC, RegClasses.begin()); 632 } 633 634 void inferMatchingSuperRegClass( 635 CodeGenRegisterClass *RC, 636 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC); 637 638 // Iteratively prune unit sets. 639 void pruneUnitSets(); 640 641 // Compute a weight for each register unit created during getSubRegs. 642 void computeRegUnitWeights(); 643 644 // Create a RegUnitSet for each RegClass and infer superclasses. 645 void computeRegUnitSets(); 646 647 // Populate the Composite map from sub-register relationships. 648 void computeComposites(); 649 650 // Compute a lane mask for each sub-register index. 651 void computeSubRegLaneMasks(); 652 653 /// Computes a lane mask for each register unit enumerated by a physical 654 /// register. 655 void computeRegUnitLaneMasks(); 656 657 public: 658 CodeGenRegBank(RecordKeeper&, const CodeGenHwModes&); 659 CodeGenRegBank(CodeGenRegBank&) = delete; 660 661 SetTheory &getSets() { return Sets; } 662 663 const CodeGenHwModes &getHwModes() const { return CGH; } 664 665 // Sub-register indices. The first NumNamedIndices are defined by the user 666 // in the .td files. The rest are synthesized such that all sub-registers 667 // have a unique name. 668 const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const { 669 return SubRegIndices; 670 } 671 672 // Find a SubRegIndex from its Record def or add to the list if it does 673 // not exist there yet. 674 CodeGenSubRegIndex *getSubRegIdx(Record*); 675 676 // Find a SubRegIndex from its Record def. 677 const CodeGenSubRegIndex *findSubRegIdx(const Record* Def) const; 678 679 // Find or create a sub-register index representing the A+B composition. 680 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A, 681 CodeGenSubRegIndex *B); 682 683 // Find or create a sub-register index representing the concatenation of 684 // non-overlapping sibling indices. 685 CodeGenSubRegIndex * 686 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&); 687 688 const std::deque<CodeGenRegister> &getRegisters() const { 689 return Registers; 690 } 691 692 const StringMap<CodeGenRegister *> &getRegistersByName() const { 693 return RegistersByName; 694 } 695 696 // Find a register from its Record def. 697 CodeGenRegister *getReg(Record*); 698 699 // Get a Register's index into the Registers array. 700 unsigned getRegIndex(const CodeGenRegister *Reg) const { 701 return Reg->EnumValue - 1; 702 } 703 704 // Return the number of allocated TopoSigs. The first TopoSig representing 705 // leaf registers is allocated number 0. 706 unsigned getNumTopoSigs() const { 707 return TopoSigs.size(); 708 } 709 710 // Find or create a TopoSig for the given TopoSigId. 711 // This function is only for use by CodeGenRegister::computeSuperRegs(). 712 // Others should simply use Reg->getTopoSig(). 713 unsigned getTopoSig(const TopoSigId &Id) { 714 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second; 715 } 716 717 // Create a native register unit that is associated with one or two root 718 // registers. 719 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) { 720 RegUnits.resize(RegUnits.size() + 1); 721 RegUnit &RU = RegUnits.back(); 722 RU.Roots[0] = R0; 723 RU.Roots[1] = R1; 724 RU.Artificial = R0->Artificial; 725 if (R1) 726 RU.Artificial |= R1->Artificial; 727 return RegUnits.size() - 1; 728 } 729 730 // Create a new non-native register unit that can be adopted by a register 731 // to increase its pressure. Note that NumNativeRegUnits is not increased. 732 unsigned newRegUnit(unsigned Weight) { 733 RegUnits.resize(RegUnits.size() + 1); 734 RegUnits.back().Weight = Weight; 735 return RegUnits.size() - 1; 736 } 737 738 // Native units are the singular unit of a leaf register. Register aliasing 739 // is completely characterized by native units. Adopted units exist to give 740 // register additional weight but don't affect aliasing. 741 bool isNativeUnit(unsigned RUID) const { 742 return RUID < NumNativeRegUnits; 743 } 744 745 unsigned getNumNativeRegUnits() const { 746 return NumNativeRegUnits; 747 } 748 749 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } 750 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } 751 752 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } 753 754 const std::list<CodeGenRegisterClass> &getRegClasses() const { 755 return RegClasses; 756 } 757 758 std::list<CodeGenRegisterCategory> &getRegCategories() { 759 return RegCategories; 760 } 761 762 const std::list<CodeGenRegisterCategory> &getRegCategories() const { 763 return RegCategories; 764 } 765 766 // Find a register class from its def. 767 CodeGenRegisterClass *getRegClass(const Record *) const; 768 769 /// getRegisterClassForRegister - Find the register class that contains the 770 /// specified physical register. If the register is not in a register 771 /// class, return null. If the register is in multiple classes, and the 772 /// classes have a superset-subset relationship and the same set of types, 773 /// return the superclass. Otherwise return null. 774 const CodeGenRegisterClass* getRegClassForRegister(Record *R); 775 776 // Analog of TargetRegisterInfo::getMinimalPhysRegClass. Unlike 777 // getRegClassForRegister, this tries to find the smallest class containing 778 // the physical register. If \p VT is specified, it will only find classes 779 // with a matching type 780 const CodeGenRegisterClass * 781 getMinimalPhysRegClass(Record *RegRecord, ValueTypeByHwMode *VT = nullptr); 782 783 // Get the sum of unit weights. 784 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const { 785 unsigned Weight = 0; 786 for (unsigned Unit : Units) 787 Weight += getRegUnit(Unit).Weight; 788 return Weight; 789 } 790 791 unsigned getRegSetIDAt(unsigned Order) const { 792 return RegUnitSetOrder[Order]; 793 } 794 795 const RegUnitSet &getRegSetAt(unsigned Order) const { 796 return RegUnitSets[RegUnitSetOrder[Order]]; 797 } 798 799 // Increase a RegUnitWeight. 800 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) { 801 getRegUnit(RUID).Weight += Inc; 802 } 803 804 // Get the number of register pressure dimensions. 805 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); } 806 807 // Get a set of register unit IDs for a given dimension of pressure. 808 const RegUnitSet &getRegPressureSet(unsigned Idx) const { 809 return RegUnitSets[Idx]; 810 } 811 812 // The number of pressure set lists may be larget than the number of 813 // register classes if some register units appeared in a list of sets that 814 // did not correspond to an existing register class. 815 unsigned getNumRegClassPressureSetLists() const { 816 return RegClassUnitSets.size(); 817 } 818 819 // Get a list of pressure set IDs for a register class. Liveness of a 820 // register in this class impacts each pressure set in this list by the 821 // weight of the register. An exact solution requires all registers in a 822 // class to have the same class, but it is not strictly guaranteed. 823 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const { 824 return RegClassUnitSets[RCIdx]; 825 } 826 827 // Computed derived records such as missing sub-register indices. 828 void computeDerivedInfo(); 829 830 // Compute the set of registers completely covered by the registers in Regs. 831 // The returned BitVector will have a bit set for each register in Regs, 832 // all sub-registers, and all super-registers that are covered by the 833 // registers in Regs. 834 // 835 // This is used to compute the mask of call-preserved registers from a list 836 // of callee-saves. 837 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs); 838 839 // Bit mask of lanes that cover their registers. A sub-register index whose 840 // LaneMask is contained in CoveringLanes will be completely covered by 841 // another sub-register with the same or larger lane mask. 842 LaneBitmask CoveringLanes; 843 844 // Helper function for printing debug information. Handles artificial 845 // (non-native) reg units. 846 void printRegUnitName(unsigned Unit) const; 847 }; 848 849 } // end namespace llvm 850 851 #endif // LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H 852