1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This tablegen backend is responsible for emitting a description of a target 10 // register file for a code generator. It uses instances of the Register, 11 // RegisterAliases, and RegisterClass classes to gather this information. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "CodeGenRegisters.h" 16 #include "CodeGenTarget.h" 17 #include "SequenceToOffsetTable.h" 18 #include "Types.h" 19 #include "llvm/ADT/ArrayRef.h" 20 #include "llvm/ADT/BitVector.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/ADT/SetVector.h" 23 #include "llvm/ADT/SmallVector.h" 24 #include "llvm/ADT/SparseBitVector.h" 25 #include "llvm/ADT/Twine.h" 26 #include "llvm/Support/Casting.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/Format.h" 29 #include "llvm/Support/MachineValueType.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/TableGen/Error.h" 32 #include "llvm/TableGen/Record.h" 33 #include "llvm/TableGen/SetTheory.h" 34 #include "llvm/TableGen/TableGenBackend.h" 35 #include <algorithm> 36 #include <cassert> 37 #include <cstddef> 38 #include <cstdint> 39 #include <deque> 40 #include <iterator> 41 #include <set> 42 #include <string> 43 #include <vector> 44 45 using namespace llvm; 46 47 cl::OptionCategory RegisterInfoCat("Options for -gen-register-info"); 48 49 static cl::opt<bool> 50 RegisterInfoDebug("register-info-debug", cl::init(false), 51 cl::desc("Dump register information to help debugging"), 52 cl::cat(RegisterInfoCat)); 53 54 namespace { 55 56 class RegisterInfoEmitter { 57 CodeGenTarget Target; 58 RecordKeeper &Records; 59 60 public: 61 RegisterInfoEmitter(RecordKeeper &R) : Target(R), Records(R) { 62 CodeGenRegBank &RegBank = Target.getRegBank(); 63 RegBank.computeDerivedInfo(); 64 } 65 66 // runEnums - Print out enum values for all of the registers. 67 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 68 69 // runMCDesc - Print out MC register descriptions. 70 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 71 72 // runTargetHeader - Emit a header fragment for the register info emitter. 73 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 74 CodeGenRegBank &Bank); 75 76 // runTargetDesc - Output the target register and register file descriptions. 77 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 78 CodeGenRegBank &Bank); 79 80 // run - Output the register file description. 81 void run(raw_ostream &o); 82 83 void debugDump(raw_ostream &OS); 84 85 private: 86 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 87 bool isCtor); 88 void EmitRegMappingTables(raw_ostream &o, 89 const std::deque<CodeGenRegister> &Regs, 90 bool isCtor); 91 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 92 const std::string &ClassName); 93 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 94 const std::string &ClassName); 95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, 96 const std::string &ClassName); 97 }; 98 99 } // end anonymous namespace 100 101 // runEnums - Print out enum values for all of the registers. 102 void RegisterInfoEmitter::runEnums(raw_ostream &OS, 103 CodeGenTarget &Target, CodeGenRegBank &Bank) { 104 const auto &Registers = Bank.getRegisters(); 105 106 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 107 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 108 109 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 110 111 emitSourceFileHeader("Target Register Enum Values", OS); 112 113 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 114 OS << "#undef GET_REGINFO_ENUM\n\n"; 115 116 OS << "namespace llvm {\n\n"; 117 118 OS << "class MCRegisterClass;\n" 119 << "extern const MCRegisterClass " << Target.getName() 120 << "MCRegisterClasses[];\n\n"; 121 122 if (!Namespace.empty()) 123 OS << "namespace " << Namespace << " {\n"; 124 OS << "enum {\n NoRegister,\n"; 125 126 for (const auto &Reg : Registers) 127 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 128 assert(Registers.size() == Registers.back().EnumValue && 129 "Register enum value mismatch!"); 130 OS << " NUM_TARGET_REGS // " << Registers.size()+1 << "\n"; 131 OS << "};\n"; 132 if (!Namespace.empty()) 133 OS << "} // end namespace " << Namespace << "\n"; 134 135 const auto &RegisterClasses = Bank.getRegClasses(); 136 if (!RegisterClasses.empty()) { 137 138 // RegisterClass enums are stored as uint16_t in the tables. 139 assert(RegisterClasses.size() <= 0xffff && 140 "Too many register classes to fit in tables"); 141 142 OS << "\n// Register classes\n\n"; 143 if (!Namespace.empty()) 144 OS << "namespace " << Namespace << " {\n"; 145 OS << "enum {\n"; 146 for (const auto &RC : RegisterClasses) 147 OS << " " << RC.getName() << "RegClassID" 148 << " = " << RC.EnumValue << ",\n"; 149 OS << "\n};\n"; 150 if (!Namespace.empty()) 151 OS << "} // end namespace " << Namespace << "\n\n"; 152 } 153 154 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 155 // If the only definition is the default NoRegAltName, we don't need to 156 // emit anything. 157 if (RegAltNameIndices.size() > 1) { 158 OS << "\n// Register alternate name indices\n\n"; 159 if (!Namespace.empty()) 160 OS << "namespace " << Namespace << " {\n"; 161 OS << "enum {\n"; 162 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 163 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 164 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 165 OS << "};\n"; 166 if (!Namespace.empty()) 167 OS << "} // end namespace " << Namespace << "\n\n"; 168 } 169 170 auto &SubRegIndices = Bank.getSubRegIndices(); 171 if (!SubRegIndices.empty()) { 172 OS << "\n// Subregister indices\n\n"; 173 std::string Namespace = SubRegIndices.front().getNamespace(); 174 if (!Namespace.empty()) 175 OS << "namespace " << Namespace << " {\n"; 176 OS << "enum : uint16_t {\n NoSubRegister,\n"; 177 unsigned i = 0; 178 for (const auto &Idx : SubRegIndices) 179 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 180 OS << " NUM_TARGET_SUBREGS\n};\n"; 181 if (!Namespace.empty()) 182 OS << "} // end namespace " << Namespace << "\n\n"; 183 } 184 185 OS << "// Register pressure sets enum.\n"; 186 if (!Namespace.empty()) 187 OS << "namespace " << Namespace << " {\n"; 188 OS << "enum RegisterPressureSets {\n"; 189 unsigned NumSets = Bank.getNumRegPressureSets(); 190 for (unsigned i = 0; i < NumSets; ++i ) { 191 const RegUnitSet &RegUnits = Bank.getRegSetAt(i); 192 OS << " " << RegUnits.Name << " = " << i << ",\n"; 193 } 194 OS << "};\n"; 195 if (!Namespace.empty()) 196 OS << "} // end namespace " << Namespace << '\n'; 197 OS << '\n'; 198 199 OS << "} // end namespace llvm\n\n"; 200 OS << "#endif // GET_REGINFO_ENUM\n\n"; 201 } 202 203 static void printInt(raw_ostream &OS, int Val) { 204 OS << Val; 205 } 206 207 void RegisterInfoEmitter:: 208 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 209 const std::string &ClassName) { 210 unsigned NumRCs = RegBank.getRegClasses().size(); 211 unsigned NumSets = RegBank.getNumRegPressureSets(); 212 213 OS << "/// Get the weight in units of pressure for this register class.\n" 214 << "const RegClassWeight &" << ClassName << "::\n" 215 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 216 << " static const RegClassWeight RCWeightTable[] = {\n"; 217 for (const auto &RC : RegBank.getRegClasses()) { 218 const CodeGenRegister::Vec &Regs = RC.getMembers(); 219 OS << " {" << RC.getWeight(RegBank) << ", "; 220 if (Regs.empty() || RC.Artificial) 221 OS << '0'; 222 else { 223 std::vector<unsigned> RegUnits; 224 RC.buildRegUnitSet(RegBank, RegUnits); 225 OS << RegBank.getRegUnitSetWeight(RegUnits); 226 } 227 OS << "}, \t// " << RC.getName() << "\n"; 228 } 229 OS << " };\n" 230 << " return RCWeightTable[RC->getID()];\n" 231 << "}\n\n"; 232 233 // Reasonable targets (not ARMv7) have unit weight for all units, so don't 234 // bother generating a table. 235 bool RegUnitsHaveUnitWeight = true; 236 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 237 UnitIdx < UnitEnd; ++UnitIdx) { 238 if (RegBank.getRegUnit(UnitIdx).Weight > 1) 239 RegUnitsHaveUnitWeight = false; 240 } 241 OS << "/// Get the weight in units of pressure for this register unit.\n" 242 << "unsigned " << ClassName << "::\n" 243 << "getRegUnitWeight(unsigned RegUnit) const {\n" 244 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 245 << " && \"invalid register unit\");\n"; 246 if (!RegUnitsHaveUnitWeight) { 247 OS << " static const uint8_t RUWeightTable[] = {\n "; 248 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 249 UnitIdx < UnitEnd; ++UnitIdx) { 250 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 251 assert(RU.Weight < 256 && "RegUnit too heavy"); 252 OS << RU.Weight << ", "; 253 } 254 OS << "};\n" 255 << " return RUWeightTable[RegUnit];\n"; 256 } 257 else { 258 OS << " // All register units have unit weight.\n" 259 << " return 1;\n"; 260 } 261 OS << "}\n\n"; 262 263 OS << "\n" 264 << "// Get the number of dimensions of register pressure.\n" 265 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 266 << " return " << NumSets << ";\n}\n\n"; 267 268 OS << "// Get the name of this register unit pressure set.\n" 269 << "const char *" << ClassName << "::\n" 270 << "getRegPressureSetName(unsigned Idx) const {\n" 271 << " static const char *const PressureNameTable[] = {\n"; 272 unsigned MaxRegUnitWeight = 0; 273 for (unsigned i = 0; i < NumSets; ++i ) { 274 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 275 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 276 OS << " \"" << RegUnits.Name << "\",\n"; 277 } 278 OS << " };\n" 279 << " return PressureNameTable[Idx];\n" 280 << "}\n\n"; 281 282 OS << "// Get the register unit pressure limit for this dimension.\n" 283 << "// This limit must be adjusted dynamically for reserved registers.\n" 284 << "unsigned " << ClassName << "::\n" 285 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const " 286 "{\n" 287 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32) 288 << " PressureLimitTable[] = {\n"; 289 for (unsigned i = 0; i < NumSets; ++i ) { 290 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 291 OS << " " << RegUnits.Weight << ", \t// " << i << ": " 292 << RegUnits.Name << "\n"; 293 } 294 OS << " };\n" 295 << " return PressureLimitTable[Idx];\n" 296 << "}\n\n"; 297 298 SequenceToOffsetTable<std::vector<int>> PSetsSeqs; 299 300 // This table may be larger than NumRCs if some register units needed a list 301 // of unit sets that did not correspond to a register class. 302 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 303 std::vector<std::vector<int>> PSets(NumRCUnitSets); 304 305 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 306 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 307 PSets[i].reserve(PSetIDs.size()); 308 for (unsigned PSetID : PSetIDs) { 309 PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order); 310 } 311 llvm::sort(PSets[i]); 312 PSetsSeqs.add(PSets[i]); 313 } 314 315 PSetsSeqs.layout(); 316 317 OS << "/// Table of pressure sets per register class or unit.\n" 318 << "static const int RCSetsTable[] = {\n"; 319 PSetsSeqs.emit(OS, printInt, "-1"); 320 OS << "};\n\n"; 321 322 OS << "/// Get the dimensions of register pressure impacted by this " 323 << "register class.\n" 324 << "/// Returns a -1 terminated array of pressure set IDs\n" 325 << "const int *" << ClassName << "::\n" 326 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 327 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 328 << " RCSetStartTable[] = {\n "; 329 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 330 OS << PSetsSeqs.get(PSets[i]) << ","; 331 } 332 OS << "};\n" 333 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 334 << "}\n\n"; 335 336 OS << "/// Get the dimensions of register pressure impacted by this " 337 << "register unit.\n" 338 << "/// Returns a -1 terminated array of pressure set IDs\n" 339 << "const int *" << ClassName << "::\n" 340 << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 341 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 342 << " && \"invalid register unit\");\n"; 343 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 344 << " RUSetStartTable[] = {\n "; 345 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 346 UnitIdx < UnitEnd; ++UnitIdx) { 347 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 348 << ","; 349 } 350 OS << "};\n" 351 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 352 << "}\n\n"; 353 } 354 355 using DwarfRegNumsMapPair = std::pair<Record*, std::vector<int64_t>>; 356 using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>; 357 358 static void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) { 359 // Sort and unique to get a map-like vector. We want the last assignment to 360 // match previous behaviour. 361 llvm::stable_sort(DwarfRegNums, on_first<LessRecordRegister>()); 362 // Warn about duplicate assignments. 363 const Record *LastSeenReg = nullptr; 364 for (const auto &X : DwarfRegNums) { 365 const auto &Reg = X.first; 366 // The only way LessRecordRegister can return equal is if they're the same 367 // string. Use simple equality instead. 368 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) 369 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 370 getQualifiedName(Reg) + 371 "specified multiple times"); 372 LastSeenReg = Reg; 373 } 374 auto Last = std::unique( 375 DwarfRegNums.begin(), DwarfRegNums.end(), 376 [](const DwarfRegNumsMapPair &A, const DwarfRegNumsMapPair &B) { 377 return A.first->getName() == B.first->getName(); 378 }); 379 DwarfRegNums.erase(Last, DwarfRegNums.end()); 380 } 381 382 void RegisterInfoEmitter::EmitRegMappingTables( 383 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 384 // Collect all information about dwarf register numbers 385 DwarfRegNumsVecTy DwarfRegNums; 386 387 // First, just pull all provided information to the map 388 unsigned maxLength = 0; 389 for (auto &RE : Regs) { 390 Record *Reg = RE.TheDef; 391 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 392 maxLength = std::max((size_t)maxLength, RegNums.size()); 393 DwarfRegNums.emplace_back(Reg, std::move(RegNums)); 394 } 395 finalizeDwarfRegNumsKeys(DwarfRegNums); 396 397 if (!maxLength) 398 return; 399 400 // Now we know maximal length of number list. Append -1's, where needed 401 for (auto &DwarfRegNum : DwarfRegNums) 402 for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I) 403 DwarfRegNum.second.push_back(-1); 404 405 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 406 407 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 408 409 // Emit reverse information about the dwarf register numbers. 410 for (unsigned j = 0; j < 2; ++j) { 411 for (unsigned I = 0, E = maxLength; I != E; ++I) { 412 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 413 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 414 OS << I << "Dwarf2L[]"; 415 416 if (!isCtor) { 417 OS << " = {\n"; 418 419 // Store the mapping sorted by the LLVM reg num so lookup can be done 420 // with a binary search. 421 std::map<uint64_t, Record*> Dwarf2LMap; 422 for (auto &DwarfRegNum : DwarfRegNums) { 423 int DwarfRegNo = DwarfRegNum.second[I]; 424 if (DwarfRegNo < 0) 425 continue; 426 Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first; 427 } 428 429 for (auto &I : Dwarf2LMap) 430 OS << " { " << I.first << "U, " << getQualifiedName(I.second) 431 << " },\n"; 432 433 OS << "};\n"; 434 } else { 435 OS << ";\n"; 436 } 437 438 // We have to store the size in a const global, it's used in multiple 439 // places. 440 OS << "extern const unsigned " << Namespace 441 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize"; 442 if (!isCtor) 443 OS << " = array_lengthof(" << Namespace 444 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n"; 445 else 446 OS << ";\n\n"; 447 } 448 } 449 450 for (auto &RE : Regs) { 451 Record *Reg = RE.TheDef; 452 const RecordVal *V = Reg->getValue("DwarfAlias"); 453 if (!V || !V->getValue()) 454 continue; 455 456 DefInit *DI = cast<DefInit>(V->getValue()); 457 Record *Alias = DI->getDef(); 458 const auto &AliasIter = llvm::lower_bound( 459 DwarfRegNums, Alias, [](const DwarfRegNumsMapPair &A, const Record *B) { 460 return LessRecordRegister()(A.first, B); 461 }); 462 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias && 463 "Expected Alias to be present in map"); 464 const auto &RegIter = llvm::lower_bound( 465 DwarfRegNums, Reg, [](const DwarfRegNumsMapPair &A, const Record *B) { 466 return LessRecordRegister()(A.first, B); 467 }); 468 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg && 469 "Expected Reg to be present in map"); 470 RegIter->second = AliasIter->second; 471 } 472 473 // Emit information about the dwarf register numbers. 474 for (unsigned j = 0; j < 2; ++j) { 475 for (unsigned i = 0, e = maxLength; i != e; ++i) { 476 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 477 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 478 OS << i << "L2Dwarf[]"; 479 if (!isCtor) { 480 OS << " = {\n"; 481 // Store the mapping sorted by the Dwarf reg num so lookup can be done 482 // with a binary search. 483 for (auto &DwarfRegNum : DwarfRegNums) { 484 int RegNo = DwarfRegNum.second[i]; 485 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 486 continue; 487 488 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo 489 << "U },\n"; 490 } 491 OS << "};\n"; 492 } else { 493 OS << ";\n"; 494 } 495 496 // We have to store the size in a const global, it's used in multiple 497 // places. 498 OS << "extern const unsigned " << Namespace 499 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 500 if (!isCtor) 501 OS << " = array_lengthof(" << Namespace 502 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 503 else 504 OS << ";\n\n"; 505 } 506 } 507 } 508 509 void RegisterInfoEmitter::EmitRegMapping( 510 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 511 // Emit the initializer so the tables from EmitRegMappingTables get wired up 512 // to the MCRegisterInfo object. 513 unsigned maxLength = 0; 514 for (auto &RE : Regs) { 515 Record *Reg = RE.TheDef; 516 maxLength = std::max((size_t)maxLength, 517 Reg->getValueAsListOfInts("DwarfNumbers").size()); 518 } 519 520 if (!maxLength) 521 return; 522 523 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 524 525 // Emit reverse information about the dwarf register numbers. 526 for (unsigned j = 0; j < 2; ++j) { 527 OS << " switch ("; 528 if (j == 0) 529 OS << "DwarfFlavour"; 530 else 531 OS << "EHFlavour"; 532 OS << ") {\n" 533 << " default:\n" 534 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 535 536 for (unsigned i = 0, e = maxLength; i != e; ++i) { 537 OS << " case " << i << ":\n"; 538 OS << " "; 539 if (!isCtor) 540 OS << "RI->"; 541 std::string Tmp; 542 raw_string_ostream(Tmp) << Namespace 543 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 544 << "Dwarf2L"; 545 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 546 if (j == 0) 547 OS << "false"; 548 else 549 OS << "true"; 550 OS << ");\n"; 551 OS << " break;\n"; 552 } 553 OS << " }\n"; 554 } 555 556 // Emit information about the dwarf register numbers. 557 for (unsigned j = 0; j < 2; ++j) { 558 OS << " switch ("; 559 if (j == 0) 560 OS << "DwarfFlavour"; 561 else 562 OS << "EHFlavour"; 563 OS << ") {\n" 564 << " default:\n" 565 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 566 567 for (unsigned i = 0, e = maxLength; i != e; ++i) { 568 OS << " case " << i << ":\n"; 569 OS << " "; 570 if (!isCtor) 571 OS << "RI->"; 572 std::string Tmp; 573 raw_string_ostream(Tmp) << Namespace 574 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 575 << "L2Dwarf"; 576 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 577 if (j == 0) 578 OS << "false"; 579 else 580 OS << "true"; 581 OS << ");\n"; 582 OS << " break;\n"; 583 } 584 OS << " }\n"; 585 } 586 } 587 588 // Print a BitVector as a sequence of hex numbers using a little-endian mapping. 589 // Width is the number of bits per hex number. 590 static void printBitVectorAsHex(raw_ostream &OS, 591 const BitVector &Bits, 592 unsigned Width) { 593 assert(Width <= 32 && "Width too large"); 594 unsigned Digits = (Width + 3) / 4; 595 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 596 unsigned Value = 0; 597 for (unsigned j = 0; j != Width && i + j != e; ++j) 598 Value |= Bits.test(i + j) << j; 599 OS << format("0x%0*x, ", Digits, Value); 600 } 601 } 602 603 // Helper to emit a set of bits into a constant byte array. 604 class BitVectorEmitter { 605 BitVector Values; 606 public: 607 void add(unsigned v) { 608 if (v >= Values.size()) 609 Values.resize(((v/8)+1)*8); // Round up to the next byte. 610 Values[v] = true; 611 } 612 613 void print(raw_ostream &OS) { 614 printBitVectorAsHex(OS, Values, 8); 615 } 616 }; 617 618 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 619 OS << getEnumName(VT); 620 } 621 622 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 623 OS << Idx->EnumValue; 624 } 625 626 // Differentially encoded register and regunit lists allow for better 627 // compression on regular register banks. The sequence is computed from the 628 // differential list as: 629 // 630 // out[0] = InitVal; 631 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 632 // 633 // The initial value depends on the specific list. The list is terminated by a 634 // 0 differential which means we can't encode repeated elements. 635 636 typedef SmallVector<uint16_t, 4> DiffVec; 637 typedef SmallVector<LaneBitmask, 4> MaskVec; 638 639 // Differentially encode a sequence of numbers into V. The starting value and 640 // terminating 0 are not added to V, so it will have the same size as List. 641 static 642 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) { 643 assert(V.empty() && "Clear DiffVec before diffEncode."); 644 uint16_t Val = uint16_t(InitVal); 645 646 for (uint16_t Cur : List) { 647 V.push_back(Cur - Val); 648 Val = Cur; 649 } 650 return V; 651 } 652 653 template<typename Iter> 654 static 655 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 656 assert(V.empty() && "Clear DiffVec before diffEncode."); 657 uint16_t Val = uint16_t(InitVal); 658 for (Iter I = Begin; I != End; ++I) { 659 uint16_t Cur = (*I)->EnumValue; 660 V.push_back(Cur - Val); 661 Val = Cur; 662 } 663 return V; 664 } 665 666 static void printDiff16(raw_ostream &OS, uint16_t Val) { 667 OS << Val; 668 } 669 670 static void printMask(raw_ostream &OS, LaneBitmask Val) { 671 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; 672 } 673 674 // Try to combine Idx's compose map into Vec if it is compatible. 675 // Return false if it's not possible. 676 static bool combine(const CodeGenSubRegIndex *Idx, 677 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 678 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 679 for (const auto &I : Map) { 680 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 681 if (Entry && Entry != I.second) 682 return false; 683 } 684 685 // All entries are compatible. Make it so. 686 for (const auto &I : Map) { 687 auto *&Entry = Vec[I.first->EnumValue - 1]; 688 assert((!Entry || Entry == I.second) && 689 "Expected EnumValue to be unique"); 690 Entry = I.second; 691 } 692 return true; 693 } 694 695 void 696 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 697 CodeGenRegBank &RegBank, 698 const std::string &ClName) { 699 const auto &SubRegIndices = RegBank.getSubRegIndices(); 700 OS << "unsigned " << ClName 701 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 702 703 // Many sub-register indexes are composition-compatible, meaning that 704 // 705 // compose(IdxA, IdxB) == compose(IdxA', IdxB) 706 // 707 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 708 // The illegal entries can be use as wildcards to compress the table further. 709 710 // Map each Sub-register index to a compatible table row. 711 SmallVector<unsigned, 4> RowMap; 712 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 713 714 auto SubRegIndicesSize = 715 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 716 for (const auto &Idx : SubRegIndices) { 717 unsigned Found = ~0u; 718 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 719 if (combine(&Idx, Rows[r])) { 720 Found = r; 721 break; 722 } 723 } 724 if (Found == ~0u) { 725 Found = Rows.size(); 726 Rows.resize(Found + 1); 727 Rows.back().resize(SubRegIndicesSize); 728 combine(&Idx, Rows.back()); 729 } 730 RowMap.push_back(Found); 731 } 732 733 // Output the row map if there is multiple rows. 734 if (Rows.size() > 1) { 735 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) 736 << " RowMap[" << SubRegIndicesSize << "] = {\n "; 737 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 738 OS << RowMap[i] << ", "; 739 OS << "\n };\n"; 740 } 741 742 // Output the rows. 743 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 744 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 745 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 746 OS << " { "; 747 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 748 if (Rows[r][i]) 749 OS << Rows[r][i]->getQualifiedName() << ", "; 750 else 751 OS << "0, "; 752 OS << "},\n"; 753 } 754 OS << " };\n\n"; 755 756 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" 757 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 758 if (Rows.size() > 1) 759 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 760 else 761 OS << " return Rows[0][IdxB];\n"; 762 OS << "}\n\n"; 763 } 764 765 void 766 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 767 CodeGenRegBank &RegBank, 768 const std::string &ClName) { 769 // See the comments in computeSubRegLaneMasks() for our goal here. 770 const auto &SubRegIndices = RegBank.getSubRegIndices(); 771 772 // Create a list of Mask+Rotate operations, with equivalent entries merged. 773 SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 774 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 775 for (const auto &Idx : SubRegIndices) { 776 const SmallVector<MaskRolPair, 1> &IdxSequence 777 = Idx.CompositionLaneMaskTransform; 778 779 unsigned Found = ~0u; 780 unsigned SIdx = 0; 781 unsigned NextSIdx; 782 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 783 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 784 NextSIdx = SIdx + Sequence.size() + 1; 785 if (Sequence == IdxSequence) { 786 Found = SIdx; 787 break; 788 } 789 } 790 if (Found == ~0u) { 791 Sequences.push_back(IdxSequence); 792 Found = SIdx; 793 } 794 SubReg2SequenceIndexMap.push_back(Found); 795 } 796 797 OS << " struct MaskRolOp {\n" 798 " LaneBitmask Mask;\n" 799 " uint8_t RotateLeft;\n" 800 " };\n" 801 " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 802 unsigned Idx = 0; 803 for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 804 OS << " "; 805 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 806 for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) { 807 const MaskRolPair &P = Sequence[p]; 808 printMask(OS << "{ ", P.Mask); 809 OS << format(", %2u }, ", P.RotateLeft); 810 } 811 OS << "{ LaneBitmask::getNone(), 0 }"; 812 if (s+1 != se) 813 OS << ", "; 814 OS << " // Sequence " << Idx << "\n"; 815 Idx += Sequence.size() + 1; 816 } 817 OS << " };\n" 818 " static const MaskRolOp *const CompositeSequences[] = {\n"; 819 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 820 OS << " "; 821 unsigned Idx = SubReg2SequenceIndexMap[i]; 822 OS << format("&LaneMaskComposeSequences[%u]", Idx); 823 if (i+1 != e) 824 OS << ","; 825 OS << " // to " << SubRegIndices[i].getName() << "\n"; 826 } 827 OS << " };\n\n"; 828 829 OS << "LaneBitmask " << ClName 830 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 831 " const {\n" 832 " --IdxA; assert(IdxA < " << SubRegIndices.size() 833 << " && \"Subregister index out of bounds\");\n" 834 " LaneBitmask Result;\n" 835 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 836 " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n" 837 " if (unsigned S = Ops->RotateLeft)\n" 838 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n" 839 " else\n" 840 " Result |= LaneBitmask(M);\n" 841 " }\n" 842 " return Result;\n" 843 "}\n\n"; 844 845 OS << "LaneBitmask " << ClName 846 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 847 " LaneBitmask LaneMask) const {\n" 848 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 849 " --IdxA; assert(IdxA < " << SubRegIndices.size() 850 << " && \"Subregister index out of bounds\");\n" 851 " LaneBitmask Result;\n" 852 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 853 " LaneBitmask::Type M = LaneMask.getAsInteger();\n" 854 " if (unsigned S = Ops->RotateLeft)\n" 855 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n" 856 " else\n" 857 " Result |= LaneBitmask(M);\n" 858 " }\n" 859 " return Result;\n" 860 "}\n\n"; 861 } 862 863 // 864 // runMCDesc - Print out MC register descriptions. 865 // 866 void 867 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 868 CodeGenRegBank &RegBank) { 869 emitSourceFileHeader("MC Register Information", OS); 870 871 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 872 OS << "#undef GET_REGINFO_MC_DESC\n\n"; 873 874 const auto &Regs = RegBank.getRegisters(); 875 876 auto &SubRegIndices = RegBank.getSubRegIndices(); 877 // The lists of sub-registers and super-registers go in the same array. That 878 // allows us to share suffixes. 879 typedef std::vector<const CodeGenRegister*> RegVec; 880 881 // Differentially encoded lists. 882 SequenceToOffsetTable<DiffVec> DiffSeqs; 883 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 884 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 885 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 886 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 887 888 // List of lane masks accompanying register unit sequences. 889 SequenceToOffsetTable<MaskVec> LaneMaskSeqs; 890 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 891 892 // Keep track of sub-register names as well. These are not differentially 893 // encoded. 894 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 895 SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs; 896 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 897 898 SequenceToOffsetTable<std::string> RegStrings; 899 900 // Precompute register lists for the SequenceToOffsetTable. 901 unsigned i = 0; 902 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 903 const auto &Reg = *I; 904 RegStrings.add(std::string(Reg.getName())); 905 906 // Compute the ordered sub-register list. 907 SetVector<const CodeGenRegister*> SR; 908 Reg.addSubRegsPreOrder(SR, RegBank); 909 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 910 DiffSeqs.add(SubRegLists[i]); 911 912 // Compute the corresponding sub-register indexes. 913 SubRegIdxVec &SRIs = SubRegIdxLists[i]; 914 for (const CodeGenRegister *S : SR) 915 SRIs.push_back(Reg.getSubRegIndex(S)); 916 SubRegIdxSeqs.add(SRIs); 917 918 // Super-registers are already computed. 919 const RegVec &SuperRegList = Reg.getSuperRegs(); 920 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 921 SuperRegList.end()); 922 DiffSeqs.add(SuperRegLists[i]); 923 924 // Differentially encode the register unit list, seeded by register number. 925 // First compute a scale factor that allows more diff-lists to be reused: 926 // 927 // D0 -> (S0, S1) 928 // D1 -> (S2, S3) 929 // 930 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 931 // value for the differential decoder is the register number multiplied by 932 // the scale. 933 // 934 // Check the neighboring registers for arithmetic progressions. 935 unsigned ScaleA = ~0u, ScaleB = ~0u; 936 SparseBitVector<> RUs = Reg.getNativeRegUnits(); 937 if (I != Regs.begin() && 938 std::prev(I)->getNativeRegUnits().count() == RUs.count()) 939 ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin(); 940 if (std::next(I) != Regs.end() && 941 std::next(I)->getNativeRegUnits().count() == RUs.count()) 942 ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin(); 943 unsigned Scale = std::min(ScaleB, ScaleA); 944 // Default the scale to 0 if it can't be encoded in 4 bits. 945 if (Scale >= 16) 946 Scale = 0; 947 RegUnitInitScale[i] = Scale; 948 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); 949 950 const auto &RUMasks = Reg.getRegUnitLaneMasks(); 951 MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 952 assert(LaneMaskVec.empty()); 953 llvm::append_range(LaneMaskVec, RUMasks); 954 // Terminator mask should not be used inside of the list. 955 #ifndef NDEBUG 956 for (LaneBitmask M : LaneMaskVec) { 957 assert(!M.all() && "terminator mask should not be part of the list"); 958 } 959 #endif 960 LaneMaskSeqs.add(LaneMaskVec); 961 } 962 963 // Compute the final layout of the sequence table. 964 DiffSeqs.layout(); 965 LaneMaskSeqs.layout(); 966 SubRegIdxSeqs.layout(); 967 968 OS << "namespace llvm {\n\n"; 969 970 const std::string &TargetName = std::string(Target.getName()); 971 972 // Emit the shared table of differential lists. 973 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 974 DiffSeqs.emit(OS, printDiff16); 975 OS << "};\n\n"; 976 977 // Emit the shared table of regunit lane mask sequences. 978 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 979 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); 980 OS << "};\n\n"; 981 982 // Emit the table of sub-register indexes. 983 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 984 SubRegIdxSeqs.emit(OS, printSubRegIndex); 985 OS << "};\n\n"; 986 987 // Emit the table of sub-register index sizes. 988 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 989 << TargetName << "SubRegIdxRanges[] = {\n"; 990 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 991 for (const auto &Idx : SubRegIndices) { 992 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " 993 << Idx.getName() << "\n"; 994 } 995 OS << "};\n\n"; 996 997 // Emit the string table. 998 RegStrings.layout(); 999 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName + 1000 "RegStrings[]"); 1001 1002 OS << "extern const MCRegisterDesc " << TargetName 1003 << "RegDesc[] = { // Descriptors\n"; 1004 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 1005 1006 // Emit the register descriptors now. 1007 i = 0; 1008 for (const auto &Reg : Regs) { 1009 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " 1010 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 1011 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 1012 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " 1013 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n"; 1014 ++i; 1015 } 1016 OS << "};\n\n"; // End of register descriptors... 1017 1018 // Emit the table of register unit roots. Each regunit has one or two root 1019 // registers. 1020 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 1021 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 1022 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 1023 assert(!Roots.empty() && "All regunits must have a root register."); 1024 assert(Roots.size() <= 2 && "More than two roots not supported yet."); 1025 OS << " { "; 1026 ListSeparator LS; 1027 for (const CodeGenRegister *R : Roots) 1028 OS << LS << getQualifiedName(R->TheDef); 1029 OS << " },\n"; 1030 } 1031 OS << "};\n\n"; 1032 1033 const auto &RegisterClasses = RegBank.getRegClasses(); 1034 1035 // Loop over all of the register classes... emitting each one. 1036 OS << "namespace { // Register classes...\n"; 1037 1038 SequenceToOffsetTable<std::string> RegClassStrings; 1039 1040 // Emit the register enum value arrays for each RegisterClass 1041 for (const auto &RC : RegisterClasses) { 1042 ArrayRef<Record*> Order = RC.getOrder(); 1043 1044 // Give the register class a legal C name if it's anonymous. 1045 const std::string &Name = RC.getName(); 1046 1047 RegClassStrings.add(Name); 1048 1049 // Emit the register list now. 1050 OS << " // " << Name << " Register Class...\n" 1051 << " const MCPhysReg " << Name 1052 << "[] = {\n "; 1053 for (Record *Reg : Order) { 1054 OS << getQualifiedName(Reg) << ", "; 1055 } 1056 OS << "\n };\n\n"; 1057 1058 OS << " // " << Name << " Bit set.\n" 1059 << " const uint8_t " << Name 1060 << "Bits[] = {\n "; 1061 BitVectorEmitter BVE; 1062 for (Record *Reg : Order) { 1063 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 1064 } 1065 BVE.print(OS); 1066 OS << "\n };\n\n"; 1067 1068 } 1069 OS << "} // end anonymous namespace\n\n"; 1070 1071 RegClassStrings.layout(); 1072 RegClassStrings.emitStringLiteralDef( 1073 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]"); 1074 1075 OS << "extern const MCRegisterClass " << TargetName 1076 << "MCRegisterClasses[] = {\n"; 1077 1078 for (const auto &RC : RegisterClasses) { 1079 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); 1080 uint32_t RegSize = 0; 1081 if (RC.RSI.isSimple()) 1082 RegSize = RC.RSI.getSimple().RegSize; 1083 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " 1084 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() 1085 << ", sizeof(" << RC.getName() << "Bits), " 1086 << RC.getQualifiedName() + "RegClassID" 1087 << ", " << RegSize << ", " << RC.CopyCost << ", " 1088 << (RC.Allocatable ? "true" : "false") << " },\n"; 1089 } 1090 1091 OS << "};\n\n"; 1092 1093 EmitRegMappingTables(OS, Regs, false); 1094 1095 // Emit Reg encoding table 1096 OS << "extern const uint16_t " << TargetName; 1097 OS << "RegEncodingTable[] = {\n"; 1098 // Add entry for NoRegister 1099 OS << " 0,\n"; 1100 for (const auto &RE : Regs) { 1101 Record *Reg = RE.TheDef; 1102 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1103 uint64_t Value = 0; 1104 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1105 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1106 Value |= (uint64_t)B->getValue() << b; 1107 } 1108 OS << " " << Value << ",\n"; 1109 } 1110 OS << "};\n"; // End of HW encoding table 1111 1112 // MCRegisterInfo initialization routine. 1113 OS << "static inline void Init" << TargetName 1114 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1115 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1116 "{\n" 1117 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1118 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1119 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1120 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1121 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1122 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1123 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1124 << TargetName << "SubRegIdxRanges, " << TargetName 1125 << "RegEncodingTable);\n\n"; 1126 1127 EmitRegMapping(OS, Regs, false); 1128 1129 OS << "}\n\n"; 1130 1131 OS << "} // end namespace llvm\n\n"; 1132 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1133 } 1134 1135 void 1136 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 1137 CodeGenRegBank &RegBank) { 1138 emitSourceFileHeader("Register Information Header Fragment", OS); 1139 1140 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1141 OS << "#undef GET_REGINFO_HEADER\n\n"; 1142 1143 const std::string &TargetName = std::string(Target.getName()); 1144 std::string ClassName = TargetName + "GenRegisterInfo"; 1145 1146 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; 1147 1148 OS << "namespace llvm {\n\n"; 1149 1150 OS << "class " << TargetName << "FrameLowering;\n\n"; 1151 1152 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1153 << " explicit " << ClassName 1154 << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n" 1155 << " unsigned PC = 0, unsigned HwMode = 0);\n"; 1156 if (!RegBank.getSubRegIndices().empty()) { 1157 OS << " unsigned composeSubRegIndicesImpl" 1158 << "(unsigned, unsigned) const override;\n" 1159 << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1160 << "(unsigned, LaneBitmask) const override;\n" 1161 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1162 << "(unsigned, LaneBitmask) const override;\n" 1163 << " const TargetRegisterClass *getSubClassWithSubReg" 1164 << "(const TargetRegisterClass *, unsigned) const override;\n"; 1165 } 1166 OS << " const RegClassWeight &getRegClassWeight(" 1167 << "const TargetRegisterClass *RC) const override;\n" 1168 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1169 << " unsigned getNumRegPressureSets() const override;\n" 1170 << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1171 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1172 "Idx) const override;\n" 1173 << " const int *getRegClassPressureSets(" 1174 << "const TargetRegisterClass *RC) const override;\n" 1175 << " const int *getRegUnitPressureSets(" 1176 << "unsigned RegUnit) const override;\n" 1177 << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1178 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1179 << " /// Devirtualized TargetFrameLowering.\n" 1180 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1181 << " const MachineFunction &MF);\n" 1182 << "};\n\n"; 1183 1184 const auto &RegisterClasses = RegBank.getRegClasses(); 1185 1186 if (!RegisterClasses.empty()) { 1187 OS << "namespace " << RegisterClasses.front().Namespace 1188 << " { // Register classes\n"; 1189 1190 for (const auto &RC : RegisterClasses) { 1191 const std::string &Name = RC.getName(); 1192 1193 // Output the extern for the instance. 1194 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1195 } 1196 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1197 } 1198 OS << "} // end namespace llvm\n\n"; 1199 OS << "#endif // GET_REGINFO_HEADER\n\n"; 1200 } 1201 1202 // 1203 // runTargetDesc - Output the target register and register file descriptions. 1204 // 1205 void 1206 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1207 CodeGenRegBank &RegBank){ 1208 emitSourceFileHeader("Target Register and Register Classes Information", OS); 1209 1210 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1211 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1212 1213 OS << "namespace llvm {\n\n"; 1214 1215 // Get access to MCRegisterClass data. 1216 OS << "extern const MCRegisterClass " << Target.getName() 1217 << "MCRegisterClasses[];\n"; 1218 1219 // Start out by emitting each of the register classes. 1220 const auto &RegisterClasses = RegBank.getRegClasses(); 1221 const auto &SubRegIndices = RegBank.getSubRegIndices(); 1222 1223 // Collect all registers belonging to any allocatable class. 1224 std::set<Record*> AllocatableRegs; 1225 1226 // Collect allocatable registers. 1227 for (const auto &RC : RegisterClasses) { 1228 ArrayRef<Record*> Order = RC.getOrder(); 1229 1230 if (RC.Allocatable) 1231 AllocatableRegs.insert(Order.begin(), Order.end()); 1232 } 1233 1234 const CodeGenHwModes &CGH = Target.getHwModes(); 1235 unsigned NumModes = CGH.getNumModeIds(); 1236 1237 // Build a shared array of value types. 1238 SequenceToOffsetTable<std::vector<MVT::SimpleValueType>> VTSeqs; 1239 for (unsigned M = 0; M < NumModes; ++M) { 1240 for (const auto &RC : RegisterClasses) { 1241 std::vector<MVT::SimpleValueType> S; 1242 for (const ValueTypeByHwMode &VVT : RC.VTs) 1243 S.push_back(VVT.get(M).SimpleTy); 1244 VTSeqs.add(S); 1245 } 1246 } 1247 VTSeqs.layout(); 1248 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1249 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1250 OS << "};\n"; 1251 1252 // Emit SubRegIndex names, skipping 0. 1253 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1254 1255 for (const auto &Idx : SubRegIndices) { 1256 OS << Idx.getName(); 1257 OS << "\", \""; 1258 } 1259 OS << "\" };\n\n"; 1260 1261 // Emit SubRegIndex lane masks, including 0. 1262 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1263 "LaneBitmask::getAll(),\n"; 1264 for (const auto &Idx : SubRegIndices) { 1265 printMask(OS << " ", Idx.LaneMask); 1266 OS << ", // " << Idx.getName() << '\n'; 1267 } 1268 OS << " };\n\n"; 1269 1270 OS << "\n"; 1271 1272 // Now that all of the structs have been emitted, emit the instances. 1273 if (!RegisterClasses.empty()) { 1274 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1275 << " = {\n"; 1276 for (unsigned M = 0; M < NumModes; ++M) { 1277 unsigned EV = 0; 1278 OS << " // Mode = " << M << " ("; 1279 if (M == 0) 1280 OS << "Default"; 1281 else 1282 OS << CGH.getMode(M).Name; 1283 OS << ")\n"; 1284 for (const auto &RC : RegisterClasses) { 1285 assert(RC.EnumValue == EV && "Unexpected order of register classes"); 1286 ++EV; 1287 (void)EV; 1288 const RegSizeInfo &RI = RC.RSI.get(M); 1289 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1290 << RI.SpillAlignment; 1291 std::vector<MVT::SimpleValueType> VTs; 1292 for (const ValueTypeByHwMode &VVT : RC.VTs) 1293 VTs.push_back(VVT.get(M).SimpleTy); 1294 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " 1295 << RC.getName() << '\n'; 1296 } 1297 } 1298 OS << "};\n"; 1299 1300 1301 OS << "\nstatic const TargetRegisterClass *const " 1302 << "NullRegClasses[] = { nullptr };\n\n"; 1303 1304 // Emit register class bit mask tables. The first bit mask emitted for a 1305 // register class, RC, is the set of sub-classes, including RC itself. 1306 // 1307 // If RC has super-registers, also create a list of subreg indices and bit 1308 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1309 // SuperRC, that satisfies: 1310 // 1311 // For all SuperReg in SuperRC: SuperReg:Idx in RC 1312 // 1313 // The 0-terminated list of subreg indices starts at: 1314 // 1315 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1316 // 1317 // The corresponding bitmasks follow the sub-class mask in memory. Each 1318 // mask has RCMaskWords uint32_t entries. 1319 // 1320 // Every bit mask present in the list has at least one bit set. 1321 1322 // Compress the sub-reg index lists. 1323 typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1324 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1325 SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs; 1326 BitVector MaskBV(RegisterClasses.size()); 1327 1328 for (const auto &RC : RegisterClasses) { 1329 OS << "static const uint32_t " << RC.getName() 1330 << "SubClassMask[] = {\n "; 1331 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1332 1333 // Emit super-reg class masks for any relevant SubRegIndices that can 1334 // project into RC. 1335 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1336 for (auto &Idx : SubRegIndices) { 1337 MaskBV.reset(); 1338 RC.getSuperRegClasses(&Idx, MaskBV); 1339 if (MaskBV.none()) 1340 continue; 1341 SRIList.push_back(&Idx); 1342 OS << "\n "; 1343 printBitVectorAsHex(OS, MaskBV, 32); 1344 OS << "// " << Idx.getName(); 1345 } 1346 SuperRegIdxSeqs.add(SRIList); 1347 OS << "\n};\n\n"; 1348 } 1349 1350 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1351 SuperRegIdxSeqs.layout(); 1352 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1353 OS << "};\n\n"; 1354 1355 // Emit NULL terminated super-class lists. 1356 for (const auto &RC : RegisterClasses) { 1357 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1358 1359 // Skip classes without supers. We can reuse NullRegClasses. 1360 if (Supers.empty()) 1361 continue; 1362 1363 OS << "static const TargetRegisterClass *const " 1364 << RC.getName() << "Superclasses[] = {\n"; 1365 for (const auto *Super : Supers) 1366 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; 1367 OS << " nullptr\n};\n\n"; 1368 } 1369 1370 // Emit methods. 1371 for (const auto &RC : RegisterClasses) { 1372 if (!RC.AltOrderSelect.empty()) { 1373 OS << "\nstatic inline unsigned " << RC.getName() 1374 << "AltOrderSelect(const MachineFunction &MF) {" 1375 << RC.AltOrderSelect << "}\n\n" 1376 << "static ArrayRef<MCPhysReg> " << RC.getName() 1377 << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1378 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1379 ArrayRef<Record*> Elems = RC.getOrder(oi); 1380 if (!Elems.empty()) { 1381 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1382 for (unsigned elem = 0; elem != Elems.size(); ++elem) 1383 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1384 OS << " };\n"; 1385 } 1386 } 1387 OS << " const MCRegisterClass &MCR = " << Target.getName() 1388 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1389 << " const ArrayRef<MCPhysReg> Order[] = {\n" 1390 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1391 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1392 if (RC.getOrder(oi).empty()) 1393 OS << "),\n ArrayRef<MCPhysReg>("; 1394 else 1395 OS << "),\n makeArrayRef(AltOrder" << oi; 1396 OS << ")\n };\n const unsigned Select = " << RC.getName() 1397 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1398 << ");\n return Order[Select];\n}\n"; 1399 } 1400 } 1401 1402 // Now emit the actual value-initialized register class instances. 1403 OS << "\nnamespace " << RegisterClasses.front().Namespace 1404 << " { // Register class instances\n"; 1405 1406 for (const auto &RC : RegisterClasses) { 1407 OS << " extern const TargetRegisterClass " << RC.getName() 1408 << "RegClass = {\n " << '&' << Target.getName() 1409 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1410 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1411 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; 1412 printMask(OS, RC.LaneMask); 1413 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1414 << (RC.HasDisjunctSubRegs?"true":"false") 1415 << ", /* HasDisjunctSubRegs */\n " 1416 << (RC.CoveredBySubRegs?"true":"false") 1417 << ", /* CoveredBySubRegs */\n "; 1418 if (RC.getSuperClasses().empty()) 1419 OS << "NullRegClasses,\n "; 1420 else 1421 OS << RC.getName() << "Superclasses,\n "; 1422 if (RC.AltOrderSelect.empty()) 1423 OS << "nullptr\n"; 1424 else 1425 OS << RC.getName() << "GetRawAllocationOrder\n"; 1426 OS << " };\n\n"; 1427 } 1428 1429 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1430 } 1431 1432 OS << "\nnamespace {\n"; 1433 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; 1434 for (const auto &RC : RegisterClasses) 1435 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1436 OS << " };\n"; 1437 OS << "} // end anonymous namespace\n"; 1438 1439 // Emit extra information about registers. 1440 const std::string &TargetName = std::string(Target.getName()); 1441 const auto &Regs = RegBank.getRegisters(); 1442 unsigned NumRegCosts = 1; 1443 for (const auto &Reg : Regs) 1444 NumRegCosts = std::max((size_t)NumRegCosts, Reg.CostPerUse.size()); 1445 1446 std::vector<unsigned> AllRegCostPerUse; 1447 llvm::BitVector InAllocClass(Regs.size() + 1, false); 1448 AllRegCostPerUse.insert(AllRegCostPerUse.end(), NumRegCosts, 0); 1449 1450 // Populate the vector RegCosts with the CostPerUse list of the registers 1451 // in the order they are read. Have at most NumRegCosts entries for 1452 // each register. Fill with zero for values which are not explicitly given. 1453 for (const auto &Reg : Regs) { 1454 auto Costs = Reg.CostPerUse; 1455 AllRegCostPerUse.insert(AllRegCostPerUse.end(), Costs.begin(), Costs.end()); 1456 if (NumRegCosts > Costs.size()) 1457 AllRegCostPerUse.insert(AllRegCostPerUse.end(), 1458 NumRegCosts - Costs.size(), 0); 1459 1460 if (AllocatableRegs.count(Reg.TheDef)) 1461 InAllocClass.set(Reg.EnumValue); 1462 } 1463 1464 // Emit the cost values as a 1D-array after grouping them by their indices, 1465 // i.e. the costs for all registers corresponds to index 0, 1, 2, etc. 1466 // Size of the emitted array should be NumRegCosts * (Regs.size() + 1). 1467 OS << "\nstatic const uint8_t " 1468 << "CostPerUseTable[] = { \n"; 1469 for (unsigned int I = 0; I < NumRegCosts; ++I) { 1470 for (unsigned J = I, E = AllRegCostPerUse.size(); J < E; J += NumRegCosts) 1471 OS << AllRegCostPerUse[J] << ", "; 1472 } 1473 OS << "};\n\n"; 1474 1475 OS << "\nstatic const bool " 1476 << "InAllocatableClassTable[] = { \n"; 1477 for (unsigned I = 0, E = InAllocClass.size(); I < E; ++I) { 1478 OS << (InAllocClass[I] ? "true" : "false") << ", "; 1479 } 1480 OS << "};\n\n"; 1481 1482 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName 1483 << "RegInfoDesc = { // Extra Descriptors\n"; 1484 OS << "CostPerUseTable, " << NumRegCosts << ", " 1485 << "InAllocatableClassTable"; 1486 OS << "};\n\n"; // End of register descriptors... 1487 1488 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; 1489 1490 auto SubRegIndicesSize = 1491 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1492 1493 if (!SubRegIndices.empty()) { 1494 emitComposeSubRegIndices(OS, RegBank, ClassName); 1495 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); 1496 } 1497 1498 // Emit getSubClassWithSubReg. 1499 if (!SubRegIndices.empty()) { 1500 OS << "const TargetRegisterClass *" << ClassName 1501 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1502 << " const {\n"; 1503 // Use the smallest type that can hold a regclass ID with room for a 1504 // sentinel. 1505 if (RegisterClasses.size() < UINT8_MAX) 1506 OS << " static const uint8_t Table["; 1507 else if (RegisterClasses.size() < UINT16_MAX) 1508 OS << " static const uint16_t Table["; 1509 else 1510 PrintFatalError("Too many register classes."); 1511 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1512 for (const auto &RC : RegisterClasses) { 1513 OS << " {\t// " << RC.getName() << "\n"; 1514 for (auto &Idx : SubRegIndices) { 1515 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1516 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1517 << " -> " << SRC->getName() << "\n"; 1518 else 1519 OS << " 0,\t// " << Idx.getName() << "\n"; 1520 } 1521 OS << " },\n"; 1522 } 1523 OS << " };\n assert(RC && \"Missing regclass\");\n" 1524 << " if (!Idx) return RC;\n --Idx;\n" 1525 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1526 << " unsigned TV = Table[RC->getID()][Idx];\n" 1527 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1528 } 1529 1530 EmitRegUnitPressure(OS, RegBank, ClassName); 1531 1532 // Emit the constructor of the class... 1533 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1534 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1535 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1536 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1537 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1538 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1539 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1540 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1541 << TargetName << "SubRegIdxRanges[];\n"; 1542 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1543 1544 EmitRegMappingTables(OS, Regs, true); 1545 1546 OS << ClassName << "::\n" 1547 << ClassName 1548 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n" 1549 " unsigned PC, unsigned HwMode)\n" 1550 << " : TargetRegisterInfo(&" << TargetName << "RegInfoDesc" 1551 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n" 1552 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable,\n" 1553 << " "; 1554 printMask(OS, RegBank.CoveringLanes); 1555 OS << ", RegClassInfos, HwMode) {\n" 1556 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1557 << ", RA, PC,\n " << TargetName 1558 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1559 << " " << TargetName << "RegUnitRoots,\n" 1560 << " " << RegBank.getNumNativeRegUnits() << ",\n" 1561 << " " << TargetName << "RegDiffLists,\n" 1562 << " " << TargetName << "LaneMaskLists,\n" 1563 << " " << TargetName << "RegStrings,\n" 1564 << " " << TargetName << "RegClassStrings,\n" 1565 << " " << TargetName << "SubRegIdxLists,\n" 1566 << " " << SubRegIndicesSize + 1 << ",\n" 1567 << " " << TargetName << "SubRegIdxRanges,\n" 1568 << " " << TargetName << "RegEncodingTable);\n\n"; 1569 1570 EmitRegMapping(OS, Regs, true); 1571 1572 OS << "}\n\n"; 1573 1574 // Emit CalleeSavedRegs information. 1575 std::vector<Record*> CSRSets = 1576 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1577 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1578 Record *CSRSet = CSRSets[i]; 1579 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1580 assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1581 1582 // Emit the *_SaveList list of callee-saved registers. 1583 OS << "static const MCPhysReg " << CSRSet->getName() 1584 << "_SaveList[] = { "; 1585 for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1586 OS << getQualifiedName((*Regs)[r]) << ", "; 1587 OS << "0 };\n"; 1588 1589 // Emit the *_RegMask bit mask of call-preserved registers. 1590 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1591 1592 // Check for an optional OtherPreserved set. 1593 // Add those registers to RegMask, but not to SaveList. 1594 if (DagInit *OPDag = 1595 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1596 SetTheory::RecSet OPSet; 1597 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1598 Covered |= RegBank.computeCoveredRegisters( 1599 ArrayRef<Record*>(OPSet.begin(), OPSet.end())); 1600 } 1601 1602 OS << "static const uint32_t " << CSRSet->getName() 1603 << "_RegMask[] = { "; 1604 printBitVectorAsHex(OS, Covered, 32); 1605 OS << "};\n"; 1606 } 1607 OS << "\n\n"; 1608 1609 OS << "ArrayRef<const uint32_t *> " << ClassName 1610 << "::getRegMasks() const {\n"; 1611 if (!CSRSets.empty()) { 1612 OS << " static const uint32_t *const Masks[] = {\n"; 1613 for (Record *CSRSet : CSRSets) 1614 OS << " " << CSRSet->getName() << "_RegMask,\n"; 1615 OS << " };\n"; 1616 OS << " return makeArrayRef(Masks);\n"; 1617 } else { 1618 OS << " return None;\n"; 1619 } 1620 OS << "}\n\n"; 1621 1622 OS << "ArrayRef<const char *> " << ClassName 1623 << "::getRegMaskNames() const {\n"; 1624 if (!CSRSets.empty()) { 1625 OS << " static const char *const Names[] = {\n"; 1626 for (Record *CSRSet : CSRSets) 1627 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1628 OS << " };\n"; 1629 OS << " return makeArrayRef(Names);\n"; 1630 } else { 1631 OS << " return None;\n"; 1632 } 1633 OS << "}\n\n"; 1634 1635 OS << "const " << TargetName << "FrameLowering *\n" << TargetName 1636 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1637 << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1638 << " MF.getSubtarget().getFrameLowering());\n" 1639 << "}\n\n"; 1640 1641 OS << "} // end namespace llvm\n\n"; 1642 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1643 } 1644 1645 void RegisterInfoEmitter::run(raw_ostream &OS) { 1646 CodeGenRegBank &RegBank = Target.getRegBank(); 1647 Records.startTimer("Print enums"); 1648 runEnums(OS, Target, RegBank); 1649 1650 Records.startTimer("Print MC registers"); 1651 runMCDesc(OS, Target, RegBank); 1652 1653 Records.startTimer("Print header fragment"); 1654 runTargetHeader(OS, Target, RegBank); 1655 1656 Records.startTimer("Print target registers"); 1657 runTargetDesc(OS, Target, RegBank); 1658 1659 if (RegisterInfoDebug) 1660 debugDump(errs()); 1661 } 1662 1663 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { 1664 CodeGenRegBank &RegBank = Target.getRegBank(); 1665 const CodeGenHwModes &CGH = Target.getHwModes(); 1666 unsigned NumModes = CGH.getNumModeIds(); 1667 auto getModeName = [CGH] (unsigned M) -> StringRef { 1668 if (M == 0) 1669 return "Default"; 1670 return CGH.getMode(M).Name; 1671 }; 1672 1673 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { 1674 OS << "RegisterClass " << RC.getName() << ":\n"; 1675 OS << "\tSpillSize: {"; 1676 for (unsigned M = 0; M != NumModes; ++M) 1677 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; 1678 OS << " }\n\tSpillAlignment: {"; 1679 for (unsigned M = 0; M != NumModes; ++M) 1680 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; 1681 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; 1682 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; 1683 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; 1684 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; 1685 OS << "\tRegs:"; 1686 for (const CodeGenRegister *R : RC.getMembers()) { 1687 OS << " " << R->getName(); 1688 } 1689 OS << '\n'; 1690 OS << "\tSubClasses:"; 1691 const BitVector &SubClasses = RC.getSubClasses(); 1692 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { 1693 if (!SubClasses.test(SRC.EnumValue)) 1694 continue; 1695 OS << " " << SRC.getName(); 1696 } 1697 OS << '\n'; 1698 OS << "\tSuperClasses:"; 1699 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { 1700 OS << " " << SRC->getName(); 1701 } 1702 OS << '\n'; 1703 } 1704 1705 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { 1706 OS << "SubRegIndex " << SRI.getName() << ":\n"; 1707 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; 1708 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; 1709 } 1710 1711 for (const CodeGenRegister &R : RegBank.getRegisters()) { 1712 OS << "Register " << R.getName() << ":\n"; 1713 OS << "\tCostPerUse: "; 1714 for (const auto &Cost : R.CostPerUse) 1715 OS << Cost << " "; 1716 OS << '\n'; 1717 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; 1718 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; 1719 for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { 1720 OS << "\tSubReg " << P.first->getName() 1721 << " = " << P.second->getName() << '\n'; 1722 } 1723 } 1724 } 1725 1726 namespace llvm { 1727 1728 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1729 RegisterInfoEmitter(RK).run(OS); 1730 } 1731 1732 } // end namespace llvm 1733