1.\" Copyright (c) 2022 Ampere Computing. 2.\" 3.\" Redistribution and use in source and binary forms, with or without 4.\" modification, are permitted provided that the following conditions 5.\" are met: 6.\" 1. Redistributions of source code must retain the above copyright 7.\" notice, this list of conditions and the following disclaimer. 8.\" 2. Redistributions in binary form must reproduce the above copyright 9.\" notice, this list of conditions and the following disclaimer in the 10.\" documentation and/or other materials provided with the distribution. 11.\" 12.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 13.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 16.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22.\" SUCH DAMAGE. 23.\" 24.Dd Jul 22, 2022 25.Dt PMC.DMC-620 3 26.Os 27.Sh NAME 28.Nm pmc.dmc-620 29.Nd measure the 30.Tn Arm 31.Tn DMC-620 32Dynamic Memory Controller performance counter events. 33.Sh LIBRARY 34.Lb libpmc 35.Sh SYNOPSIS 36.In pmc.h 37.Sh DESCRIPTION 38.Tn DMC-620 39PMU counters may be configured to count any one of a defined set of hardware 40events. 41.Pp 42.Tn Arm 43.Tn CoreLink 44.Tn DMC-620 Dynamic Memory Controller performance counters are documented in 45.Rs 46.%B "ARM CoreLink DMC-620 Dynamic Memory Controller Technical Reference Manual" 47.%T "Revision: r0p0" 48.%D 2017 49.%Q "ARM Limited" 50.Re 51.Ss PMC Capabilities 52.Tn DMC-620 53PMU counters support the following capabilities: 54.Bl -column "PMC_CAP_INTERRUPT" "Support" 55.It Sy Capability Ta Em Support 56.It PMC_CAP_CASCADE Ta \&No 57.It PMC_CAP_EDGE Ta \&No 58.It PMC_CAP_INTERRUPT Ta Yes 59.It PMC_CAP_INVERT Ta Yes 60.It PMC_CAP_READ Ta Yes 61.It PMC_CAP_PRECISE Ta \&No 62.It PMC_CAP_SYSTEM Ta Yes 63.It PMC_CAP_TAGGING Ta \&No 64.It PMC_CAP_THRESHOLD Ta Yes 65.It PMC_CAP_USER Ta \&No 66.It PMC_CAP_WRITE Ta Yes 67.El 68.Ss Event Qualifiers 69Event specifiers for these PMCs support the following common 70qualifiers: 71.Bl -tag -width indent 72.It Li inc= Ns Ar value 73Two-bit value that controls direction of count for PMC. 74Behavior depend on selected event. 75.It Li inv 76Invert the sense of comparison. 77.It Li match= Ns Ar value 78Count only events matched by 79.Ar value. 80.It Li mask= Ns Ar qualifier 81Allow to apply 82.Ar qualifier 83mask to compared 84.Ar value . 85.El 86.Ss Class Name Prefix 87These PMCs use a class name prefix of 88.Dq Li DMC620_CD2_ 89or 90.Dq Li DMC620_C_ . 91.Ss Event Specifiers 92The following PMC events are available: 93.Bl -column 94.It Sy clkdiv2_cycle_count 95.It Sy clkdiv2_allocate 96.It Sy clkdiv2_queue_depth 97.It Sy clkdiv2_waiting_for_wr_data 98.It Sy clkdiv2_read_backlog 99.It Sy clkdiv2_waiting_for_mi 100.It Sy clkdiv2_hazard_resolution 101.It Sy clkdiv2_enqueue 102.It Sy clkdiv2_arbitrate 103.It Sy clkdiv2_lrank_turnaround_activate 104.It Sy clkdiv2_prank_turnaround_activate 105.It Sy clkdiv2_read_depth 106.It Sy clkdiv2_write_depth 107.It Sy clkdiv2_highhigh_qos_depth 108.It Sy clkdiv2_high_qos_depth 109.It Sy clkdiv2_medium_qos_depth 110.It Sy clkdiv2_low_qos_depth 111.It Sy clkdiv2_activate 112.It Sy clkdiv2_rdwr 113.It Sy clkdiv2_refresh 114.It Sy clkdiv2_training_request 115.It Sy clkdiv2_t_mac_tracker 116.It Sy clkdiv2_bk_fsm_tracker 117.It Sy clkdiv2_bk_open_tracker 118.It Sy clkdiv2_ranks_in_pwr_down 119.It Sy clkdiv2_ranks_in_sref 120.It Sy clk_cycle_count 121.It Sy clk_request 122.It Sy clk_upload_stall 123.El 124.Sh SEE ALSO 125.Xr pmc 3 , 126.Xr pmc.atom 3 , 127.Xr pmc.core 3 , 128.Xr pmc.core2 3 , 129.Xr pmc.corei7 3 , 130.Xr pmc.corei7uc 3 , 131.Xr pmc.iaf 3 , 132.Xr pmc.iaf 3 , 133.Xr pmc.k7 3 , 134.Xr pmc.k8 3 , 135.Xr pmc.soft 3 , 136.Xr pmc.tsc 3 , 137.Xr pmc.westmere 3 , 138.Xr pmc.westmereuc 3 , 139.Xr pmc_cpuinfo 3 , 140.Xr pmclog 3 , 141.Xr hwpmc 4 142.Sh HISTORY 143The 144.Nm pmc 145library first appeared in 146.Fx 6.0 . 147.br 148The 149.Nm pmc.dmc-620 150driver was added in 151.Fx 14.0 . 152.Sh AUTHORS 153.An -nosplit 154The 155.Lb libpmc 156library was written by 157.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . 158.An Oleksandr Rybalko Aq Mt ray@FreeBSD.org . 159.br 160The DMC-620 PMU driver was sponsored by Ampere Computing LLC. 161This manual page was written by 162.An Oleksandr Rybalko Aq Mt ray@FreeBSD.org . 163