1[
2    {
3        "ArchStdEvent": "L1D_CACHE_RD"
4    },
5    {
6        "ArchStdEvent": "L1D_CACHE_WR"
7    },
8    {
9        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
10    },
11    {
12        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
13    },
14    {
15        "ArchStdEvent": "L1D_TLB_REFILL_RD"
16    },
17    {
18        "ArchStdEvent": "L1D_TLB_REFILL_WR"
19    },
20    {
21        "ArchStdEvent": "L1D_TLB_RD"
22    },
23    {
24        "ArchStdEvent": "L1D_TLB_WR"
25    },
26    {
27        "ArchStdEvent": "BUS_ACCESS_RD"
28   },
29   {
30        "ArchStdEvent": "BUS_ACCESS_WR"
31   }
32]
33