1[ 2 { 3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "CounterMask": "2", 7 "EventCode": "0xA3", 8 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 9 "SampleAfterValue": "2000003", 10 "UMask": "0x2" 11 }, 12 { 13 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "CounterMask": "6", 17 "EventCode": "0xA3", 18 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 19 "SampleAfterValue": "2000003", 20 "UMask": "0x6" 21 }, 22 { 23 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 24 "Counter": "0,1,2,3", 25 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "EventCode": "0xC8", 27 "EventName": "HLE_RETIRED.ABORTED", 28 "PEBS": "1", 29 "PublicDescription": "Number of times HLE abort was triggered.", 30 "SampleAfterValue": "2000003", 31 "UMask": "0x4" 32 }, 33 { 34 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 35 "Counter": "0,1,2,3", 36 "CounterHTOff": "0,1,2,3,4,5,6,7", 37 "EventCode": "0xC8", 38 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 39 "SampleAfterValue": "2000003", 40 "UMask": "0x80" 41 }, 42 { 43 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 44 "Counter": "0,1,2,3", 45 "CounterHTOff": "0,1,2,3,4,5,6,7", 46 "EventCode": "0xC8", 47 "EventName": "HLE_RETIRED.ABORTED_MEM", 48 "SampleAfterValue": "2000003", 49 "UMask": "0x8" 50 }, 51 { 52 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 53 "Counter": "0,1,2,3", 54 "CounterHTOff": "0,1,2,3,4,5,6,7", 55 "EventCode": "0xC8", 56 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 57 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 58 "SampleAfterValue": "2000003", 59 "UMask": "0x40" 60 }, 61 { 62 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 63 "Counter": "0,1,2,3", 64 "CounterHTOff": "0,1,2,3,4,5,6,7", 65 "EventCode": "0xC8", 66 "EventName": "HLE_RETIRED.ABORTED_TIMER", 67 "SampleAfterValue": "2000003", 68 "UMask": "0x10" 69 }, 70 { 71 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 72 "Counter": "0,1,2,3", 73 "CounterHTOff": "0,1,2,3,4,5,6,7", 74 "EventCode": "0xC8", 75 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 76 "SampleAfterValue": "2000003", 77 "UMask": "0x20" 78 }, 79 { 80 "BriefDescription": "Number of times an HLE execution successfully committed", 81 "Counter": "0,1,2,3", 82 "CounterHTOff": "0,1,2,3,4,5,6,7", 83 "EventCode": "0xC8", 84 "EventName": "HLE_RETIRED.COMMIT", 85 "PublicDescription": "Number of times HLE commit succeeded.", 86 "SampleAfterValue": "2000003", 87 "UMask": "0x2" 88 }, 89 { 90 "BriefDescription": "Number of times an HLE execution started.", 91 "Counter": "0,1,2,3", 92 "CounterHTOff": "0,1,2,3,4,5,6,7", 93 "EventCode": "0xC8", 94 "EventName": "HLE_RETIRED.START", 95 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 96 "SampleAfterValue": "2000003", 97 "UMask": "0x1" 98 }, 99 { 100 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 101 "Counter": "0,1,2,3", 102 "CounterHTOff": "0,1,2,3,4,5,6,7", 103 "Errata": "SKL089", 104 "EventCode": "0xC3", 105 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 106 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 107 "SampleAfterValue": "100003", 108 "UMask": "0x2" 109 }, 110 { 111 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 112 "Counter": "0,1,2,3", 113 "CounterHTOff": "0,1,2,3", 114 "Data_LA": "1", 115 "EventCode": "0xcd", 116 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 117 "MSRIndex": "0x3F6", 118 "MSRValue": "0x80", 119 "PEBS": "2", 120 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 121 "SampleAfterValue": "1009", 122 "TakenAlone": "1", 123 "UMask": "0x1" 124 }, 125 { 126 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 127 "Counter": "0,1,2,3", 128 "CounterHTOff": "0,1,2,3", 129 "Data_LA": "1", 130 "EventCode": "0xcd", 131 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 132 "MSRIndex": "0x3F6", 133 "MSRValue": "0x10", 134 "PEBS": "2", 135 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 136 "SampleAfterValue": "20011", 137 "TakenAlone": "1", 138 "UMask": "0x1" 139 }, 140 { 141 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 142 "Counter": "0,1,2,3", 143 "CounterHTOff": "0,1,2,3", 144 "Data_LA": "1", 145 "EventCode": "0xcd", 146 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 147 "MSRIndex": "0x3F6", 148 "MSRValue": "0x100", 149 "PEBS": "2", 150 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 151 "SampleAfterValue": "503", 152 "TakenAlone": "1", 153 "UMask": "0x1" 154 }, 155 { 156 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 157 "Counter": "0,1,2,3", 158 "CounterHTOff": "0,1,2,3", 159 "Data_LA": "1", 160 "EventCode": "0xcd", 161 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 162 "MSRIndex": "0x3F6", 163 "MSRValue": "0x20", 164 "PEBS": "2", 165 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 166 "SampleAfterValue": "100007", 167 "TakenAlone": "1", 168 "UMask": "0x1" 169 }, 170 { 171 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 172 "Counter": "0,1,2,3", 173 "CounterHTOff": "0,1,2,3", 174 "Data_LA": "1", 175 "EventCode": "0xcd", 176 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 177 "MSRIndex": "0x3F6", 178 "MSRValue": "0x4", 179 "PEBS": "2", 180 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 181 "SampleAfterValue": "100003", 182 "TakenAlone": "1", 183 "UMask": "0x1" 184 }, 185 { 186 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 187 "Counter": "0,1,2,3", 188 "CounterHTOff": "0,1,2,3", 189 "Data_LA": "1", 190 "EventCode": "0xcd", 191 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 192 "MSRIndex": "0x3F6", 193 "MSRValue": "0x200", 194 "PEBS": "2", 195 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 196 "SampleAfterValue": "101", 197 "TakenAlone": "1", 198 "UMask": "0x1" 199 }, 200 { 201 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 202 "Counter": "0,1,2,3", 203 "CounterHTOff": "0,1,2,3", 204 "Data_LA": "1", 205 "EventCode": "0xcd", 206 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 207 "MSRIndex": "0x3F6", 208 "MSRValue": "0x40", 209 "PEBS": "2", 210 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 211 "SampleAfterValue": "2003", 212 "TakenAlone": "1", 213 "UMask": "0x1" 214 }, 215 { 216 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 217 "Counter": "0,1,2,3", 218 "CounterHTOff": "0,1,2,3", 219 "Data_LA": "1", 220 "EventCode": "0xcd", 221 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 222 "MSRIndex": "0x3F6", 223 "MSRValue": "0x8", 224 "PEBS": "2", 225 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 226 "SampleAfterValue": "50021", 227 "TakenAlone": "1", 228 "UMask": "0x1" 229 }, 230 { 231 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 232 "Counter": "0,1,2,3", 233 "CounterHTOff": "0,1,2,3", 234 "EventCode": "0xB7, 0xBB", 235 "EventName": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 236 "MSRIndex": "0x1a6,0x1a7", 237 "MSRValue": "0x3FBC000491", 238 "Offcore": "1", 239 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 240 "SampleAfterValue": "100003", 241 "UMask": "0x1" 242 }, 243 { 244 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", 245 "Counter": "0,1,2,3", 246 "CounterHTOff": "0,1,2,3", 247 "EventCode": "0xB7, 0xBB", 248 "EventName": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", 249 "MSRIndex": "0x1a6,0x1a7", 250 "MSRValue": "0x103C000491", 251 "Offcore": "1", 252 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 253 "SampleAfterValue": "100003", 254 "UMask": "0x1" 255 }, 256 { 257 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 258 "Counter": "0,1,2,3", 259 "CounterHTOff": "0,1,2,3", 260 "EventCode": "0xB7, 0xBB", 261 "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 262 "MSRIndex": "0x1a6,0x1a7", 263 "MSRValue": "0x083C000491", 264 "Offcore": "1", 265 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 266 "SampleAfterValue": "100003", 267 "UMask": "0x1" 268 }, 269 { 270 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 271 "Counter": "0,1,2,3", 272 "CounterHTOff": "0,1,2,3", 273 "EventCode": "0xB7, 0xBB", 274 "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 275 "MSRIndex": "0x1a6,0x1a7", 276 "MSRValue": "0x043C000491", 277 "Offcore": "1", 278 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 279 "SampleAfterValue": "100003", 280 "UMask": "0x1" 281 }, 282 { 283 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 284 "Counter": "0,1,2,3", 285 "CounterHTOff": "0,1,2,3", 286 "EventCode": "0xB7, 0xBB", 287 "EventName": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 288 "MSRIndex": "0x1a6,0x1a7", 289 "MSRValue": "0x013C000491", 290 "Offcore": "1", 291 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 292 "SampleAfterValue": "100003", 293 "UMask": "0x1" 294 }, 295 { 296 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 297 "Counter": "0,1,2,3", 298 "CounterHTOff": "0,1,2,3", 299 "EventCode": "0xB7, 0xBB", 300 "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 301 "MSRIndex": "0x1a6,0x1a7", 302 "MSRValue": "0x103FC00491", 303 "Offcore": "1", 304 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 305 "SampleAfterValue": "100003", 306 "UMask": "0x1" 307 }, 308 { 309 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 310 "Counter": "0,1,2,3", 311 "CounterHTOff": "0,1,2,3", 312 "EventCode": "0xB7, 0xBB", 313 "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 314 "MSRIndex": "0x1a6,0x1a7", 315 "MSRValue": "0x083FC00491", 316 "Offcore": "1", 317 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 318 "SampleAfterValue": "100003", 319 "UMask": "0x1" 320 }, 321 { 322 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 323 "Counter": "0,1,2,3", 324 "CounterHTOff": "0,1,2,3", 325 "EventCode": "0xB7, 0xBB", 326 "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 327 "MSRIndex": "0x1a6,0x1a7", 328 "MSRValue": "0x023C000491", 329 "Offcore": "1", 330 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 331 "SampleAfterValue": "100003", 332 "UMask": "0x1" 333 }, 334 { 335 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 336 "Counter": "0,1,2,3", 337 "CounterHTOff": "0,1,2,3", 338 "EventCode": "0xB7, 0xBB", 339 "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 340 "MSRIndex": "0x1a6,0x1a7", 341 "MSRValue": "0x00BC000491", 342 "Offcore": "1", 343 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 344 "SampleAfterValue": "100003", 345 "UMask": "0x1" 346 }, 347 { 348 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 349 "Counter": "0,1,2,3", 350 "CounterHTOff": "0,1,2,3", 351 "EventCode": "0xB7, 0xBB", 352 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 353 "MSRIndex": "0x1a6,0x1a7", 354 "MSRValue": "0x3F84000491", 355 "Offcore": "1", 356 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 357 "SampleAfterValue": "100003", 358 "UMask": "0x1" 359 }, 360 { 361 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 362 "Counter": "0,1,2,3", 363 "CounterHTOff": "0,1,2,3", 364 "EventCode": "0xB7, 0xBB", 365 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 366 "MSRIndex": "0x1a6,0x1a7", 367 "MSRValue": "0x1004000491", 368 "Offcore": "1", 369 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 370 "SampleAfterValue": "100003", 371 "UMask": "0x1" 372 }, 373 { 374 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 375 "Counter": "0,1,2,3", 376 "CounterHTOff": "0,1,2,3", 377 "EventCode": "0xB7, 0xBB", 378 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 379 "MSRIndex": "0x1a6,0x1a7", 380 "MSRValue": "0x0804000491", 381 "Offcore": "1", 382 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 383 "SampleAfterValue": "100003", 384 "UMask": "0x1" 385 }, 386 { 387 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 388 "Counter": "0,1,2,3", 389 "CounterHTOff": "0,1,2,3", 390 "EventCode": "0xB7, 0xBB", 391 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 392 "MSRIndex": "0x1a6,0x1a7", 393 "MSRValue": "0x0404000491", 394 "Offcore": "1", 395 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 396 "SampleAfterValue": "100003", 397 "UMask": "0x1" 398 }, 399 { 400 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 401 "Counter": "0,1,2,3", 402 "CounterHTOff": "0,1,2,3", 403 "EventCode": "0xB7, 0xBB", 404 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 405 "MSRIndex": "0x1a6,0x1a7", 406 "MSRValue": "0x0104000491", 407 "Offcore": "1", 408 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 409 "SampleAfterValue": "100003", 410 "UMask": "0x1" 411 }, 412 { 413 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 414 "Counter": "0,1,2,3", 415 "CounterHTOff": "0,1,2,3", 416 "EventCode": "0xB7, 0xBB", 417 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 418 "MSRIndex": "0x1a6,0x1a7", 419 "MSRValue": "0x0204000491", 420 "Offcore": "1", 421 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 422 "SampleAfterValue": "100003", 423 "UMask": "0x1" 424 }, 425 { 426 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 427 "Counter": "0,1,2,3", 428 "CounterHTOff": "0,1,2,3", 429 "EventCode": "0xB7, 0xBB", 430 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 431 "MSRIndex": "0x1a6,0x1a7", 432 "MSRValue": "0x0604000491", 433 "Offcore": "1", 434 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 435 "SampleAfterValue": "100003", 436 "UMask": "0x1" 437 }, 438 { 439 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 440 "Counter": "0,1,2,3", 441 "CounterHTOff": "0,1,2,3", 442 "EventCode": "0xB7, 0xBB", 443 "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 444 "MSRIndex": "0x1a6,0x1a7", 445 "MSRValue": "0x0084000491", 446 "Offcore": "1", 447 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 448 "SampleAfterValue": "100003", 449 "UMask": "0x1" 450 }, 451 { 452 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 453 "Counter": "0,1,2,3", 454 "CounterHTOff": "0,1,2,3", 455 "EventCode": "0xB7, 0xBB", 456 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 457 "MSRIndex": "0x1a6,0x1a7", 458 "MSRValue": "0x063B800491", 459 "Offcore": "1", 460 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 461 "SampleAfterValue": "100003", 462 "UMask": "0x1" 463 }, 464 { 465 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 466 "Counter": "0,1,2,3", 467 "CounterHTOff": "0,1,2,3", 468 "EventCode": "0xB7, 0xBB", 469 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 470 "MSRIndex": "0x1a6,0x1a7", 471 "MSRValue": "0x3F90000491", 472 "Offcore": "1", 473 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 474 "SampleAfterValue": "100003", 475 "UMask": "0x1" 476 }, 477 { 478 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 479 "Counter": "0,1,2,3", 480 "CounterHTOff": "0,1,2,3", 481 "EventCode": "0xB7, 0xBB", 482 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 483 "MSRIndex": "0x1a6,0x1a7", 484 "MSRValue": "0x1010000491", 485 "Offcore": "1", 486 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 487 "SampleAfterValue": "100003", 488 "UMask": "0x1" 489 }, 490 { 491 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 492 "Counter": "0,1,2,3", 493 "CounterHTOff": "0,1,2,3", 494 "EventCode": "0xB7, 0xBB", 495 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 496 "MSRIndex": "0x1a6,0x1a7", 497 "MSRValue": "0x0810000491", 498 "Offcore": "1", 499 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 500 "SampleAfterValue": "100003", 501 "UMask": "0x1" 502 }, 503 { 504 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 505 "Counter": "0,1,2,3", 506 "CounterHTOff": "0,1,2,3", 507 "EventCode": "0xB7, 0xBB", 508 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 509 "MSRIndex": "0x1a6,0x1a7", 510 "MSRValue": "0x0410000491", 511 "Offcore": "1", 512 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 513 "SampleAfterValue": "100003", 514 "UMask": "0x1" 515 }, 516 { 517 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 518 "Counter": "0,1,2,3", 519 "CounterHTOff": "0,1,2,3", 520 "EventCode": "0xB7, 0xBB", 521 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 522 "MSRIndex": "0x1a6,0x1a7", 523 "MSRValue": "0x0110000491", 524 "Offcore": "1", 525 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 526 "SampleAfterValue": "100003", 527 "UMask": "0x1" 528 }, 529 { 530 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 531 "Counter": "0,1,2,3", 532 "CounterHTOff": "0,1,2,3", 533 "EventCode": "0xB7, 0xBB", 534 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 535 "MSRIndex": "0x1a6,0x1a7", 536 "MSRValue": "0x0210000491", 537 "Offcore": "1", 538 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 539 "SampleAfterValue": "100003", 540 "UMask": "0x1" 541 }, 542 { 543 "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 544 "Counter": "0,1,2,3", 545 "CounterHTOff": "0,1,2,3", 546 "EventCode": "0xB7, 0xBB", 547 "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 548 "MSRIndex": "0x1a6,0x1a7", 549 "MSRValue": "0x0090000491", 550 "Offcore": "1", 551 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 552 "SampleAfterValue": "100003", 553 "UMask": "0x1" 554 }, 555 { 556 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 557 "Counter": "0,1,2,3", 558 "CounterHTOff": "0,1,2,3", 559 "EventCode": "0xB7, 0xBB", 560 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 561 "MSRIndex": "0x1a6,0x1a7", 562 "MSRValue": "0x3FBC000490", 563 "Offcore": "1", 564 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 565 "SampleAfterValue": "100003", 566 "UMask": "0x1" 567 }, 568 { 569 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", 570 "Counter": "0,1,2,3", 571 "CounterHTOff": "0,1,2,3", 572 "EventCode": "0xB7, 0xBB", 573 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", 574 "MSRIndex": "0x1a6,0x1a7", 575 "MSRValue": "0x103C000490", 576 "Offcore": "1", 577 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 578 "SampleAfterValue": "100003", 579 "UMask": "0x1" 580 }, 581 { 582 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 583 "Counter": "0,1,2,3", 584 "CounterHTOff": "0,1,2,3", 585 "EventCode": "0xB7, 0xBB", 586 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 587 "MSRIndex": "0x1a6,0x1a7", 588 "MSRValue": "0x083C000490", 589 "Offcore": "1", 590 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 591 "SampleAfterValue": "100003", 592 "UMask": "0x1" 593 }, 594 { 595 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 596 "Counter": "0,1,2,3", 597 "CounterHTOff": "0,1,2,3", 598 "EventCode": "0xB7, 0xBB", 599 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 600 "MSRIndex": "0x1a6,0x1a7", 601 "MSRValue": "0x043C000490", 602 "Offcore": "1", 603 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 604 "SampleAfterValue": "100003", 605 "UMask": "0x1" 606 }, 607 { 608 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 609 "Counter": "0,1,2,3", 610 "CounterHTOff": "0,1,2,3", 611 "EventCode": "0xB7, 0xBB", 612 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 613 "MSRIndex": "0x1a6,0x1a7", 614 "MSRValue": "0x013C000490", 615 "Offcore": "1", 616 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 617 "SampleAfterValue": "100003", 618 "UMask": "0x1" 619 }, 620 { 621 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 622 "Counter": "0,1,2,3", 623 "CounterHTOff": "0,1,2,3", 624 "EventCode": "0xB7, 0xBB", 625 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 626 "MSRIndex": "0x1a6,0x1a7", 627 "MSRValue": "0x103FC00490", 628 "Offcore": "1", 629 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 630 "SampleAfterValue": "100003", 631 "UMask": "0x1" 632 }, 633 { 634 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 635 "Counter": "0,1,2,3", 636 "CounterHTOff": "0,1,2,3", 637 "EventCode": "0xB7, 0xBB", 638 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 639 "MSRIndex": "0x1a6,0x1a7", 640 "MSRValue": "0x083FC00490", 641 "Offcore": "1", 642 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 643 "SampleAfterValue": "100003", 644 "UMask": "0x1" 645 }, 646 { 647 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 648 "Counter": "0,1,2,3", 649 "CounterHTOff": "0,1,2,3", 650 "EventCode": "0xB7, 0xBB", 651 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 652 "MSRIndex": "0x1a6,0x1a7", 653 "MSRValue": "0x023C000490", 654 "Offcore": "1", 655 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 656 "SampleAfterValue": "100003", 657 "UMask": "0x1" 658 }, 659 { 660 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", 661 "Counter": "0,1,2,3", 662 "CounterHTOff": "0,1,2,3", 663 "EventCode": "0xB7, 0xBB", 664 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", 665 "MSRIndex": "0x1a6,0x1a7", 666 "MSRValue": "0x00BC000490", 667 "Offcore": "1", 668 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 669 "SampleAfterValue": "100003", 670 "UMask": "0x1" 671 }, 672 { 673 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 674 "Counter": "0,1,2,3", 675 "CounterHTOff": "0,1,2,3", 676 "EventCode": "0xB7, 0xBB", 677 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 678 "MSRIndex": "0x1a6,0x1a7", 679 "MSRValue": "0x3F84000490", 680 "Offcore": "1", 681 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 682 "SampleAfterValue": "100003", 683 "UMask": "0x1" 684 }, 685 { 686 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 687 "Counter": "0,1,2,3", 688 "CounterHTOff": "0,1,2,3", 689 "EventCode": "0xB7, 0xBB", 690 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 691 "MSRIndex": "0x1a6,0x1a7", 692 "MSRValue": "0x1004000490", 693 "Offcore": "1", 694 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 695 "SampleAfterValue": "100003", 696 "UMask": "0x1" 697 }, 698 { 699 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 700 "Counter": "0,1,2,3", 701 "CounterHTOff": "0,1,2,3", 702 "EventCode": "0xB7, 0xBB", 703 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 704 "MSRIndex": "0x1a6,0x1a7", 705 "MSRValue": "0x0804000490", 706 "Offcore": "1", 707 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 708 "SampleAfterValue": "100003", 709 "UMask": "0x1" 710 }, 711 { 712 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 713 "Counter": "0,1,2,3", 714 "CounterHTOff": "0,1,2,3", 715 "EventCode": "0xB7, 0xBB", 716 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 717 "MSRIndex": "0x1a6,0x1a7", 718 "MSRValue": "0x0404000490", 719 "Offcore": "1", 720 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 721 "SampleAfterValue": "100003", 722 "UMask": "0x1" 723 }, 724 { 725 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 726 "Counter": "0,1,2,3", 727 "CounterHTOff": "0,1,2,3", 728 "EventCode": "0xB7, 0xBB", 729 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 730 "MSRIndex": "0x1a6,0x1a7", 731 "MSRValue": "0x0104000490", 732 "Offcore": "1", 733 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 734 "SampleAfterValue": "100003", 735 "UMask": "0x1" 736 }, 737 { 738 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 739 "Counter": "0,1,2,3", 740 "CounterHTOff": "0,1,2,3", 741 "EventCode": "0xB7, 0xBB", 742 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 743 "MSRIndex": "0x1a6,0x1a7", 744 "MSRValue": "0x0204000490", 745 "Offcore": "1", 746 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 747 "SampleAfterValue": "100003", 748 "UMask": "0x1" 749 }, 750 { 751 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 752 "Counter": "0,1,2,3", 753 "CounterHTOff": "0,1,2,3", 754 "EventCode": "0xB7, 0xBB", 755 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 756 "MSRIndex": "0x1a6,0x1a7", 757 "MSRValue": "0x0604000490", 758 "Offcore": "1", 759 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 760 "SampleAfterValue": "100003", 761 "UMask": "0x1" 762 }, 763 { 764 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 765 "Counter": "0,1,2,3", 766 "CounterHTOff": "0,1,2,3", 767 "EventCode": "0xB7, 0xBB", 768 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 769 "MSRIndex": "0x1a6,0x1a7", 770 "MSRValue": "0x0084000490", 771 "Offcore": "1", 772 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 773 "SampleAfterValue": "100003", 774 "UMask": "0x1" 775 }, 776 { 777 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 778 "Counter": "0,1,2,3", 779 "CounterHTOff": "0,1,2,3", 780 "EventCode": "0xB7, 0xBB", 781 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 782 "MSRIndex": "0x1a6,0x1a7", 783 "MSRValue": "0x063B800490", 784 "Offcore": "1", 785 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 786 "SampleAfterValue": "100003", 787 "UMask": "0x1" 788 }, 789 { 790 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 791 "Counter": "0,1,2,3", 792 "CounterHTOff": "0,1,2,3", 793 "EventCode": "0xB7, 0xBB", 794 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 795 "MSRIndex": "0x1a6,0x1a7", 796 "MSRValue": "0x3F90000490", 797 "Offcore": "1", 798 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 799 "SampleAfterValue": "100003", 800 "UMask": "0x1" 801 }, 802 { 803 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 804 "Counter": "0,1,2,3", 805 "CounterHTOff": "0,1,2,3", 806 "EventCode": "0xB7, 0xBB", 807 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 808 "MSRIndex": "0x1a6,0x1a7", 809 "MSRValue": "0x1010000490", 810 "Offcore": "1", 811 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 812 "SampleAfterValue": "100003", 813 "UMask": "0x1" 814 }, 815 { 816 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 817 "Counter": "0,1,2,3", 818 "CounterHTOff": "0,1,2,3", 819 "EventCode": "0xB7, 0xBB", 820 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 821 "MSRIndex": "0x1a6,0x1a7", 822 "MSRValue": "0x0810000490", 823 "Offcore": "1", 824 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 825 "SampleAfterValue": "100003", 826 "UMask": "0x1" 827 }, 828 { 829 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 830 "Counter": "0,1,2,3", 831 "CounterHTOff": "0,1,2,3", 832 "EventCode": "0xB7, 0xBB", 833 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 834 "MSRIndex": "0x1a6,0x1a7", 835 "MSRValue": "0x0410000490", 836 "Offcore": "1", 837 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 838 "SampleAfterValue": "100003", 839 "UMask": "0x1" 840 }, 841 { 842 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 843 "Counter": "0,1,2,3", 844 "CounterHTOff": "0,1,2,3", 845 "EventCode": "0xB7, 0xBB", 846 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 847 "MSRIndex": "0x1a6,0x1a7", 848 "MSRValue": "0x0110000490", 849 "Offcore": "1", 850 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 851 "SampleAfterValue": "100003", 852 "UMask": "0x1" 853 }, 854 { 855 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 856 "Counter": "0,1,2,3", 857 "CounterHTOff": "0,1,2,3", 858 "EventCode": "0xB7, 0xBB", 859 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 860 "MSRIndex": "0x1a6,0x1a7", 861 "MSRValue": "0x0210000490", 862 "Offcore": "1", 863 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 864 "SampleAfterValue": "100003", 865 "UMask": "0x1" 866 }, 867 { 868 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 869 "Counter": "0,1,2,3", 870 "CounterHTOff": "0,1,2,3", 871 "EventCode": "0xB7, 0xBB", 872 "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 873 "MSRIndex": "0x1a6,0x1a7", 874 "MSRValue": "0x0090000490", 875 "Offcore": "1", 876 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 877 "SampleAfterValue": "100003", 878 "UMask": "0x1" 879 }, 880 { 881 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 882 "Counter": "0,1,2,3", 883 "CounterHTOff": "0,1,2,3", 884 "EventCode": "0xB7, 0xBB", 885 "EventName": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 886 "MSRIndex": "0x1a6,0x1a7", 887 "MSRValue": "0x3FBC000120", 888 "Offcore": "1", 889 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 890 "SampleAfterValue": "100003", 891 "UMask": "0x1" 892 }, 893 { 894 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", 895 "Counter": "0,1,2,3", 896 "CounterHTOff": "0,1,2,3", 897 "EventCode": "0xB7, 0xBB", 898 "EventName": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", 899 "MSRIndex": "0x1a6,0x1a7", 900 "MSRValue": "0x103C000120", 901 "Offcore": "1", 902 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 903 "SampleAfterValue": "100003", 904 "UMask": "0x1" 905 }, 906 { 907 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 908 "Counter": "0,1,2,3", 909 "CounterHTOff": "0,1,2,3", 910 "EventCode": "0xB7, 0xBB", 911 "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 912 "MSRIndex": "0x1a6,0x1a7", 913 "MSRValue": "0x083C000120", 914 "Offcore": "1", 915 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 916 "SampleAfterValue": "100003", 917 "UMask": "0x1" 918 }, 919 { 920 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 921 "Counter": "0,1,2,3", 922 "CounterHTOff": "0,1,2,3", 923 "EventCode": "0xB7, 0xBB", 924 "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 925 "MSRIndex": "0x1a6,0x1a7", 926 "MSRValue": "0x043C000120", 927 "Offcore": "1", 928 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 929 "SampleAfterValue": "100003", 930 "UMask": "0x1" 931 }, 932 { 933 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", 934 "Counter": "0,1,2,3", 935 "CounterHTOff": "0,1,2,3", 936 "EventCode": "0xB7, 0xBB", 937 "EventName": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", 938 "MSRIndex": "0x1a6,0x1a7", 939 "MSRValue": "0x013C000120", 940 "Offcore": "1", 941 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 942 "SampleAfterValue": "100003", 943 "UMask": "0x1" 944 }, 945 { 946 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 947 "Counter": "0,1,2,3", 948 "CounterHTOff": "0,1,2,3", 949 "EventCode": "0xB7, 0xBB", 950 "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 951 "MSRIndex": "0x1a6,0x1a7", 952 "MSRValue": "0x103FC00120", 953 "Offcore": "1", 954 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 955 "SampleAfterValue": "100003", 956 "UMask": "0x1" 957 }, 958 { 959 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 960 "Counter": "0,1,2,3", 961 "CounterHTOff": "0,1,2,3", 962 "EventCode": "0xB7, 0xBB", 963 "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 964 "MSRIndex": "0x1a6,0x1a7", 965 "MSRValue": "0x083FC00120", 966 "Offcore": "1", 967 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 968 "SampleAfterValue": "100003", 969 "UMask": "0x1" 970 }, 971 { 972 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", 973 "Counter": "0,1,2,3", 974 "CounterHTOff": "0,1,2,3", 975 "EventCode": "0xB7, 0xBB", 976 "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", 977 "MSRIndex": "0x1a6,0x1a7", 978 "MSRValue": "0x023C000120", 979 "Offcore": "1", 980 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 981 "SampleAfterValue": "100003", 982 "UMask": "0x1" 983 }, 984 { 985 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", 986 "Counter": "0,1,2,3", 987 "CounterHTOff": "0,1,2,3", 988 "EventCode": "0xB7, 0xBB", 989 "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", 990 "MSRIndex": "0x1a6,0x1a7", 991 "MSRValue": "0x00BC000120", 992 "Offcore": "1", 993 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 994 "SampleAfterValue": "100003", 995 "UMask": "0x1" 996 }, 997 { 998 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 999 "Counter": "0,1,2,3", 1000 "CounterHTOff": "0,1,2,3", 1001 "EventCode": "0xB7, 0xBB", 1002 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1003 "MSRIndex": "0x1a6,0x1a7", 1004 "MSRValue": "0x3F84000120", 1005 "Offcore": "1", 1006 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1007 "SampleAfterValue": "100003", 1008 "UMask": "0x1" 1009 }, 1010 { 1011 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1012 "Counter": "0,1,2,3", 1013 "CounterHTOff": "0,1,2,3", 1014 "EventCode": "0xB7, 0xBB", 1015 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1016 "MSRIndex": "0x1a6,0x1a7", 1017 "MSRValue": "0x1004000120", 1018 "Offcore": "1", 1019 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1020 "SampleAfterValue": "100003", 1021 "UMask": "0x1" 1022 }, 1023 { 1024 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1025 "Counter": "0,1,2,3", 1026 "CounterHTOff": "0,1,2,3", 1027 "EventCode": "0xB7, 0xBB", 1028 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1029 "MSRIndex": "0x1a6,0x1a7", 1030 "MSRValue": "0x0804000120", 1031 "Offcore": "1", 1032 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1033 "SampleAfterValue": "100003", 1034 "UMask": "0x1" 1035 }, 1036 { 1037 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1038 "Counter": "0,1,2,3", 1039 "CounterHTOff": "0,1,2,3", 1040 "EventCode": "0xB7, 0xBB", 1041 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1042 "MSRIndex": "0x1a6,0x1a7", 1043 "MSRValue": "0x0404000120", 1044 "Offcore": "1", 1045 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1046 "SampleAfterValue": "100003", 1047 "UMask": "0x1" 1048 }, 1049 { 1050 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1051 "Counter": "0,1,2,3", 1052 "CounterHTOff": "0,1,2,3", 1053 "EventCode": "0xB7, 0xBB", 1054 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1055 "MSRIndex": "0x1a6,0x1a7", 1056 "MSRValue": "0x0104000120", 1057 "Offcore": "1", 1058 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1059 "SampleAfterValue": "100003", 1060 "UMask": "0x1" 1061 }, 1062 { 1063 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1064 "Counter": "0,1,2,3", 1065 "CounterHTOff": "0,1,2,3", 1066 "EventCode": "0xB7, 0xBB", 1067 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1068 "MSRIndex": "0x1a6,0x1a7", 1069 "MSRValue": "0x0204000120", 1070 "Offcore": "1", 1071 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1072 "SampleAfterValue": "100003", 1073 "UMask": "0x1" 1074 }, 1075 { 1076 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1077 "Counter": "0,1,2,3", 1078 "CounterHTOff": "0,1,2,3", 1079 "EventCode": "0xB7, 0xBB", 1080 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1081 "MSRIndex": "0x1a6,0x1a7", 1082 "MSRValue": "0x0604000120", 1083 "Offcore": "1", 1084 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1085 "SampleAfterValue": "100003", 1086 "UMask": "0x1" 1087 }, 1088 { 1089 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1090 "Counter": "0,1,2,3", 1091 "CounterHTOff": "0,1,2,3", 1092 "EventCode": "0xB7, 0xBB", 1093 "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1094 "MSRIndex": "0x1a6,0x1a7", 1095 "MSRValue": "0x0084000120", 1096 "Offcore": "1", 1097 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1098 "SampleAfterValue": "100003", 1099 "UMask": "0x1" 1100 }, 1101 { 1102 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1103 "Counter": "0,1,2,3", 1104 "CounterHTOff": "0,1,2,3", 1105 "EventCode": "0xB7, 0xBB", 1106 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1107 "MSRIndex": "0x1a6,0x1a7", 1108 "MSRValue": "0x063B800120", 1109 "Offcore": "1", 1110 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1111 "SampleAfterValue": "100003", 1112 "UMask": "0x1" 1113 }, 1114 { 1115 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1116 "Counter": "0,1,2,3", 1117 "CounterHTOff": "0,1,2,3", 1118 "EventCode": "0xB7, 0xBB", 1119 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1120 "MSRIndex": "0x1a6,0x1a7", 1121 "MSRValue": "0x3F90000120", 1122 "Offcore": "1", 1123 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1124 "SampleAfterValue": "100003", 1125 "UMask": "0x1" 1126 }, 1127 { 1128 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1129 "Counter": "0,1,2,3", 1130 "CounterHTOff": "0,1,2,3", 1131 "EventCode": "0xB7, 0xBB", 1132 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1133 "MSRIndex": "0x1a6,0x1a7", 1134 "MSRValue": "0x1010000120", 1135 "Offcore": "1", 1136 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1137 "SampleAfterValue": "100003", 1138 "UMask": "0x1" 1139 }, 1140 { 1141 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1142 "Counter": "0,1,2,3", 1143 "CounterHTOff": "0,1,2,3", 1144 "EventCode": "0xB7, 0xBB", 1145 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1146 "MSRIndex": "0x1a6,0x1a7", 1147 "MSRValue": "0x0810000120", 1148 "Offcore": "1", 1149 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1150 "SampleAfterValue": "100003", 1151 "UMask": "0x1" 1152 }, 1153 { 1154 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1155 "Counter": "0,1,2,3", 1156 "CounterHTOff": "0,1,2,3", 1157 "EventCode": "0xB7, 0xBB", 1158 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1159 "MSRIndex": "0x1a6,0x1a7", 1160 "MSRValue": "0x0410000120", 1161 "Offcore": "1", 1162 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1163 "SampleAfterValue": "100003", 1164 "UMask": "0x1" 1165 }, 1166 { 1167 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1168 "Counter": "0,1,2,3", 1169 "CounterHTOff": "0,1,2,3", 1170 "EventCode": "0xB7, 0xBB", 1171 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1172 "MSRIndex": "0x1a6,0x1a7", 1173 "MSRValue": "0x0110000120", 1174 "Offcore": "1", 1175 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1176 "SampleAfterValue": "100003", 1177 "UMask": "0x1" 1178 }, 1179 { 1180 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1181 "Counter": "0,1,2,3", 1182 "CounterHTOff": "0,1,2,3", 1183 "EventCode": "0xB7, 0xBB", 1184 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1185 "MSRIndex": "0x1a6,0x1a7", 1186 "MSRValue": "0x0210000120", 1187 "Offcore": "1", 1188 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1189 "SampleAfterValue": "100003", 1190 "UMask": "0x1" 1191 }, 1192 { 1193 "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1194 "Counter": "0,1,2,3", 1195 "CounterHTOff": "0,1,2,3", 1196 "EventCode": "0xB7, 0xBB", 1197 "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1198 "MSRIndex": "0x1a6,0x1a7", 1199 "MSRValue": "0x0090000120", 1200 "Offcore": "1", 1201 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1202 "SampleAfterValue": "100003", 1203 "UMask": "0x1" 1204 }, 1205 { 1206 "BriefDescription": "OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP", 1207 "Counter": "0,1,2,3", 1208 "CounterHTOff": "0,1,2,3", 1209 "EventCode": "0xB7, 0xBB", 1210 "EventName": "OCR.ALL_READS.L3_MISS.ANY_SNOOP", 1211 "MSRIndex": "0x1a6,0x1a7", 1212 "MSRValue": "0x3FBC0007F7", 1213 "Offcore": "1", 1214 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1215 "SampleAfterValue": "100003", 1216 "UMask": "0x1" 1217 }, 1218 { 1219 "BriefDescription": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", 1220 "Counter": "0,1,2,3", 1221 "CounterHTOff": "0,1,2,3", 1222 "EventCode": "0xB7, 0xBB", 1223 "EventName": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", 1224 "MSRIndex": "0x1a6,0x1a7", 1225 "MSRValue": "0x103C0007F7", 1226 "Offcore": "1", 1227 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1228 "SampleAfterValue": "100003", 1229 "UMask": "0x1" 1230 }, 1231 { 1232 "BriefDescription": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", 1233 "Counter": "0,1,2,3", 1234 "CounterHTOff": "0,1,2,3", 1235 "EventCode": "0xB7, 0xBB", 1236 "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", 1237 "MSRIndex": "0x1a6,0x1a7", 1238 "MSRValue": "0x083C0007F7", 1239 "Offcore": "1", 1240 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1241 "SampleAfterValue": "100003", 1242 "UMask": "0x1" 1243 }, 1244 { 1245 "BriefDescription": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1246 "Counter": "0,1,2,3", 1247 "CounterHTOff": "0,1,2,3", 1248 "EventCode": "0xB7, 0xBB", 1249 "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1250 "MSRIndex": "0x1a6,0x1a7", 1251 "MSRValue": "0x043C0007F7", 1252 "Offcore": "1", 1253 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1254 "SampleAfterValue": "100003", 1255 "UMask": "0x1" 1256 }, 1257 { 1258 "BriefDescription": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", 1259 "Counter": "0,1,2,3", 1260 "CounterHTOff": "0,1,2,3", 1261 "EventCode": "0xB7, 0xBB", 1262 "EventName": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", 1263 "MSRIndex": "0x1a6,0x1a7", 1264 "MSRValue": "0x013C0007F7", 1265 "Offcore": "1", 1266 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1267 "SampleAfterValue": "100003", 1268 "UMask": "0x1" 1269 }, 1270 { 1271 "BriefDescription": "OCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_READS.L3_MISS.REMOTE_HITM", 1272 "Counter": "0,1,2,3", 1273 "CounterHTOff": "0,1,2,3", 1274 "EventCode": "0xB7, 0xBB", 1275 "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HITM", 1276 "MSRIndex": "0x1a6,0x1a7", 1277 "MSRValue": "0x103FC007F7", 1278 "Offcore": "1", 1279 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1280 "SampleAfterValue": "100003", 1281 "UMask": "0x1" 1282 }, 1283 { 1284 "BriefDescription": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", 1285 "Counter": "0,1,2,3", 1286 "CounterHTOff": "0,1,2,3", 1287 "EventCode": "0xB7, 0xBB", 1288 "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", 1289 "MSRIndex": "0x1a6,0x1a7", 1290 "MSRValue": "0x083FC007F7", 1291 "Offcore": "1", 1292 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1293 "SampleAfterValue": "100003", 1294 "UMask": "0x1" 1295 }, 1296 { 1297 "BriefDescription": "OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS.SNOOP_MISS", 1298 "Counter": "0,1,2,3", 1299 "CounterHTOff": "0,1,2,3", 1300 "EventCode": "0xB7, 0xBB", 1301 "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_MISS", 1302 "MSRIndex": "0x1a6,0x1a7", 1303 "MSRValue": "0x023C0007F7", 1304 "Offcore": "1", 1305 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1306 "SampleAfterValue": "100003", 1307 "UMask": "0x1" 1308 }, 1309 { 1310 "BriefDescription": "OCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READS.L3_MISS.SNOOP_NONE", 1311 "Counter": "0,1,2,3", 1312 "CounterHTOff": "0,1,2,3", 1313 "EventCode": "0xB7, 0xBB", 1314 "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_NONE", 1315 "MSRIndex": "0x1a6,0x1a7", 1316 "MSRValue": "0x00BC0007F7", 1317 "Offcore": "1", 1318 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1319 "SampleAfterValue": "100003", 1320 "UMask": "0x1" 1321 }, 1322 { 1323 "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1324 "Counter": "0,1,2,3", 1325 "CounterHTOff": "0,1,2,3", 1326 "EventCode": "0xB7, 0xBB", 1327 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1328 "MSRIndex": "0x1a6,0x1a7", 1329 "MSRValue": "0x3F840007F7", 1330 "Offcore": "1", 1331 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1332 "SampleAfterValue": "100003", 1333 "UMask": "0x1" 1334 }, 1335 { 1336 "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1337 "Counter": "0,1,2,3", 1338 "CounterHTOff": "0,1,2,3", 1339 "EventCode": "0xB7, 0xBB", 1340 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1341 "MSRIndex": "0x1a6,0x1a7", 1342 "MSRValue": "0x10040007F7", 1343 "Offcore": "1", 1344 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1345 "SampleAfterValue": "100003", 1346 "UMask": "0x1" 1347 }, 1348 { 1349 "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1350 "Counter": "0,1,2,3", 1351 "CounterHTOff": "0,1,2,3", 1352 "EventCode": "0xB7, 0xBB", 1353 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1354 "MSRIndex": "0x1a6,0x1a7", 1355 "MSRValue": "0x08040007F7", 1356 "Offcore": "1", 1357 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1358 "SampleAfterValue": "100003", 1359 "UMask": "0x1" 1360 }, 1361 { 1362 "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1363 "Counter": "0,1,2,3", 1364 "CounterHTOff": "0,1,2,3", 1365 "EventCode": "0xB7, 0xBB", 1366 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1367 "MSRIndex": "0x1a6,0x1a7", 1368 "MSRValue": "0x04040007F7", 1369 "Offcore": "1", 1370 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1371 "SampleAfterValue": "100003", 1372 "UMask": "0x1" 1373 }, 1374 { 1375 "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1376 "Counter": "0,1,2,3", 1377 "CounterHTOff": "0,1,2,3", 1378 "EventCode": "0xB7, 0xBB", 1379 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1380 "MSRIndex": "0x1a6,0x1a7", 1381 "MSRValue": "0x01040007F7", 1382 "Offcore": "1", 1383 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1384 "SampleAfterValue": "100003", 1385 "UMask": "0x1" 1386 }, 1387 { 1388 "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1389 "Counter": "0,1,2,3", 1390 "CounterHTOff": "0,1,2,3", 1391 "EventCode": "0xB7, 0xBB", 1392 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1393 "MSRIndex": "0x1a6,0x1a7", 1394 "MSRValue": "0x02040007F7", 1395 "Offcore": "1", 1396 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1397 "SampleAfterValue": "100003", 1398 "UMask": "0x1" 1399 }, 1400 { 1401 "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1402 "Counter": "0,1,2,3", 1403 "CounterHTOff": "0,1,2,3", 1404 "EventCode": "0xB7, 0xBB", 1405 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1406 "MSRIndex": "0x1a6,0x1a7", 1407 "MSRValue": "0x06040007F7", 1408 "Offcore": "1", 1409 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1410 "SampleAfterValue": "100003", 1411 "UMask": "0x1" 1412 }, 1413 { 1414 "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1415 "Counter": "0,1,2,3", 1416 "CounterHTOff": "0,1,2,3", 1417 "EventCode": "0xB7, 0xBB", 1418 "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1419 "MSRIndex": "0x1a6,0x1a7", 1420 "MSRValue": "0x00840007F7", 1421 "Offcore": "1", 1422 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1423 "SampleAfterValue": "100003", 1424 "UMask": "0x1" 1425 }, 1426 { 1427 "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1428 "Counter": "0,1,2,3", 1429 "CounterHTOff": "0,1,2,3", 1430 "EventCode": "0xB7, 0xBB", 1431 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1432 "MSRIndex": "0x1a6,0x1a7", 1433 "MSRValue": "0x063B8007F7", 1434 "Offcore": "1", 1435 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1436 "SampleAfterValue": "100003", 1437 "UMask": "0x1" 1438 }, 1439 { 1440 "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1441 "Counter": "0,1,2,3", 1442 "CounterHTOff": "0,1,2,3", 1443 "EventCode": "0xB7, 0xBB", 1444 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1445 "MSRIndex": "0x1a6,0x1a7", 1446 "MSRValue": "0x3F900007F7", 1447 "Offcore": "1", 1448 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1449 "SampleAfterValue": "100003", 1450 "UMask": "0x1" 1451 }, 1452 { 1453 "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1454 "Counter": "0,1,2,3", 1455 "CounterHTOff": "0,1,2,3", 1456 "EventCode": "0xB7, 0xBB", 1457 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1458 "MSRIndex": "0x1a6,0x1a7", 1459 "MSRValue": "0x10100007F7", 1460 "Offcore": "1", 1461 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1462 "SampleAfterValue": "100003", 1463 "UMask": "0x1" 1464 }, 1465 { 1466 "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1467 "Counter": "0,1,2,3", 1468 "CounterHTOff": "0,1,2,3", 1469 "EventCode": "0xB7, 0xBB", 1470 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1471 "MSRIndex": "0x1a6,0x1a7", 1472 "MSRValue": "0x08100007F7", 1473 "Offcore": "1", 1474 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1475 "SampleAfterValue": "100003", 1476 "UMask": "0x1" 1477 }, 1478 { 1479 "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1480 "Counter": "0,1,2,3", 1481 "CounterHTOff": "0,1,2,3", 1482 "EventCode": "0xB7, 0xBB", 1483 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1484 "MSRIndex": "0x1a6,0x1a7", 1485 "MSRValue": "0x04100007F7", 1486 "Offcore": "1", 1487 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1488 "SampleAfterValue": "100003", 1489 "UMask": "0x1" 1490 }, 1491 { 1492 "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1493 "Counter": "0,1,2,3", 1494 "CounterHTOff": "0,1,2,3", 1495 "EventCode": "0xB7, 0xBB", 1496 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1497 "MSRIndex": "0x1a6,0x1a7", 1498 "MSRValue": "0x01100007F7", 1499 "Offcore": "1", 1500 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1501 "SampleAfterValue": "100003", 1502 "UMask": "0x1" 1503 }, 1504 { 1505 "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1506 "Counter": "0,1,2,3", 1507 "CounterHTOff": "0,1,2,3", 1508 "EventCode": "0xB7, 0xBB", 1509 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1510 "MSRIndex": "0x1a6,0x1a7", 1511 "MSRValue": "0x02100007F7", 1512 "Offcore": "1", 1513 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1514 "SampleAfterValue": "100003", 1515 "UMask": "0x1" 1516 }, 1517 { 1518 "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1519 "Counter": "0,1,2,3", 1520 "CounterHTOff": "0,1,2,3", 1521 "EventCode": "0xB7, 0xBB", 1522 "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1523 "MSRIndex": "0x1a6,0x1a7", 1524 "MSRValue": "0x00900007F7", 1525 "Offcore": "1", 1526 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1527 "SampleAfterValue": "100003", 1528 "UMask": "0x1" 1529 }, 1530 { 1531 "BriefDescription": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP", 1532 "Counter": "0,1,2,3", 1533 "CounterHTOff": "0,1,2,3", 1534 "EventCode": "0xB7, 0xBB", 1535 "EventName": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP", 1536 "MSRIndex": "0x1a6,0x1a7", 1537 "MSRValue": "0x3FBC000122", 1538 "Offcore": "1", 1539 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1540 "SampleAfterValue": "100003", 1541 "UMask": "0x1" 1542 }, 1543 { 1544 "BriefDescription": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", 1545 "Counter": "0,1,2,3", 1546 "CounterHTOff": "0,1,2,3", 1547 "EventCode": "0xB7, 0xBB", 1548 "EventName": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", 1549 "MSRIndex": "0x1a6,0x1a7", 1550 "MSRValue": "0x103C000122", 1551 "Offcore": "1", 1552 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1553 "SampleAfterValue": "100003", 1554 "UMask": "0x1" 1555 }, 1556 { 1557 "BriefDescription": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 1558 "Counter": "0,1,2,3", 1559 "CounterHTOff": "0,1,2,3", 1560 "EventCode": "0xB7, 0xBB", 1561 "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 1562 "MSRIndex": "0x1a6,0x1a7", 1563 "MSRValue": "0x083C000122", 1564 "Offcore": "1", 1565 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1566 "SampleAfterValue": "100003", 1567 "UMask": "0x1" 1568 }, 1569 { 1570 "BriefDescription": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1571 "Counter": "0,1,2,3", 1572 "CounterHTOff": "0,1,2,3", 1573 "EventCode": "0xB7, 0xBB", 1574 "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1575 "MSRIndex": "0x1a6,0x1a7", 1576 "MSRValue": "0x043C000122", 1577 "Offcore": "1", 1578 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1579 "SampleAfterValue": "100003", 1580 "UMask": "0x1" 1581 }, 1582 { 1583 "BriefDescription": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", 1584 "Counter": "0,1,2,3", 1585 "CounterHTOff": "0,1,2,3", 1586 "EventCode": "0xB7, 0xBB", 1587 "EventName": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", 1588 "MSRIndex": "0x1a6,0x1a7", 1589 "MSRValue": "0x013C000122", 1590 "Offcore": "1", 1591 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1592 "SampleAfterValue": "100003", 1593 "UMask": "0x1" 1594 }, 1595 { 1596 "BriefDescription": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS.REMOTE_HITM", 1597 "Counter": "0,1,2,3", 1598 "CounterHTOff": "0,1,2,3", 1599 "EventCode": "0xB7, 0xBB", 1600 "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM", 1601 "MSRIndex": "0x1a6,0x1a7", 1602 "MSRValue": "0x103FC00122", 1603 "Offcore": "1", 1604 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1605 "SampleAfterValue": "100003", 1606 "UMask": "0x1" 1607 }, 1608 { 1609 "BriefDescription": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 1610 "Counter": "0,1,2,3", 1611 "CounterHTOff": "0,1,2,3", 1612 "EventCode": "0xB7, 0xBB", 1613 "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 1614 "MSRIndex": "0x1a6,0x1a7", 1615 "MSRValue": "0x083FC00122", 1616 "Offcore": "1", 1617 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1618 "SampleAfterValue": "100003", 1619 "UMask": "0x1" 1620 }, 1621 { 1622 "BriefDescription": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3_MISS.SNOOP_MISS", 1623 "Counter": "0,1,2,3", 1624 "CounterHTOff": "0,1,2,3", 1625 "EventCode": "0xB7, 0xBB", 1626 "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS", 1627 "MSRIndex": "0x1a6,0x1a7", 1628 "MSRValue": "0x023C000122", 1629 "Offcore": "1", 1630 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1631 "SampleAfterValue": "100003", 1632 "UMask": "0x1" 1633 }, 1634 { 1635 "BriefDescription": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS.SNOOP_NONE", 1636 "Counter": "0,1,2,3", 1637 "CounterHTOff": "0,1,2,3", 1638 "EventCode": "0xB7, 0xBB", 1639 "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE", 1640 "MSRIndex": "0x1a6,0x1a7", 1641 "MSRValue": "0x00BC000122", 1642 "Offcore": "1", 1643 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1644 "SampleAfterValue": "100003", 1645 "UMask": "0x1" 1646 }, 1647 { 1648 "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1649 "Counter": "0,1,2,3", 1650 "CounterHTOff": "0,1,2,3", 1651 "EventCode": "0xB7, 0xBB", 1652 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1653 "MSRIndex": "0x1a6,0x1a7", 1654 "MSRValue": "0x3F84000122", 1655 "Offcore": "1", 1656 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1657 "SampleAfterValue": "100003", 1658 "UMask": "0x1" 1659 }, 1660 { 1661 "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1662 "Counter": "0,1,2,3", 1663 "CounterHTOff": "0,1,2,3", 1664 "EventCode": "0xB7, 0xBB", 1665 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1666 "MSRIndex": "0x1a6,0x1a7", 1667 "MSRValue": "0x1004000122", 1668 "Offcore": "1", 1669 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1670 "SampleAfterValue": "100003", 1671 "UMask": "0x1" 1672 }, 1673 { 1674 "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1675 "Counter": "0,1,2,3", 1676 "CounterHTOff": "0,1,2,3", 1677 "EventCode": "0xB7, 0xBB", 1678 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 1679 "MSRIndex": "0x1a6,0x1a7", 1680 "MSRValue": "0x0804000122", 1681 "Offcore": "1", 1682 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1683 "SampleAfterValue": "100003", 1684 "UMask": "0x1" 1685 }, 1686 { 1687 "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1688 "Counter": "0,1,2,3", 1689 "CounterHTOff": "0,1,2,3", 1690 "EventCode": "0xB7, 0xBB", 1691 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 1692 "MSRIndex": "0x1a6,0x1a7", 1693 "MSRValue": "0x0404000122", 1694 "Offcore": "1", 1695 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1696 "SampleAfterValue": "100003", 1697 "UMask": "0x1" 1698 }, 1699 { 1700 "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1701 "Counter": "0,1,2,3", 1702 "CounterHTOff": "0,1,2,3", 1703 "EventCode": "0xB7, 0xBB", 1704 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 1705 "MSRIndex": "0x1a6,0x1a7", 1706 "MSRValue": "0x0104000122", 1707 "Offcore": "1", 1708 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1709 "SampleAfterValue": "100003", 1710 "UMask": "0x1" 1711 }, 1712 { 1713 "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1714 "Counter": "0,1,2,3", 1715 "CounterHTOff": "0,1,2,3", 1716 "EventCode": "0xB7, 0xBB", 1717 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1718 "MSRIndex": "0x1a6,0x1a7", 1719 "MSRValue": "0x0204000122", 1720 "Offcore": "1", 1721 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1722 "SampleAfterValue": "100003", 1723 "UMask": "0x1" 1724 }, 1725 { 1726 "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1727 "Counter": "0,1,2,3", 1728 "CounterHTOff": "0,1,2,3", 1729 "EventCode": "0xB7, 0xBB", 1730 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 1731 "MSRIndex": "0x1a6,0x1a7", 1732 "MSRValue": "0x0604000122", 1733 "Offcore": "1", 1734 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1735 "SampleAfterValue": "100003", 1736 "UMask": "0x1" 1737 }, 1738 { 1739 "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1740 "Counter": "0,1,2,3", 1741 "CounterHTOff": "0,1,2,3", 1742 "EventCode": "0xB7, 0xBB", 1743 "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1744 "MSRIndex": "0x1a6,0x1a7", 1745 "MSRValue": "0x0084000122", 1746 "Offcore": "1", 1747 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1748 "SampleAfterValue": "100003", 1749 "UMask": "0x1" 1750 }, 1751 { 1752 "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1753 "Counter": "0,1,2,3", 1754 "CounterHTOff": "0,1,2,3", 1755 "EventCode": "0xB7, 0xBB", 1756 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 1757 "MSRIndex": "0x1a6,0x1a7", 1758 "MSRValue": "0x063B800122", 1759 "Offcore": "1", 1760 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1761 "SampleAfterValue": "100003", 1762 "UMask": "0x1" 1763 }, 1764 { 1765 "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1766 "Counter": "0,1,2,3", 1767 "CounterHTOff": "0,1,2,3", 1768 "EventCode": "0xB7, 0xBB", 1769 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 1770 "MSRIndex": "0x1a6,0x1a7", 1771 "MSRValue": "0x3F90000122", 1772 "Offcore": "1", 1773 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1774 "SampleAfterValue": "100003", 1775 "UMask": "0x1" 1776 }, 1777 { 1778 "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1779 "Counter": "0,1,2,3", 1780 "CounterHTOff": "0,1,2,3", 1781 "EventCode": "0xB7, 0xBB", 1782 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 1783 "MSRIndex": "0x1a6,0x1a7", 1784 "MSRValue": "0x1010000122", 1785 "Offcore": "1", 1786 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1787 "SampleAfterValue": "100003", 1788 "UMask": "0x1" 1789 }, 1790 { 1791 "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1792 "Counter": "0,1,2,3", 1793 "CounterHTOff": "0,1,2,3", 1794 "EventCode": "0xB7, 0xBB", 1795 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 1796 "MSRIndex": "0x1a6,0x1a7", 1797 "MSRValue": "0x0810000122", 1798 "Offcore": "1", 1799 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1800 "SampleAfterValue": "100003", 1801 "UMask": "0x1" 1802 }, 1803 { 1804 "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1805 "Counter": "0,1,2,3", 1806 "CounterHTOff": "0,1,2,3", 1807 "EventCode": "0xB7, 0xBB", 1808 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 1809 "MSRIndex": "0x1a6,0x1a7", 1810 "MSRValue": "0x0410000122", 1811 "Offcore": "1", 1812 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1813 "SampleAfterValue": "100003", 1814 "UMask": "0x1" 1815 }, 1816 { 1817 "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1818 "Counter": "0,1,2,3", 1819 "CounterHTOff": "0,1,2,3", 1820 "EventCode": "0xB7, 0xBB", 1821 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 1822 "MSRIndex": "0x1a6,0x1a7", 1823 "MSRValue": "0x0110000122", 1824 "Offcore": "1", 1825 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1826 "SampleAfterValue": "100003", 1827 "UMask": "0x1" 1828 }, 1829 { 1830 "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1831 "Counter": "0,1,2,3", 1832 "CounterHTOff": "0,1,2,3", 1833 "EventCode": "0xB7, 0xBB", 1834 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 1835 "MSRIndex": "0x1a6,0x1a7", 1836 "MSRValue": "0x0210000122", 1837 "Offcore": "1", 1838 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1839 "SampleAfterValue": "100003", 1840 "UMask": "0x1" 1841 }, 1842 { 1843 "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1844 "Counter": "0,1,2,3", 1845 "CounterHTOff": "0,1,2,3", 1846 "EventCode": "0xB7, 0xBB", 1847 "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 1848 "MSRIndex": "0x1a6,0x1a7", 1849 "MSRValue": "0x0090000122", 1850 "Offcore": "1", 1851 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1852 "SampleAfterValue": "100003", 1853 "UMask": "0x1" 1854 }, 1855 { 1856 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 1857 "Counter": "0,1,2,3", 1858 "CounterHTOff": "0,1,2,3", 1859 "EventCode": "0xB7, 0xBB", 1860 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 1861 "MSRIndex": "0x1a6,0x1a7", 1862 "MSRValue": "0x3FBC000004", 1863 "Offcore": "1", 1864 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1865 "SampleAfterValue": "100003", 1866 "UMask": "0x1" 1867 }, 1868 { 1869 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", 1870 "Counter": "0,1,2,3", 1871 "CounterHTOff": "0,1,2,3", 1872 "EventCode": "0xB7, 0xBB", 1873 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", 1874 "MSRIndex": "0x1a6,0x1a7", 1875 "MSRValue": "0x103C000004", 1876 "Offcore": "1", 1877 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1878 "SampleAfterValue": "100003", 1879 "UMask": "0x1" 1880 }, 1881 { 1882 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", 1883 "Counter": "0,1,2,3", 1884 "CounterHTOff": "0,1,2,3", 1885 "EventCode": "0xB7, 0xBB", 1886 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", 1887 "MSRIndex": "0x1a6,0x1a7", 1888 "MSRValue": "0x083C000004", 1889 "Offcore": "1", 1890 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1891 "SampleAfterValue": "100003", 1892 "UMask": "0x1" 1893 }, 1894 { 1895 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1896 "Counter": "0,1,2,3", 1897 "CounterHTOff": "0,1,2,3", 1898 "EventCode": "0xB7, 0xBB", 1899 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 1900 "MSRIndex": "0x1a6,0x1a7", 1901 "MSRValue": "0x043C000004", 1902 "Offcore": "1", 1903 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1904 "SampleAfterValue": "100003", 1905 "UMask": "0x1" 1906 }, 1907 { 1908 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", 1909 "Counter": "0,1,2,3", 1910 "CounterHTOff": "0,1,2,3", 1911 "EventCode": "0xB7, 0xBB", 1912 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", 1913 "MSRIndex": "0x1a6,0x1a7", 1914 "MSRValue": "0x013C000004", 1915 "Offcore": "1", 1916 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1917 "SampleAfterValue": "100003", 1918 "UMask": "0x1" 1919 }, 1920 { 1921 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 1922 "Counter": "0,1,2,3", 1923 "CounterHTOff": "0,1,2,3", 1924 "EventCode": "0xB7, 0xBB", 1925 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 1926 "MSRIndex": "0x1a6,0x1a7", 1927 "MSRValue": "0x103FC00004", 1928 "Offcore": "1", 1929 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1930 "SampleAfterValue": "100003", 1931 "UMask": "0x1" 1932 }, 1933 { 1934 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 1935 "Counter": "0,1,2,3", 1936 "CounterHTOff": "0,1,2,3", 1937 "EventCode": "0xB7, 0xBB", 1938 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 1939 "MSRIndex": "0x1a6,0x1a7", 1940 "MSRValue": "0x083FC00004", 1941 "Offcore": "1", 1942 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1943 "SampleAfterValue": "100003", 1944 "UMask": "0x1" 1945 }, 1946 { 1947 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 1948 "Counter": "0,1,2,3", 1949 "CounterHTOff": "0,1,2,3", 1950 "EventCode": "0xB7, 0xBB", 1951 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 1952 "MSRIndex": "0x1a6,0x1a7", 1953 "MSRValue": "0x023C000004", 1954 "Offcore": "1", 1955 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1956 "SampleAfterValue": "100003", 1957 "UMask": "0x1" 1958 }, 1959 { 1960 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 1961 "Counter": "0,1,2,3", 1962 "CounterHTOff": "0,1,2,3", 1963 "EventCode": "0xB7, 0xBB", 1964 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 1965 "MSRIndex": "0x1a6,0x1a7", 1966 "MSRValue": "0x00BC000004", 1967 "Offcore": "1", 1968 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1969 "SampleAfterValue": "100003", 1970 "UMask": "0x1" 1971 }, 1972 { 1973 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1974 "Counter": "0,1,2,3", 1975 "CounterHTOff": "0,1,2,3", 1976 "EventCode": "0xB7, 0xBB", 1977 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 1978 "MSRIndex": "0x1a6,0x1a7", 1979 "MSRValue": "0x3F84000004", 1980 "Offcore": "1", 1981 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1982 "SampleAfterValue": "100003", 1983 "UMask": "0x1" 1984 }, 1985 { 1986 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1987 "Counter": "0,1,2,3", 1988 "CounterHTOff": "0,1,2,3", 1989 "EventCode": "0xB7, 0xBB", 1990 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 1991 "MSRIndex": "0x1a6,0x1a7", 1992 "MSRValue": "0x1004000004", 1993 "Offcore": "1", 1994 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1995 "SampleAfterValue": "100003", 1996 "UMask": "0x1" 1997 }, 1998 { 1999 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2000 "Counter": "0,1,2,3", 2001 "CounterHTOff": "0,1,2,3", 2002 "EventCode": "0xB7, 0xBB", 2003 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2004 "MSRIndex": "0x1a6,0x1a7", 2005 "MSRValue": "0x0804000004", 2006 "Offcore": "1", 2007 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2008 "SampleAfterValue": "100003", 2009 "UMask": "0x1" 2010 }, 2011 { 2012 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2013 "Counter": "0,1,2,3", 2014 "CounterHTOff": "0,1,2,3", 2015 "EventCode": "0xB7, 0xBB", 2016 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2017 "MSRIndex": "0x1a6,0x1a7", 2018 "MSRValue": "0x0404000004", 2019 "Offcore": "1", 2020 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2021 "SampleAfterValue": "100003", 2022 "UMask": "0x1" 2023 }, 2024 { 2025 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2026 "Counter": "0,1,2,3", 2027 "CounterHTOff": "0,1,2,3", 2028 "EventCode": "0xB7, 0xBB", 2029 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2030 "MSRIndex": "0x1a6,0x1a7", 2031 "MSRValue": "0x0104000004", 2032 "Offcore": "1", 2033 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2034 "SampleAfterValue": "100003", 2035 "UMask": "0x1" 2036 }, 2037 { 2038 "BriefDescription": "Counts all demand code reads", 2039 "Counter": "0,1,2,3", 2040 "CounterHTOff": "0,1,2,3", 2041 "EventCode": "0xB7, 0xBB", 2042 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2043 "MSRIndex": "0x1a6,0x1a7", 2044 "MSRValue": "0x0204000004", 2045 "Offcore": "1", 2046 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2047 "SampleAfterValue": "100003", 2048 "UMask": "0x1" 2049 }, 2050 { 2051 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 2052 "Counter": "0,1,2,3", 2053 "CounterHTOff": "0,1,2,3", 2054 "EventCode": "0xB7, 0xBB", 2055 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 2056 "MSRIndex": "0x1a6,0x1a7", 2057 "MSRValue": "0x0604000004", 2058 "Offcore": "1", 2059 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2060 "SampleAfterValue": "100003", 2061 "UMask": "0x1" 2062 }, 2063 { 2064 "BriefDescription": "Counts all demand code reads", 2065 "Counter": "0,1,2,3", 2066 "CounterHTOff": "0,1,2,3", 2067 "EventCode": "0xB7, 0xBB", 2068 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2069 "MSRIndex": "0x1a6,0x1a7", 2070 "MSRValue": "0x0084000004", 2071 "Offcore": "1", 2072 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2073 "SampleAfterValue": "100003", 2074 "UMask": "0x1" 2075 }, 2076 { 2077 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 2078 "Counter": "0,1,2,3", 2079 "CounterHTOff": "0,1,2,3", 2080 "EventCode": "0xB7, 0xBB", 2081 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 2082 "MSRIndex": "0x1a6,0x1a7", 2083 "MSRValue": "0x063B800004", 2084 "Offcore": "1", 2085 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2086 "SampleAfterValue": "100003", 2087 "UMask": "0x1" 2088 }, 2089 { 2090 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2091 "Counter": "0,1,2,3", 2092 "CounterHTOff": "0,1,2,3", 2093 "EventCode": "0xB7, 0xBB", 2094 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2095 "MSRIndex": "0x1a6,0x1a7", 2096 "MSRValue": "0x3F90000004", 2097 "Offcore": "1", 2098 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2099 "SampleAfterValue": "100003", 2100 "UMask": "0x1" 2101 }, 2102 { 2103 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2104 "Counter": "0,1,2,3", 2105 "CounterHTOff": "0,1,2,3", 2106 "EventCode": "0xB7, 0xBB", 2107 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2108 "MSRIndex": "0x1a6,0x1a7", 2109 "MSRValue": "0x1010000004", 2110 "Offcore": "1", 2111 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2112 "SampleAfterValue": "100003", 2113 "UMask": "0x1" 2114 }, 2115 { 2116 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2117 "Counter": "0,1,2,3", 2118 "CounterHTOff": "0,1,2,3", 2119 "EventCode": "0xB7, 0xBB", 2120 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2121 "MSRIndex": "0x1a6,0x1a7", 2122 "MSRValue": "0x0810000004", 2123 "Offcore": "1", 2124 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2125 "SampleAfterValue": "100003", 2126 "UMask": "0x1" 2127 }, 2128 { 2129 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2130 "Counter": "0,1,2,3", 2131 "CounterHTOff": "0,1,2,3", 2132 "EventCode": "0xB7, 0xBB", 2133 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2134 "MSRIndex": "0x1a6,0x1a7", 2135 "MSRValue": "0x0410000004", 2136 "Offcore": "1", 2137 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2138 "SampleAfterValue": "100003", 2139 "UMask": "0x1" 2140 }, 2141 { 2142 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2143 "Counter": "0,1,2,3", 2144 "CounterHTOff": "0,1,2,3", 2145 "EventCode": "0xB7, 0xBB", 2146 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2147 "MSRIndex": "0x1a6,0x1a7", 2148 "MSRValue": "0x0110000004", 2149 "Offcore": "1", 2150 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2151 "SampleAfterValue": "100003", 2152 "UMask": "0x1" 2153 }, 2154 { 2155 "BriefDescription": "Counts all demand code reads", 2156 "Counter": "0,1,2,3", 2157 "CounterHTOff": "0,1,2,3", 2158 "EventCode": "0xB7, 0xBB", 2159 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2160 "MSRIndex": "0x1a6,0x1a7", 2161 "MSRValue": "0x0210000004", 2162 "Offcore": "1", 2163 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2164 "SampleAfterValue": "100003", 2165 "UMask": "0x1" 2166 }, 2167 { 2168 "BriefDescription": "Counts all demand code reads", 2169 "Counter": "0,1,2,3", 2170 "CounterHTOff": "0,1,2,3", 2171 "EventCode": "0xB7, 0xBB", 2172 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2173 "MSRIndex": "0x1a6,0x1a7", 2174 "MSRValue": "0x0090000004", 2175 "Offcore": "1", 2176 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2177 "SampleAfterValue": "100003", 2178 "UMask": "0x1" 2179 }, 2180 { 2181 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 2182 "Counter": "0,1,2,3", 2183 "CounterHTOff": "0,1,2,3", 2184 "EventCode": "0xB7, 0xBB", 2185 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 2186 "MSRIndex": "0x1a6,0x1a7", 2187 "MSRValue": "0x3FBC000001", 2188 "Offcore": "1", 2189 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2190 "SampleAfterValue": "100003", 2191 "UMask": "0x1" 2192 }, 2193 { 2194 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", 2195 "Counter": "0,1,2,3", 2196 "CounterHTOff": "0,1,2,3", 2197 "EventCode": "0xB7, 0xBB", 2198 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", 2199 "MSRIndex": "0x1a6,0x1a7", 2200 "MSRValue": "0x103C000001", 2201 "Offcore": "1", 2202 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2203 "SampleAfterValue": "100003", 2204 "UMask": "0x1" 2205 }, 2206 { 2207 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 2208 "Counter": "0,1,2,3", 2209 "CounterHTOff": "0,1,2,3", 2210 "EventCode": "0xB7, 0xBB", 2211 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 2212 "MSRIndex": "0x1a6,0x1a7", 2213 "MSRValue": "0x083C000001", 2214 "Offcore": "1", 2215 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2216 "SampleAfterValue": "100003", 2217 "UMask": "0x1" 2218 }, 2219 { 2220 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2221 "Counter": "0,1,2,3", 2222 "CounterHTOff": "0,1,2,3", 2223 "EventCode": "0xB7, 0xBB", 2224 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2225 "MSRIndex": "0x1a6,0x1a7", 2226 "MSRValue": "0x043C000001", 2227 "Offcore": "1", 2228 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2229 "SampleAfterValue": "100003", 2230 "UMask": "0x1" 2231 }, 2232 { 2233 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 2234 "Counter": "0,1,2,3", 2235 "CounterHTOff": "0,1,2,3", 2236 "EventCode": "0xB7, 0xBB", 2237 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 2238 "MSRIndex": "0x1a6,0x1a7", 2239 "MSRValue": "0x013C000001", 2240 "Offcore": "1", 2241 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2242 "SampleAfterValue": "100003", 2243 "UMask": "0x1" 2244 }, 2245 { 2246 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 2247 "Counter": "0,1,2,3", 2248 "CounterHTOff": "0,1,2,3", 2249 "EventCode": "0xB7, 0xBB", 2250 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 2251 "MSRIndex": "0x1a6,0x1a7", 2252 "MSRValue": "0x103FC00001", 2253 "Offcore": "1", 2254 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2255 "SampleAfterValue": "100003", 2256 "UMask": "0x1" 2257 }, 2258 { 2259 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 2260 "Counter": "0,1,2,3", 2261 "CounterHTOff": "0,1,2,3", 2262 "EventCode": "0xB7, 0xBB", 2263 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 2264 "MSRIndex": "0x1a6,0x1a7", 2265 "MSRValue": "0x083FC00001", 2266 "Offcore": "1", 2267 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2268 "SampleAfterValue": "100003", 2269 "UMask": "0x1" 2270 }, 2271 { 2272 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 2273 "Counter": "0,1,2,3", 2274 "CounterHTOff": "0,1,2,3", 2275 "EventCode": "0xB7, 0xBB", 2276 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 2277 "MSRIndex": "0x1a6,0x1a7", 2278 "MSRValue": "0x023C000001", 2279 "Offcore": "1", 2280 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2281 "SampleAfterValue": "100003", 2282 "UMask": "0x1" 2283 }, 2284 { 2285 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 2286 "Counter": "0,1,2,3", 2287 "CounterHTOff": "0,1,2,3", 2288 "EventCode": "0xB7, 0xBB", 2289 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 2290 "MSRIndex": "0x1a6,0x1a7", 2291 "MSRValue": "0x00BC000001", 2292 "Offcore": "1", 2293 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2294 "SampleAfterValue": "100003", 2295 "UMask": "0x1" 2296 }, 2297 { 2298 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2299 "Counter": "0,1,2,3", 2300 "CounterHTOff": "0,1,2,3", 2301 "EventCode": "0xB7, 0xBB", 2302 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2303 "MSRIndex": "0x1a6,0x1a7", 2304 "MSRValue": "0x3F84000001", 2305 "Offcore": "1", 2306 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2307 "SampleAfterValue": "100003", 2308 "UMask": "0x1" 2309 }, 2310 { 2311 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2312 "Counter": "0,1,2,3", 2313 "CounterHTOff": "0,1,2,3", 2314 "EventCode": "0xB7, 0xBB", 2315 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2316 "MSRIndex": "0x1a6,0x1a7", 2317 "MSRValue": "0x1004000001", 2318 "Offcore": "1", 2319 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2320 "SampleAfterValue": "100003", 2321 "UMask": "0x1" 2322 }, 2323 { 2324 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2325 "Counter": "0,1,2,3", 2326 "CounterHTOff": "0,1,2,3", 2327 "EventCode": "0xB7, 0xBB", 2328 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2329 "MSRIndex": "0x1a6,0x1a7", 2330 "MSRValue": "0x0804000001", 2331 "Offcore": "1", 2332 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2333 "SampleAfterValue": "100003", 2334 "UMask": "0x1" 2335 }, 2336 { 2337 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2338 "Counter": "0,1,2,3", 2339 "CounterHTOff": "0,1,2,3", 2340 "EventCode": "0xB7, 0xBB", 2341 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2342 "MSRIndex": "0x1a6,0x1a7", 2343 "MSRValue": "0x0404000001", 2344 "Offcore": "1", 2345 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2346 "SampleAfterValue": "100003", 2347 "UMask": "0x1" 2348 }, 2349 { 2350 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2351 "Counter": "0,1,2,3", 2352 "CounterHTOff": "0,1,2,3", 2353 "EventCode": "0xB7, 0xBB", 2354 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2355 "MSRIndex": "0x1a6,0x1a7", 2356 "MSRValue": "0x0104000001", 2357 "Offcore": "1", 2358 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2359 "SampleAfterValue": "100003", 2360 "UMask": "0x1" 2361 }, 2362 { 2363 "BriefDescription": "Counts demand data reads", 2364 "Counter": "0,1,2,3", 2365 "CounterHTOff": "0,1,2,3", 2366 "EventCode": "0xB7, 0xBB", 2367 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2368 "MSRIndex": "0x1a6,0x1a7", 2369 "MSRValue": "0x0204000001", 2370 "Offcore": "1", 2371 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2372 "SampleAfterValue": "100003", 2373 "UMask": "0x1" 2374 }, 2375 { 2376 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 2377 "Counter": "0,1,2,3", 2378 "CounterHTOff": "0,1,2,3", 2379 "EventCode": "0xB7, 0xBB", 2380 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 2381 "MSRIndex": "0x1a6,0x1a7", 2382 "MSRValue": "0x0604000001", 2383 "Offcore": "1", 2384 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2385 "SampleAfterValue": "100003", 2386 "UMask": "0x1" 2387 }, 2388 { 2389 "BriefDescription": "Counts demand data reads", 2390 "Counter": "0,1,2,3", 2391 "CounterHTOff": "0,1,2,3", 2392 "EventCode": "0xB7, 0xBB", 2393 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2394 "MSRIndex": "0x1a6,0x1a7", 2395 "MSRValue": "0x0084000001", 2396 "Offcore": "1", 2397 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2398 "SampleAfterValue": "100003", 2399 "UMask": "0x1" 2400 }, 2401 { 2402 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 2403 "Counter": "0,1,2,3", 2404 "CounterHTOff": "0,1,2,3", 2405 "EventCode": "0xB7, 0xBB", 2406 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 2407 "MSRIndex": "0x1a6,0x1a7", 2408 "MSRValue": "0x063B800001", 2409 "Offcore": "1", 2410 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2411 "SampleAfterValue": "100003", 2412 "UMask": "0x1" 2413 }, 2414 { 2415 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2416 "Counter": "0,1,2,3", 2417 "CounterHTOff": "0,1,2,3", 2418 "EventCode": "0xB7, 0xBB", 2419 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2420 "MSRIndex": "0x1a6,0x1a7", 2421 "MSRValue": "0x3F90000001", 2422 "Offcore": "1", 2423 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2424 "SampleAfterValue": "100003", 2425 "UMask": "0x1" 2426 }, 2427 { 2428 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2429 "Counter": "0,1,2,3", 2430 "CounterHTOff": "0,1,2,3", 2431 "EventCode": "0xB7, 0xBB", 2432 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2433 "MSRIndex": "0x1a6,0x1a7", 2434 "MSRValue": "0x1010000001", 2435 "Offcore": "1", 2436 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2437 "SampleAfterValue": "100003", 2438 "UMask": "0x1" 2439 }, 2440 { 2441 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2442 "Counter": "0,1,2,3", 2443 "CounterHTOff": "0,1,2,3", 2444 "EventCode": "0xB7, 0xBB", 2445 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2446 "MSRIndex": "0x1a6,0x1a7", 2447 "MSRValue": "0x0810000001", 2448 "Offcore": "1", 2449 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2450 "SampleAfterValue": "100003", 2451 "UMask": "0x1" 2452 }, 2453 { 2454 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2455 "Counter": "0,1,2,3", 2456 "CounterHTOff": "0,1,2,3", 2457 "EventCode": "0xB7, 0xBB", 2458 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2459 "MSRIndex": "0x1a6,0x1a7", 2460 "MSRValue": "0x0410000001", 2461 "Offcore": "1", 2462 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2463 "SampleAfterValue": "100003", 2464 "UMask": "0x1" 2465 }, 2466 { 2467 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2468 "Counter": "0,1,2,3", 2469 "CounterHTOff": "0,1,2,3", 2470 "EventCode": "0xB7, 0xBB", 2471 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2472 "MSRIndex": "0x1a6,0x1a7", 2473 "MSRValue": "0x0110000001", 2474 "Offcore": "1", 2475 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2476 "SampleAfterValue": "100003", 2477 "UMask": "0x1" 2478 }, 2479 { 2480 "BriefDescription": "Counts demand data reads", 2481 "Counter": "0,1,2,3", 2482 "CounterHTOff": "0,1,2,3", 2483 "EventCode": "0xB7, 0xBB", 2484 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2485 "MSRIndex": "0x1a6,0x1a7", 2486 "MSRValue": "0x0210000001", 2487 "Offcore": "1", 2488 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2489 "SampleAfterValue": "100003", 2490 "UMask": "0x1" 2491 }, 2492 { 2493 "BriefDescription": "Counts demand data reads", 2494 "Counter": "0,1,2,3", 2495 "CounterHTOff": "0,1,2,3", 2496 "EventCode": "0xB7, 0xBB", 2497 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2498 "MSRIndex": "0x1a6,0x1a7", 2499 "MSRValue": "0x0090000001", 2500 "Offcore": "1", 2501 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2502 "SampleAfterValue": "100003", 2503 "UMask": "0x1" 2504 }, 2505 { 2506 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", 2507 "Counter": "0,1,2,3", 2508 "CounterHTOff": "0,1,2,3", 2509 "EventCode": "0xB7, 0xBB", 2510 "EventName": "OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", 2511 "MSRIndex": "0x1a6,0x1a7", 2512 "MSRValue": "0x3FBC000002", 2513 "Offcore": "1", 2514 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2515 "SampleAfterValue": "100003", 2516 "UMask": "0x1" 2517 }, 2518 { 2519 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", 2520 "Counter": "0,1,2,3", 2521 "CounterHTOff": "0,1,2,3", 2522 "EventCode": "0xB7, 0xBB", 2523 "EventName": "OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", 2524 "MSRIndex": "0x1a6,0x1a7", 2525 "MSRValue": "0x103C000002", 2526 "Offcore": "1", 2527 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2528 "SampleAfterValue": "100003", 2529 "UMask": "0x1" 2530 }, 2531 { 2532 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 2533 "Counter": "0,1,2,3", 2534 "CounterHTOff": "0,1,2,3", 2535 "EventCode": "0xB7, 0xBB", 2536 "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 2537 "MSRIndex": "0x1a6,0x1a7", 2538 "MSRValue": "0x083C000002", 2539 "Offcore": "1", 2540 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2541 "SampleAfterValue": "100003", 2542 "UMask": "0x1" 2543 }, 2544 { 2545 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2546 "Counter": "0,1,2,3", 2547 "CounterHTOff": "0,1,2,3", 2548 "EventCode": "0xB7, 0xBB", 2549 "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2550 "MSRIndex": "0x1a6,0x1a7", 2551 "MSRValue": "0x043C000002", 2552 "Offcore": "1", 2553 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2554 "SampleAfterValue": "100003", 2555 "UMask": "0x1" 2556 }, 2557 { 2558 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", 2559 "Counter": "0,1,2,3", 2560 "CounterHTOff": "0,1,2,3", 2561 "EventCode": "0xB7, 0xBB", 2562 "EventName": "OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", 2563 "MSRIndex": "0x1a6,0x1a7", 2564 "MSRValue": "0x013C000002", 2565 "Offcore": "1", 2566 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2567 "SampleAfterValue": "100003", 2568 "UMask": "0x1" 2569 }, 2570 { 2571 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", 2572 "Counter": "0,1,2,3", 2573 "CounterHTOff": "0,1,2,3", 2574 "EventCode": "0xB7, 0xBB", 2575 "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", 2576 "MSRIndex": "0x1a6,0x1a7", 2577 "MSRValue": "0x103FC00002", 2578 "Offcore": "1", 2579 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2580 "SampleAfterValue": "100003", 2581 "UMask": "0x1" 2582 }, 2583 { 2584 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 2585 "Counter": "0,1,2,3", 2586 "CounterHTOff": "0,1,2,3", 2587 "EventCode": "0xB7, 0xBB", 2588 "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 2589 "MSRIndex": "0x1a6,0x1a7", 2590 "MSRValue": "0x083FC00002", 2591 "Offcore": "1", 2592 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2593 "SampleAfterValue": "100003", 2594 "UMask": "0x1" 2595 }, 2596 { 2597 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", 2598 "Counter": "0,1,2,3", 2599 "CounterHTOff": "0,1,2,3", 2600 "EventCode": "0xB7, 0xBB", 2601 "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", 2602 "MSRIndex": "0x1a6,0x1a7", 2603 "MSRValue": "0x023C000002", 2604 "Offcore": "1", 2605 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2606 "SampleAfterValue": "100003", 2607 "UMask": "0x1" 2608 }, 2609 { 2610 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", 2611 "Counter": "0,1,2,3", 2612 "CounterHTOff": "0,1,2,3", 2613 "EventCode": "0xB7, 0xBB", 2614 "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", 2615 "MSRIndex": "0x1a6,0x1a7", 2616 "MSRValue": "0x00BC000002", 2617 "Offcore": "1", 2618 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2619 "SampleAfterValue": "100003", 2620 "UMask": "0x1" 2621 }, 2622 { 2623 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2624 "Counter": "0,1,2,3", 2625 "CounterHTOff": "0,1,2,3", 2626 "EventCode": "0xB7, 0xBB", 2627 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2628 "MSRIndex": "0x1a6,0x1a7", 2629 "MSRValue": "0x3F84000002", 2630 "Offcore": "1", 2631 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2632 "SampleAfterValue": "100003", 2633 "UMask": "0x1" 2634 }, 2635 { 2636 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2637 "Counter": "0,1,2,3", 2638 "CounterHTOff": "0,1,2,3", 2639 "EventCode": "0xB7, 0xBB", 2640 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2641 "MSRIndex": "0x1a6,0x1a7", 2642 "MSRValue": "0x1004000002", 2643 "Offcore": "1", 2644 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2645 "SampleAfterValue": "100003", 2646 "UMask": "0x1" 2647 }, 2648 { 2649 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2650 "Counter": "0,1,2,3", 2651 "CounterHTOff": "0,1,2,3", 2652 "EventCode": "0xB7, 0xBB", 2653 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2654 "MSRIndex": "0x1a6,0x1a7", 2655 "MSRValue": "0x0804000002", 2656 "Offcore": "1", 2657 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2658 "SampleAfterValue": "100003", 2659 "UMask": "0x1" 2660 }, 2661 { 2662 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2663 "Counter": "0,1,2,3", 2664 "CounterHTOff": "0,1,2,3", 2665 "EventCode": "0xB7, 0xBB", 2666 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2667 "MSRIndex": "0x1a6,0x1a7", 2668 "MSRValue": "0x0404000002", 2669 "Offcore": "1", 2670 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2671 "SampleAfterValue": "100003", 2672 "UMask": "0x1" 2673 }, 2674 { 2675 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2676 "Counter": "0,1,2,3", 2677 "CounterHTOff": "0,1,2,3", 2678 "EventCode": "0xB7, 0xBB", 2679 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 2680 "MSRIndex": "0x1a6,0x1a7", 2681 "MSRValue": "0x0104000002", 2682 "Offcore": "1", 2683 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2684 "SampleAfterValue": "100003", 2685 "UMask": "0x1" 2686 }, 2687 { 2688 "BriefDescription": "Counts all demand data writes (RFOs)", 2689 "Counter": "0,1,2,3", 2690 "CounterHTOff": "0,1,2,3", 2691 "EventCode": "0xB7, 0xBB", 2692 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 2693 "MSRIndex": "0x1a6,0x1a7", 2694 "MSRValue": "0x0204000002", 2695 "Offcore": "1", 2696 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2697 "SampleAfterValue": "100003", 2698 "UMask": "0x1" 2699 }, 2700 { 2701 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 2702 "Counter": "0,1,2,3", 2703 "CounterHTOff": "0,1,2,3", 2704 "EventCode": "0xB7, 0xBB", 2705 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 2706 "MSRIndex": "0x1a6,0x1a7", 2707 "MSRValue": "0x0604000002", 2708 "Offcore": "1", 2709 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2710 "SampleAfterValue": "100003", 2711 "UMask": "0x1" 2712 }, 2713 { 2714 "BriefDescription": "Counts all demand data writes (RFOs)", 2715 "Counter": "0,1,2,3", 2716 "CounterHTOff": "0,1,2,3", 2717 "EventCode": "0xB7, 0xBB", 2718 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 2719 "MSRIndex": "0x1a6,0x1a7", 2720 "MSRValue": "0x0084000002", 2721 "Offcore": "1", 2722 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2723 "SampleAfterValue": "100003", 2724 "UMask": "0x1" 2725 }, 2726 { 2727 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 2728 "Counter": "0,1,2,3", 2729 "CounterHTOff": "0,1,2,3", 2730 "EventCode": "0xB7, 0xBB", 2731 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 2732 "MSRIndex": "0x1a6,0x1a7", 2733 "MSRValue": "0x063B800002", 2734 "Offcore": "1", 2735 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2736 "SampleAfterValue": "100003", 2737 "UMask": "0x1" 2738 }, 2739 { 2740 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2741 "Counter": "0,1,2,3", 2742 "CounterHTOff": "0,1,2,3", 2743 "EventCode": "0xB7, 0xBB", 2744 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 2745 "MSRIndex": "0x1a6,0x1a7", 2746 "MSRValue": "0x3F90000002", 2747 "Offcore": "1", 2748 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2749 "SampleAfterValue": "100003", 2750 "UMask": "0x1" 2751 }, 2752 { 2753 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2754 "Counter": "0,1,2,3", 2755 "CounterHTOff": "0,1,2,3", 2756 "EventCode": "0xB7, 0xBB", 2757 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 2758 "MSRIndex": "0x1a6,0x1a7", 2759 "MSRValue": "0x1010000002", 2760 "Offcore": "1", 2761 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2762 "SampleAfterValue": "100003", 2763 "UMask": "0x1" 2764 }, 2765 { 2766 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2767 "Counter": "0,1,2,3", 2768 "CounterHTOff": "0,1,2,3", 2769 "EventCode": "0xB7, 0xBB", 2770 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 2771 "MSRIndex": "0x1a6,0x1a7", 2772 "MSRValue": "0x0810000002", 2773 "Offcore": "1", 2774 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2775 "SampleAfterValue": "100003", 2776 "UMask": "0x1" 2777 }, 2778 { 2779 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2780 "Counter": "0,1,2,3", 2781 "CounterHTOff": "0,1,2,3", 2782 "EventCode": "0xB7, 0xBB", 2783 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 2784 "MSRIndex": "0x1a6,0x1a7", 2785 "MSRValue": "0x0410000002", 2786 "Offcore": "1", 2787 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2788 "SampleAfterValue": "100003", 2789 "UMask": "0x1" 2790 }, 2791 { 2792 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2793 "Counter": "0,1,2,3", 2794 "CounterHTOff": "0,1,2,3", 2795 "EventCode": "0xB7, 0xBB", 2796 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 2797 "MSRIndex": "0x1a6,0x1a7", 2798 "MSRValue": "0x0110000002", 2799 "Offcore": "1", 2800 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2801 "SampleAfterValue": "100003", 2802 "UMask": "0x1" 2803 }, 2804 { 2805 "BriefDescription": "Counts all demand data writes (RFOs)", 2806 "Counter": "0,1,2,3", 2807 "CounterHTOff": "0,1,2,3", 2808 "EventCode": "0xB7, 0xBB", 2809 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 2810 "MSRIndex": "0x1a6,0x1a7", 2811 "MSRValue": "0x0210000002", 2812 "Offcore": "1", 2813 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2814 "SampleAfterValue": "100003", 2815 "UMask": "0x1" 2816 }, 2817 { 2818 "BriefDescription": "Counts all demand data writes (RFOs)", 2819 "Counter": "0,1,2,3", 2820 "CounterHTOff": "0,1,2,3", 2821 "EventCode": "0xB7, 0xBB", 2822 "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 2823 "MSRIndex": "0x1a6,0x1a7", 2824 "MSRValue": "0x0090000002", 2825 "Offcore": "1", 2826 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2827 "SampleAfterValue": "100003", 2828 "UMask": "0x1" 2829 }, 2830 { 2831 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.ANY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOP", 2832 "Counter": "0,1,2,3", 2833 "CounterHTOff": "0,1,2,3", 2834 "EventCode": "0xB7, 0xBB", 2835 "EventName": "OCR.OTHER.L3_MISS.ANY_SNOOP", 2836 "MSRIndex": "0x1a6,0x1a7", 2837 "MSRValue": "0x3FBC008000", 2838 "Offcore": "1", 2839 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2840 "SampleAfterValue": "100003", 2841 "UMask": "0x1" 2842 }, 2843 { 2844 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_CORE", 2845 "Counter": "0,1,2,3", 2846 "CounterHTOff": "0,1,2,3", 2847 "EventCode": "0xB7, 0xBB", 2848 "EventName": "OCR.OTHER.L3_MISS.HITM_OTHER_CORE", 2849 "MSRIndex": "0x1a6,0x1a7", 2850 "MSRValue": "0x103C008000", 2851 "Offcore": "1", 2852 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2853 "SampleAfterValue": "100003", 2854 "UMask": "0x1" 2855 }, 2856 { 2857 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", 2858 "Counter": "0,1,2,3", 2859 "CounterHTOff": "0,1,2,3", 2860 "EventCode": "0xB7, 0xBB", 2861 "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", 2862 "MSRIndex": "0x1a6,0x1a7", 2863 "MSRValue": "0x083C008000", 2864 "Offcore": "1", 2865 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2866 "SampleAfterValue": "100003", 2867 "UMask": "0x1" 2868 }, 2869 { 2870 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2871 "Counter": "0,1,2,3", 2872 "CounterHTOff": "0,1,2,3", 2873 "EventCode": "0xB7, 0xBB", 2874 "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", 2875 "MSRIndex": "0x1a6,0x1a7", 2876 "MSRValue": "0x043C008000", 2877 "Offcore": "1", 2878 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2879 "SampleAfterValue": "100003", 2880 "UMask": "0x1" 2881 }, 2882 { 2883 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", 2884 "Counter": "0,1,2,3", 2885 "CounterHTOff": "0,1,2,3", 2886 "EventCode": "0xB7, 0xBB", 2887 "EventName": "OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", 2888 "MSRIndex": "0x1a6,0x1a7", 2889 "MSRValue": "0x013C008000", 2890 "Offcore": "1", 2891 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2892 "SampleAfterValue": "100003", 2893 "UMask": "0x1" 2894 }, 2895 { 2896 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HITM", 2897 "Counter": "0,1,2,3", 2898 "CounterHTOff": "0,1,2,3", 2899 "EventCode": "0xB7, 0xBB", 2900 "EventName": "OCR.OTHER.L3_MISS.REMOTE_HITM", 2901 "MSRIndex": "0x1a6,0x1a7", 2902 "MSRValue": "0x103FC08000", 2903 "Offcore": "1", 2904 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2905 "SampleAfterValue": "100003", 2906 "UMask": "0x1" 2907 }, 2908 { 2909 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", 2910 "Counter": "0,1,2,3", 2911 "CounterHTOff": "0,1,2,3", 2912 "EventCode": "0xB7, 0xBB", 2913 "EventName": "OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", 2914 "MSRIndex": "0x1a6,0x1a7", 2915 "MSRValue": "0x083FC08000", 2916 "Offcore": "1", 2917 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2918 "SampleAfterValue": "100003", 2919 "UMask": "0x1" 2920 }, 2921 { 2922 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.SNOOP_MISS", 2923 "Counter": "0,1,2,3", 2924 "CounterHTOff": "0,1,2,3", 2925 "EventCode": "0xB7, 0xBB", 2926 "EventName": "OCR.OTHER.L3_MISS.SNOOP_MISS", 2927 "MSRIndex": "0x1a6,0x1a7", 2928 "MSRValue": "0x023C008000", 2929 "Offcore": "1", 2930 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2931 "SampleAfterValue": "100003", 2932 "UMask": "0x1" 2933 }, 2934 { 2935 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.SNOOP_NONE", 2936 "Counter": "0,1,2,3", 2937 "CounterHTOff": "0,1,2,3", 2938 "EventCode": "0xB7, 0xBB", 2939 "EventName": "OCR.OTHER.L3_MISS.SNOOP_NONE", 2940 "MSRIndex": "0x1a6,0x1a7", 2941 "MSRValue": "0x00BC008000", 2942 "Offcore": "1", 2943 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2944 "SampleAfterValue": "100003", 2945 "UMask": "0x1" 2946 }, 2947 { 2948 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2949 "Counter": "0,1,2,3", 2950 "CounterHTOff": "0,1,2,3", 2951 "EventCode": "0xB7, 0xBB", 2952 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 2953 "MSRIndex": "0x1a6,0x1a7", 2954 "MSRValue": "0x3F84008000", 2955 "Offcore": "1", 2956 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2957 "SampleAfterValue": "100003", 2958 "UMask": "0x1" 2959 }, 2960 { 2961 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2962 "Counter": "0,1,2,3", 2963 "CounterHTOff": "0,1,2,3", 2964 "EventCode": "0xB7, 0xBB", 2965 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 2966 "MSRIndex": "0x1a6,0x1a7", 2967 "MSRValue": "0x1004008000", 2968 "Offcore": "1", 2969 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2970 "SampleAfterValue": "100003", 2971 "UMask": "0x1" 2972 }, 2973 { 2974 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2975 "Counter": "0,1,2,3", 2976 "CounterHTOff": "0,1,2,3", 2977 "EventCode": "0xB7, 0xBB", 2978 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 2979 "MSRIndex": "0x1a6,0x1a7", 2980 "MSRValue": "0x0804008000", 2981 "Offcore": "1", 2982 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2983 "SampleAfterValue": "100003", 2984 "UMask": "0x1" 2985 }, 2986 { 2987 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2988 "Counter": "0,1,2,3", 2989 "CounterHTOff": "0,1,2,3", 2990 "EventCode": "0xB7, 0xBB", 2991 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 2992 "MSRIndex": "0x1a6,0x1a7", 2993 "MSRValue": "0x0404008000", 2994 "Offcore": "1", 2995 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2996 "SampleAfterValue": "100003", 2997 "UMask": "0x1" 2998 }, 2999 { 3000 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3001 "Counter": "0,1,2,3", 3002 "CounterHTOff": "0,1,2,3", 3003 "EventCode": "0xB7, 0xBB", 3004 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3005 "MSRIndex": "0x1a6,0x1a7", 3006 "MSRValue": "0x0104008000", 3007 "Offcore": "1", 3008 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3009 "SampleAfterValue": "100003", 3010 "UMask": "0x1" 3011 }, 3012 { 3013 "BriefDescription": "Counts any other requests", 3014 "Counter": "0,1,2,3", 3015 "CounterHTOff": "0,1,2,3", 3016 "EventCode": "0xB7, 0xBB", 3017 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3018 "MSRIndex": "0x1a6,0x1a7", 3019 "MSRValue": "0x0204008000", 3020 "Offcore": "1", 3021 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3022 "SampleAfterValue": "100003", 3023 "UMask": "0x1" 3024 }, 3025 { 3026 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 3027 "Counter": "0,1,2,3", 3028 "CounterHTOff": "0,1,2,3", 3029 "EventCode": "0xB7, 0xBB", 3030 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 3031 "MSRIndex": "0x1a6,0x1a7", 3032 "MSRValue": "0x0604008000", 3033 "Offcore": "1", 3034 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3035 "SampleAfterValue": "100003", 3036 "UMask": "0x1" 3037 }, 3038 { 3039 "BriefDescription": "Counts any other requests", 3040 "Counter": "0,1,2,3", 3041 "CounterHTOff": "0,1,2,3", 3042 "EventCode": "0xB7, 0xBB", 3043 "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3044 "MSRIndex": "0x1a6,0x1a7", 3045 "MSRValue": "0x0084008000", 3046 "Offcore": "1", 3047 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3048 "SampleAfterValue": "100003", 3049 "UMask": "0x1" 3050 }, 3051 { 3052 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 3053 "Counter": "0,1,2,3", 3054 "CounterHTOff": "0,1,2,3", 3055 "EventCode": "0xB7, 0xBB", 3056 "EventName": "OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 3057 "MSRIndex": "0x1a6,0x1a7", 3058 "MSRValue": "0x063B808000", 3059 "Offcore": "1", 3060 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3061 "SampleAfterValue": "100003", 3062 "UMask": "0x1" 3063 }, 3064 { 3065 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3066 "Counter": "0,1,2,3", 3067 "CounterHTOff": "0,1,2,3", 3068 "EventCode": "0xB7, 0xBB", 3069 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3070 "MSRIndex": "0x1a6,0x1a7", 3071 "MSRValue": "0x3F90008000", 3072 "Offcore": "1", 3073 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3074 "SampleAfterValue": "100003", 3075 "UMask": "0x1" 3076 }, 3077 { 3078 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3079 "Counter": "0,1,2,3", 3080 "CounterHTOff": "0,1,2,3", 3081 "EventCode": "0xB7, 0xBB", 3082 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3083 "MSRIndex": "0x1a6,0x1a7", 3084 "MSRValue": "0x1010008000", 3085 "Offcore": "1", 3086 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3087 "SampleAfterValue": "100003", 3088 "UMask": "0x1" 3089 }, 3090 { 3091 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3092 "Counter": "0,1,2,3", 3093 "CounterHTOff": "0,1,2,3", 3094 "EventCode": "0xB7, 0xBB", 3095 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3096 "MSRIndex": "0x1a6,0x1a7", 3097 "MSRValue": "0x0810008000", 3098 "Offcore": "1", 3099 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3100 "SampleAfterValue": "100003", 3101 "UMask": "0x1" 3102 }, 3103 { 3104 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3105 "Counter": "0,1,2,3", 3106 "CounterHTOff": "0,1,2,3", 3107 "EventCode": "0xB7, 0xBB", 3108 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3109 "MSRIndex": "0x1a6,0x1a7", 3110 "MSRValue": "0x0410008000", 3111 "Offcore": "1", 3112 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3113 "SampleAfterValue": "100003", 3114 "UMask": "0x1" 3115 }, 3116 { 3117 "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3118 "Counter": "0,1,2,3", 3119 "CounterHTOff": "0,1,2,3", 3120 "EventCode": "0xB7, 0xBB", 3121 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3122 "MSRIndex": "0x1a6,0x1a7", 3123 "MSRValue": "0x0110008000", 3124 "Offcore": "1", 3125 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3126 "SampleAfterValue": "100003", 3127 "UMask": "0x1" 3128 }, 3129 { 3130 "BriefDescription": "Counts any other requests", 3131 "Counter": "0,1,2,3", 3132 "CounterHTOff": "0,1,2,3", 3133 "EventCode": "0xB7, 0xBB", 3134 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3135 "MSRIndex": "0x1a6,0x1a7", 3136 "MSRValue": "0x0210008000", 3137 "Offcore": "1", 3138 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3139 "SampleAfterValue": "100003", 3140 "UMask": "0x1" 3141 }, 3142 { 3143 "BriefDescription": "Counts any other requests", 3144 "Counter": "0,1,2,3", 3145 "CounterHTOff": "0,1,2,3", 3146 "EventCode": "0xB7, 0xBB", 3147 "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3148 "MSRIndex": "0x1a6,0x1a7", 3149 "MSRValue": "0x0090008000", 3150 "Offcore": "1", 3151 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3152 "SampleAfterValue": "100003", 3153 "UMask": "0x1" 3154 }, 3155 { 3156 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 3157 "Counter": "0,1,2,3", 3158 "CounterHTOff": "0,1,2,3", 3159 "EventCode": "0xB7, 0xBB", 3160 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 3161 "MSRIndex": "0x1a6,0x1a7", 3162 "MSRValue": "0x3FBC000400", 3163 "Offcore": "1", 3164 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3165 "SampleAfterValue": "100003", 3166 "UMask": "0x1" 3167 }, 3168 { 3169 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", 3170 "Counter": "0,1,2,3", 3171 "CounterHTOff": "0,1,2,3", 3172 "EventCode": "0xB7, 0xBB", 3173 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", 3174 "MSRIndex": "0x1a6,0x1a7", 3175 "MSRValue": "0x103C000400", 3176 "Offcore": "1", 3177 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3178 "SampleAfterValue": "100003", 3179 "UMask": "0x1" 3180 }, 3181 { 3182 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", 3183 "Counter": "0,1,2,3", 3184 "CounterHTOff": "0,1,2,3", 3185 "EventCode": "0xB7, 0xBB", 3186 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", 3187 "MSRIndex": "0x1a6,0x1a7", 3188 "MSRValue": "0x083C000400", 3189 "Offcore": "1", 3190 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3191 "SampleAfterValue": "100003", 3192 "UMask": "0x1" 3193 }, 3194 { 3195 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3196 "Counter": "0,1,2,3", 3197 "CounterHTOff": "0,1,2,3", 3198 "EventCode": "0xB7, 0xBB", 3199 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3200 "MSRIndex": "0x1a6,0x1a7", 3201 "MSRValue": "0x043C000400", 3202 "Offcore": "1", 3203 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3204 "SampleAfterValue": "100003", 3205 "UMask": "0x1" 3206 }, 3207 { 3208 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", 3209 "Counter": "0,1,2,3", 3210 "CounterHTOff": "0,1,2,3", 3211 "EventCode": "0xB7, 0xBB", 3212 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", 3213 "MSRIndex": "0x1a6,0x1a7", 3214 "MSRValue": "0x013C000400", 3215 "Offcore": "1", 3216 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3217 "SampleAfterValue": "100003", 3218 "UMask": "0x1" 3219 }, 3220 { 3221 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 3222 "Counter": "0,1,2,3", 3223 "CounterHTOff": "0,1,2,3", 3224 "EventCode": "0xB7, 0xBB", 3225 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 3226 "MSRIndex": "0x1a6,0x1a7", 3227 "MSRValue": "0x103FC00400", 3228 "Offcore": "1", 3229 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3230 "SampleAfterValue": "100003", 3231 "UMask": "0x1" 3232 }, 3233 { 3234 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 3235 "Counter": "0,1,2,3", 3236 "CounterHTOff": "0,1,2,3", 3237 "EventCode": "0xB7, 0xBB", 3238 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 3239 "MSRIndex": "0x1a6,0x1a7", 3240 "MSRValue": "0x083FC00400", 3241 "Offcore": "1", 3242 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3243 "SampleAfterValue": "100003", 3244 "UMask": "0x1" 3245 }, 3246 { 3247 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", 3248 "Counter": "0,1,2,3", 3249 "CounterHTOff": "0,1,2,3", 3250 "EventCode": "0xB7, 0xBB", 3251 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", 3252 "MSRIndex": "0x1a6,0x1a7", 3253 "MSRValue": "0x023C000400", 3254 "Offcore": "1", 3255 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3256 "SampleAfterValue": "100003", 3257 "UMask": "0x1" 3258 }, 3259 { 3260 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", 3261 "Counter": "0,1,2,3", 3262 "CounterHTOff": "0,1,2,3", 3263 "EventCode": "0xB7, 0xBB", 3264 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", 3265 "MSRIndex": "0x1a6,0x1a7", 3266 "MSRValue": "0x00BC000400", 3267 "Offcore": "1", 3268 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3269 "SampleAfterValue": "100003", 3270 "UMask": "0x1" 3271 }, 3272 { 3273 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3274 "Counter": "0,1,2,3", 3275 "CounterHTOff": "0,1,2,3", 3276 "EventCode": "0xB7, 0xBB", 3277 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3278 "MSRIndex": "0x1a6,0x1a7", 3279 "MSRValue": "0x3F84000400", 3280 "Offcore": "1", 3281 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3282 "SampleAfterValue": "100003", 3283 "UMask": "0x1" 3284 }, 3285 { 3286 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3287 "Counter": "0,1,2,3", 3288 "CounterHTOff": "0,1,2,3", 3289 "EventCode": "0xB7, 0xBB", 3290 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3291 "MSRIndex": "0x1a6,0x1a7", 3292 "MSRValue": "0x1004000400", 3293 "Offcore": "1", 3294 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3295 "SampleAfterValue": "100003", 3296 "UMask": "0x1" 3297 }, 3298 { 3299 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3300 "Counter": "0,1,2,3", 3301 "CounterHTOff": "0,1,2,3", 3302 "EventCode": "0xB7, 0xBB", 3303 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3304 "MSRIndex": "0x1a6,0x1a7", 3305 "MSRValue": "0x0804000400", 3306 "Offcore": "1", 3307 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3308 "SampleAfterValue": "100003", 3309 "UMask": "0x1" 3310 }, 3311 { 3312 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3313 "Counter": "0,1,2,3", 3314 "CounterHTOff": "0,1,2,3", 3315 "EventCode": "0xB7, 0xBB", 3316 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3317 "MSRIndex": "0x1a6,0x1a7", 3318 "MSRValue": "0x0404000400", 3319 "Offcore": "1", 3320 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3321 "SampleAfterValue": "100003", 3322 "UMask": "0x1" 3323 }, 3324 { 3325 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3326 "Counter": "0,1,2,3", 3327 "CounterHTOff": "0,1,2,3", 3328 "EventCode": "0xB7, 0xBB", 3329 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3330 "MSRIndex": "0x1a6,0x1a7", 3331 "MSRValue": "0x0104000400", 3332 "Offcore": "1", 3333 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3334 "SampleAfterValue": "100003", 3335 "UMask": "0x1" 3336 }, 3337 { 3338 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 3339 "Counter": "0,1,2,3", 3340 "CounterHTOff": "0,1,2,3", 3341 "EventCode": "0xB7, 0xBB", 3342 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3343 "MSRIndex": "0x1a6,0x1a7", 3344 "MSRValue": "0x0204000400", 3345 "Offcore": "1", 3346 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3347 "SampleAfterValue": "100003", 3348 "UMask": "0x1" 3349 }, 3350 { 3351 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 3352 "Counter": "0,1,2,3", 3353 "CounterHTOff": "0,1,2,3", 3354 "EventCode": "0xB7, 0xBB", 3355 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 3356 "MSRIndex": "0x1a6,0x1a7", 3357 "MSRValue": "0x0604000400", 3358 "Offcore": "1", 3359 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3360 "SampleAfterValue": "100003", 3361 "UMask": "0x1" 3362 }, 3363 { 3364 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 3365 "Counter": "0,1,2,3", 3366 "CounterHTOff": "0,1,2,3", 3367 "EventCode": "0xB7, 0xBB", 3368 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3369 "MSRIndex": "0x1a6,0x1a7", 3370 "MSRValue": "0x0084000400", 3371 "Offcore": "1", 3372 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3373 "SampleAfterValue": "100003", 3374 "UMask": "0x1" 3375 }, 3376 { 3377 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 3378 "Counter": "0,1,2,3", 3379 "CounterHTOff": "0,1,2,3", 3380 "EventCode": "0xB7, 0xBB", 3381 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 3382 "MSRIndex": "0x1a6,0x1a7", 3383 "MSRValue": "0x063B800400", 3384 "Offcore": "1", 3385 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3386 "SampleAfterValue": "100003", 3387 "UMask": "0x1" 3388 }, 3389 { 3390 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3391 "Counter": "0,1,2,3", 3392 "CounterHTOff": "0,1,2,3", 3393 "EventCode": "0xB7, 0xBB", 3394 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3395 "MSRIndex": "0x1a6,0x1a7", 3396 "MSRValue": "0x3F90000400", 3397 "Offcore": "1", 3398 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3399 "SampleAfterValue": "100003", 3400 "UMask": "0x1" 3401 }, 3402 { 3403 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3404 "Counter": "0,1,2,3", 3405 "CounterHTOff": "0,1,2,3", 3406 "EventCode": "0xB7, 0xBB", 3407 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3408 "MSRIndex": "0x1a6,0x1a7", 3409 "MSRValue": "0x1010000400", 3410 "Offcore": "1", 3411 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3412 "SampleAfterValue": "100003", 3413 "UMask": "0x1" 3414 }, 3415 { 3416 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3417 "Counter": "0,1,2,3", 3418 "CounterHTOff": "0,1,2,3", 3419 "EventCode": "0xB7, 0xBB", 3420 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3421 "MSRIndex": "0x1a6,0x1a7", 3422 "MSRValue": "0x0810000400", 3423 "Offcore": "1", 3424 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3425 "SampleAfterValue": "100003", 3426 "UMask": "0x1" 3427 }, 3428 { 3429 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3430 "Counter": "0,1,2,3", 3431 "CounterHTOff": "0,1,2,3", 3432 "EventCode": "0xB7, 0xBB", 3433 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3434 "MSRIndex": "0x1a6,0x1a7", 3435 "MSRValue": "0x0410000400", 3436 "Offcore": "1", 3437 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3438 "SampleAfterValue": "100003", 3439 "UMask": "0x1" 3440 }, 3441 { 3442 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3443 "Counter": "0,1,2,3", 3444 "CounterHTOff": "0,1,2,3", 3445 "EventCode": "0xB7, 0xBB", 3446 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3447 "MSRIndex": "0x1a6,0x1a7", 3448 "MSRValue": "0x0110000400", 3449 "Offcore": "1", 3450 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3451 "SampleAfterValue": "100003", 3452 "UMask": "0x1" 3453 }, 3454 { 3455 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 3456 "Counter": "0,1,2,3", 3457 "CounterHTOff": "0,1,2,3", 3458 "EventCode": "0xB7, 0xBB", 3459 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3460 "MSRIndex": "0x1a6,0x1a7", 3461 "MSRValue": "0x0210000400", 3462 "Offcore": "1", 3463 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3464 "SampleAfterValue": "100003", 3465 "UMask": "0x1" 3466 }, 3467 { 3468 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 3469 "Counter": "0,1,2,3", 3470 "CounterHTOff": "0,1,2,3", 3471 "EventCode": "0xB7, 0xBB", 3472 "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3473 "MSRIndex": "0x1a6,0x1a7", 3474 "MSRValue": "0x0090000400", 3475 "Offcore": "1", 3476 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3477 "SampleAfterValue": "100003", 3478 "UMask": "0x1" 3479 }, 3480 { 3481 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 3482 "Counter": "0,1,2,3", 3483 "CounterHTOff": "0,1,2,3", 3484 "EventCode": "0xB7, 0xBB", 3485 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 3486 "MSRIndex": "0x1a6,0x1a7", 3487 "MSRValue": "0x3FBC000010", 3488 "Offcore": "1", 3489 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3490 "SampleAfterValue": "100003", 3491 "UMask": "0x1" 3492 }, 3493 { 3494 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", 3495 "Counter": "0,1,2,3", 3496 "CounterHTOff": "0,1,2,3", 3497 "EventCode": "0xB7, 0xBB", 3498 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", 3499 "MSRIndex": "0x1a6,0x1a7", 3500 "MSRValue": "0x103C000010", 3501 "Offcore": "1", 3502 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3503 "SampleAfterValue": "100003", 3504 "UMask": "0x1" 3505 }, 3506 { 3507 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 3508 "Counter": "0,1,2,3", 3509 "CounterHTOff": "0,1,2,3", 3510 "EventCode": "0xB7, 0xBB", 3511 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 3512 "MSRIndex": "0x1a6,0x1a7", 3513 "MSRValue": "0x083C000010", 3514 "Offcore": "1", 3515 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3516 "SampleAfterValue": "100003", 3517 "UMask": "0x1" 3518 }, 3519 { 3520 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3521 "Counter": "0,1,2,3", 3522 "CounterHTOff": "0,1,2,3", 3523 "EventCode": "0xB7, 0xBB", 3524 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3525 "MSRIndex": "0x1a6,0x1a7", 3526 "MSRValue": "0x043C000010", 3527 "Offcore": "1", 3528 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3529 "SampleAfterValue": "100003", 3530 "UMask": "0x1" 3531 }, 3532 { 3533 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 3534 "Counter": "0,1,2,3", 3535 "CounterHTOff": "0,1,2,3", 3536 "EventCode": "0xB7, 0xBB", 3537 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 3538 "MSRIndex": "0x1a6,0x1a7", 3539 "MSRValue": "0x013C000010", 3540 "Offcore": "1", 3541 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3542 "SampleAfterValue": "100003", 3543 "UMask": "0x1" 3544 }, 3545 { 3546 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 3547 "Counter": "0,1,2,3", 3548 "CounterHTOff": "0,1,2,3", 3549 "EventCode": "0xB7, 0xBB", 3550 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 3551 "MSRIndex": "0x1a6,0x1a7", 3552 "MSRValue": "0x103FC00010", 3553 "Offcore": "1", 3554 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3555 "SampleAfterValue": "100003", 3556 "UMask": "0x1" 3557 }, 3558 { 3559 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 3560 "Counter": "0,1,2,3", 3561 "CounterHTOff": "0,1,2,3", 3562 "EventCode": "0xB7, 0xBB", 3563 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 3564 "MSRIndex": "0x1a6,0x1a7", 3565 "MSRValue": "0x083FC00010", 3566 "Offcore": "1", 3567 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3568 "SampleAfterValue": "100003", 3569 "UMask": "0x1" 3570 }, 3571 { 3572 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", 3573 "Counter": "0,1,2,3", 3574 "CounterHTOff": "0,1,2,3", 3575 "EventCode": "0xB7, 0xBB", 3576 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", 3577 "MSRIndex": "0x1a6,0x1a7", 3578 "MSRValue": "0x023C000010", 3579 "Offcore": "1", 3580 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3581 "SampleAfterValue": "100003", 3582 "UMask": "0x1" 3583 }, 3584 { 3585 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", 3586 "Counter": "0,1,2,3", 3587 "CounterHTOff": "0,1,2,3", 3588 "EventCode": "0xB7, 0xBB", 3589 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", 3590 "MSRIndex": "0x1a6,0x1a7", 3591 "MSRValue": "0x00BC000010", 3592 "Offcore": "1", 3593 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3594 "SampleAfterValue": "100003", 3595 "UMask": "0x1" 3596 }, 3597 { 3598 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3599 "Counter": "0,1,2,3", 3600 "CounterHTOff": "0,1,2,3", 3601 "EventCode": "0xB7, 0xBB", 3602 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3603 "MSRIndex": "0x1a6,0x1a7", 3604 "MSRValue": "0x3F84000010", 3605 "Offcore": "1", 3606 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3607 "SampleAfterValue": "100003", 3608 "UMask": "0x1" 3609 }, 3610 { 3611 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3612 "Counter": "0,1,2,3", 3613 "CounterHTOff": "0,1,2,3", 3614 "EventCode": "0xB7, 0xBB", 3615 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3616 "MSRIndex": "0x1a6,0x1a7", 3617 "MSRValue": "0x1004000010", 3618 "Offcore": "1", 3619 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3620 "SampleAfterValue": "100003", 3621 "UMask": "0x1" 3622 }, 3623 { 3624 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3625 "Counter": "0,1,2,3", 3626 "CounterHTOff": "0,1,2,3", 3627 "EventCode": "0xB7, 0xBB", 3628 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3629 "MSRIndex": "0x1a6,0x1a7", 3630 "MSRValue": "0x0804000010", 3631 "Offcore": "1", 3632 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3633 "SampleAfterValue": "100003", 3634 "UMask": "0x1" 3635 }, 3636 { 3637 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3638 "Counter": "0,1,2,3", 3639 "CounterHTOff": "0,1,2,3", 3640 "EventCode": "0xB7, 0xBB", 3641 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3642 "MSRIndex": "0x1a6,0x1a7", 3643 "MSRValue": "0x0404000010", 3644 "Offcore": "1", 3645 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3646 "SampleAfterValue": "100003", 3647 "UMask": "0x1" 3648 }, 3649 { 3650 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3651 "Counter": "0,1,2,3", 3652 "CounterHTOff": "0,1,2,3", 3653 "EventCode": "0xB7, 0xBB", 3654 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3655 "MSRIndex": "0x1a6,0x1a7", 3656 "MSRValue": "0x0104000010", 3657 "Offcore": "1", 3658 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3659 "SampleAfterValue": "100003", 3660 "UMask": "0x1" 3661 }, 3662 { 3663 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 3664 "Counter": "0,1,2,3", 3665 "CounterHTOff": "0,1,2,3", 3666 "EventCode": "0xB7, 0xBB", 3667 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3668 "MSRIndex": "0x1a6,0x1a7", 3669 "MSRValue": "0x0204000010", 3670 "Offcore": "1", 3671 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3672 "SampleAfterValue": "100003", 3673 "UMask": "0x1" 3674 }, 3675 { 3676 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 3677 "Counter": "0,1,2,3", 3678 "CounterHTOff": "0,1,2,3", 3679 "EventCode": "0xB7, 0xBB", 3680 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 3681 "MSRIndex": "0x1a6,0x1a7", 3682 "MSRValue": "0x0604000010", 3683 "Offcore": "1", 3684 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3685 "SampleAfterValue": "100003", 3686 "UMask": "0x1" 3687 }, 3688 { 3689 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 3690 "Counter": "0,1,2,3", 3691 "CounterHTOff": "0,1,2,3", 3692 "EventCode": "0xB7, 0xBB", 3693 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 3694 "MSRIndex": "0x1a6,0x1a7", 3695 "MSRValue": "0x0084000010", 3696 "Offcore": "1", 3697 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3698 "SampleAfterValue": "100003", 3699 "UMask": "0x1" 3700 }, 3701 { 3702 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 3703 "Counter": "0,1,2,3", 3704 "CounterHTOff": "0,1,2,3", 3705 "EventCode": "0xB7, 0xBB", 3706 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 3707 "MSRIndex": "0x1a6,0x1a7", 3708 "MSRValue": "0x063B800010", 3709 "Offcore": "1", 3710 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3711 "SampleAfterValue": "100003", 3712 "UMask": "0x1" 3713 }, 3714 { 3715 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3716 "Counter": "0,1,2,3", 3717 "CounterHTOff": "0,1,2,3", 3718 "EventCode": "0xB7, 0xBB", 3719 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 3720 "MSRIndex": "0x1a6,0x1a7", 3721 "MSRValue": "0x3F90000010", 3722 "Offcore": "1", 3723 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3724 "SampleAfterValue": "100003", 3725 "UMask": "0x1" 3726 }, 3727 { 3728 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3729 "Counter": "0,1,2,3", 3730 "CounterHTOff": "0,1,2,3", 3731 "EventCode": "0xB7, 0xBB", 3732 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 3733 "MSRIndex": "0x1a6,0x1a7", 3734 "MSRValue": "0x1010000010", 3735 "Offcore": "1", 3736 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3737 "SampleAfterValue": "100003", 3738 "UMask": "0x1" 3739 }, 3740 { 3741 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3742 "Counter": "0,1,2,3", 3743 "CounterHTOff": "0,1,2,3", 3744 "EventCode": "0xB7, 0xBB", 3745 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 3746 "MSRIndex": "0x1a6,0x1a7", 3747 "MSRValue": "0x0810000010", 3748 "Offcore": "1", 3749 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3750 "SampleAfterValue": "100003", 3751 "UMask": "0x1" 3752 }, 3753 { 3754 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3755 "Counter": "0,1,2,3", 3756 "CounterHTOff": "0,1,2,3", 3757 "EventCode": "0xB7, 0xBB", 3758 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 3759 "MSRIndex": "0x1a6,0x1a7", 3760 "MSRValue": "0x0410000010", 3761 "Offcore": "1", 3762 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3763 "SampleAfterValue": "100003", 3764 "UMask": "0x1" 3765 }, 3766 { 3767 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3768 "Counter": "0,1,2,3", 3769 "CounterHTOff": "0,1,2,3", 3770 "EventCode": "0xB7, 0xBB", 3771 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 3772 "MSRIndex": "0x1a6,0x1a7", 3773 "MSRValue": "0x0110000010", 3774 "Offcore": "1", 3775 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3776 "SampleAfterValue": "100003", 3777 "UMask": "0x1" 3778 }, 3779 { 3780 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 3781 "Counter": "0,1,2,3", 3782 "CounterHTOff": "0,1,2,3", 3783 "EventCode": "0xB7, 0xBB", 3784 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 3785 "MSRIndex": "0x1a6,0x1a7", 3786 "MSRValue": "0x0210000010", 3787 "Offcore": "1", 3788 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3789 "SampleAfterValue": "100003", 3790 "UMask": "0x1" 3791 }, 3792 { 3793 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 3794 "Counter": "0,1,2,3", 3795 "CounterHTOff": "0,1,2,3", 3796 "EventCode": "0xB7, 0xBB", 3797 "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 3798 "MSRIndex": "0x1a6,0x1a7", 3799 "MSRValue": "0x0090000010", 3800 "Offcore": "1", 3801 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3802 "SampleAfterValue": "100003", 3803 "UMask": "0x1" 3804 }, 3805 { 3806 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", 3807 "Counter": "0,1,2,3", 3808 "CounterHTOff": "0,1,2,3", 3809 "EventCode": "0xB7, 0xBB", 3810 "EventName": "OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", 3811 "MSRIndex": "0x1a6,0x1a7", 3812 "MSRValue": "0x3FBC000020", 3813 "Offcore": "1", 3814 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3815 "SampleAfterValue": "100003", 3816 "UMask": "0x1" 3817 }, 3818 { 3819 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", 3820 "Counter": "0,1,2,3", 3821 "CounterHTOff": "0,1,2,3", 3822 "EventCode": "0xB7, 0xBB", 3823 "EventName": "OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", 3824 "MSRIndex": "0x1a6,0x1a7", 3825 "MSRValue": "0x103C000020", 3826 "Offcore": "1", 3827 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3828 "SampleAfterValue": "100003", 3829 "UMask": "0x1" 3830 }, 3831 { 3832 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 3833 "Counter": "0,1,2,3", 3834 "CounterHTOff": "0,1,2,3", 3835 "EventCode": "0xB7, 0xBB", 3836 "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 3837 "MSRIndex": "0x1a6,0x1a7", 3838 "MSRValue": "0x083C000020", 3839 "Offcore": "1", 3840 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3841 "SampleAfterValue": "100003", 3842 "UMask": "0x1" 3843 }, 3844 { 3845 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3846 "Counter": "0,1,2,3", 3847 "CounterHTOff": "0,1,2,3", 3848 "EventCode": "0xB7, 0xBB", 3849 "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 3850 "MSRIndex": "0x1a6,0x1a7", 3851 "MSRValue": "0x043C000020", 3852 "Offcore": "1", 3853 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3854 "SampleAfterValue": "100003", 3855 "UMask": "0x1" 3856 }, 3857 { 3858 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", 3859 "Counter": "0,1,2,3", 3860 "CounterHTOff": "0,1,2,3", 3861 "EventCode": "0xB7, 0xBB", 3862 "EventName": "OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", 3863 "MSRIndex": "0x1a6,0x1a7", 3864 "MSRValue": "0x013C000020", 3865 "Offcore": "1", 3866 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3867 "SampleAfterValue": "100003", 3868 "UMask": "0x1" 3869 }, 3870 { 3871 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", 3872 "Counter": "0,1,2,3", 3873 "CounterHTOff": "0,1,2,3", 3874 "EventCode": "0xB7, 0xBB", 3875 "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", 3876 "MSRIndex": "0x1a6,0x1a7", 3877 "MSRValue": "0x103FC00020", 3878 "Offcore": "1", 3879 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3880 "SampleAfterValue": "100003", 3881 "UMask": "0x1" 3882 }, 3883 { 3884 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 3885 "Counter": "0,1,2,3", 3886 "CounterHTOff": "0,1,2,3", 3887 "EventCode": "0xB7, 0xBB", 3888 "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 3889 "MSRIndex": "0x1a6,0x1a7", 3890 "MSRValue": "0x083FC00020", 3891 "Offcore": "1", 3892 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3893 "SampleAfterValue": "100003", 3894 "UMask": "0x1" 3895 }, 3896 { 3897 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", 3898 "Counter": "0,1,2,3", 3899 "CounterHTOff": "0,1,2,3", 3900 "EventCode": "0xB7, 0xBB", 3901 "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", 3902 "MSRIndex": "0x1a6,0x1a7", 3903 "MSRValue": "0x023C000020", 3904 "Offcore": "1", 3905 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3906 "SampleAfterValue": "100003", 3907 "UMask": "0x1" 3908 }, 3909 { 3910 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", 3911 "Counter": "0,1,2,3", 3912 "CounterHTOff": "0,1,2,3", 3913 "EventCode": "0xB7, 0xBB", 3914 "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", 3915 "MSRIndex": "0x1a6,0x1a7", 3916 "MSRValue": "0x00BC000020", 3917 "Offcore": "1", 3918 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3919 "SampleAfterValue": "100003", 3920 "UMask": "0x1" 3921 }, 3922 { 3923 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3924 "Counter": "0,1,2,3", 3925 "CounterHTOff": "0,1,2,3", 3926 "EventCode": "0xB7, 0xBB", 3927 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 3928 "MSRIndex": "0x1a6,0x1a7", 3929 "MSRValue": "0x3F84000020", 3930 "Offcore": "1", 3931 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3932 "SampleAfterValue": "100003", 3933 "UMask": "0x1" 3934 }, 3935 { 3936 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3937 "Counter": "0,1,2,3", 3938 "CounterHTOff": "0,1,2,3", 3939 "EventCode": "0xB7, 0xBB", 3940 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 3941 "MSRIndex": "0x1a6,0x1a7", 3942 "MSRValue": "0x1004000020", 3943 "Offcore": "1", 3944 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3945 "SampleAfterValue": "100003", 3946 "UMask": "0x1" 3947 }, 3948 { 3949 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3950 "Counter": "0,1,2,3", 3951 "CounterHTOff": "0,1,2,3", 3952 "EventCode": "0xB7, 0xBB", 3953 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 3954 "MSRIndex": "0x1a6,0x1a7", 3955 "MSRValue": "0x0804000020", 3956 "Offcore": "1", 3957 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3958 "SampleAfterValue": "100003", 3959 "UMask": "0x1" 3960 }, 3961 { 3962 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3963 "Counter": "0,1,2,3", 3964 "CounterHTOff": "0,1,2,3", 3965 "EventCode": "0xB7, 0xBB", 3966 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 3967 "MSRIndex": "0x1a6,0x1a7", 3968 "MSRValue": "0x0404000020", 3969 "Offcore": "1", 3970 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3971 "SampleAfterValue": "100003", 3972 "UMask": "0x1" 3973 }, 3974 { 3975 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3976 "Counter": "0,1,2,3", 3977 "CounterHTOff": "0,1,2,3", 3978 "EventCode": "0xB7, 0xBB", 3979 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 3980 "MSRIndex": "0x1a6,0x1a7", 3981 "MSRValue": "0x0104000020", 3982 "Offcore": "1", 3983 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3984 "SampleAfterValue": "100003", 3985 "UMask": "0x1" 3986 }, 3987 { 3988 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 3989 "Counter": "0,1,2,3", 3990 "CounterHTOff": "0,1,2,3", 3991 "EventCode": "0xB7, 0xBB", 3992 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 3993 "MSRIndex": "0x1a6,0x1a7", 3994 "MSRValue": "0x0204000020", 3995 "Offcore": "1", 3996 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3997 "SampleAfterValue": "100003", 3998 "UMask": "0x1" 3999 }, 4000 { 4001 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4002 "Counter": "0,1,2,3", 4003 "CounterHTOff": "0,1,2,3", 4004 "EventCode": "0xB7, 0xBB", 4005 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4006 "MSRIndex": "0x1a6,0x1a7", 4007 "MSRValue": "0x0604000020", 4008 "Offcore": "1", 4009 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4010 "SampleAfterValue": "100003", 4011 "UMask": "0x1" 4012 }, 4013 { 4014 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 4015 "Counter": "0,1,2,3", 4016 "CounterHTOff": "0,1,2,3", 4017 "EventCode": "0xB7, 0xBB", 4018 "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 4019 "MSRIndex": "0x1a6,0x1a7", 4020 "MSRValue": "0x0084000020", 4021 "Offcore": "1", 4022 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4023 "SampleAfterValue": "100003", 4024 "UMask": "0x1" 4025 }, 4026 { 4027 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4028 "Counter": "0,1,2,3", 4029 "CounterHTOff": "0,1,2,3", 4030 "EventCode": "0xB7, 0xBB", 4031 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4032 "MSRIndex": "0x1a6,0x1a7", 4033 "MSRValue": "0x063B800020", 4034 "Offcore": "1", 4035 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4036 "SampleAfterValue": "100003", 4037 "UMask": "0x1" 4038 }, 4039 { 4040 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4041 "Counter": "0,1,2,3", 4042 "CounterHTOff": "0,1,2,3", 4043 "EventCode": "0xB7, 0xBB", 4044 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4045 "MSRIndex": "0x1a6,0x1a7", 4046 "MSRValue": "0x3F90000020", 4047 "Offcore": "1", 4048 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4049 "SampleAfterValue": "100003", 4050 "UMask": "0x1" 4051 }, 4052 { 4053 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4054 "Counter": "0,1,2,3", 4055 "CounterHTOff": "0,1,2,3", 4056 "EventCode": "0xB7, 0xBB", 4057 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4058 "MSRIndex": "0x1a6,0x1a7", 4059 "MSRValue": "0x1010000020", 4060 "Offcore": "1", 4061 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4062 "SampleAfterValue": "100003", 4063 "UMask": "0x1" 4064 }, 4065 { 4066 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4067 "Counter": "0,1,2,3", 4068 "CounterHTOff": "0,1,2,3", 4069 "EventCode": "0xB7, 0xBB", 4070 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4071 "MSRIndex": "0x1a6,0x1a7", 4072 "MSRValue": "0x0810000020", 4073 "Offcore": "1", 4074 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4075 "SampleAfterValue": "100003", 4076 "UMask": "0x1" 4077 }, 4078 { 4079 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4080 "Counter": "0,1,2,3", 4081 "CounterHTOff": "0,1,2,3", 4082 "EventCode": "0xB7, 0xBB", 4083 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4084 "MSRIndex": "0x1a6,0x1a7", 4085 "MSRValue": "0x0410000020", 4086 "Offcore": "1", 4087 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4088 "SampleAfterValue": "100003", 4089 "UMask": "0x1" 4090 }, 4091 { 4092 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4093 "Counter": "0,1,2,3", 4094 "CounterHTOff": "0,1,2,3", 4095 "EventCode": "0xB7, 0xBB", 4096 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4097 "MSRIndex": "0x1a6,0x1a7", 4098 "MSRValue": "0x0110000020", 4099 "Offcore": "1", 4100 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4101 "SampleAfterValue": "100003", 4102 "UMask": "0x1" 4103 }, 4104 { 4105 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 4106 "Counter": "0,1,2,3", 4107 "CounterHTOff": "0,1,2,3", 4108 "EventCode": "0xB7, 0xBB", 4109 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4110 "MSRIndex": "0x1a6,0x1a7", 4111 "MSRValue": "0x0210000020", 4112 "Offcore": "1", 4113 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4114 "SampleAfterValue": "100003", 4115 "UMask": "0x1" 4116 }, 4117 { 4118 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 4119 "Counter": "0,1,2,3", 4120 "CounterHTOff": "0,1,2,3", 4121 "EventCode": "0xB7, 0xBB", 4122 "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4123 "MSRIndex": "0x1a6,0x1a7", 4124 "MSRValue": "0x0090000020", 4125 "Offcore": "1", 4126 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4127 "SampleAfterValue": "100003", 4128 "UMask": "0x1" 4129 }, 4130 { 4131 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 4132 "Counter": "0,1,2,3", 4133 "CounterHTOff": "0,1,2,3", 4134 "EventCode": "0xB7, 0xBB", 4135 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 4136 "MSRIndex": "0x1a6,0x1a7", 4137 "MSRValue": "0x3FBC000080", 4138 "Offcore": "1", 4139 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4140 "SampleAfterValue": "100003", 4141 "UMask": "0x1" 4142 }, 4143 { 4144 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", 4145 "Counter": "0,1,2,3", 4146 "CounterHTOff": "0,1,2,3", 4147 "EventCode": "0xB7, 0xBB", 4148 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", 4149 "MSRIndex": "0x1a6,0x1a7", 4150 "MSRValue": "0x103C000080", 4151 "Offcore": "1", 4152 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4153 "SampleAfterValue": "100003", 4154 "UMask": "0x1" 4155 }, 4156 { 4157 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 4158 "Counter": "0,1,2,3", 4159 "CounterHTOff": "0,1,2,3", 4160 "EventCode": "0xB7, 0xBB", 4161 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 4162 "MSRIndex": "0x1a6,0x1a7", 4163 "MSRValue": "0x083C000080", 4164 "Offcore": "1", 4165 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4166 "SampleAfterValue": "100003", 4167 "UMask": "0x1" 4168 }, 4169 { 4170 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 4171 "Counter": "0,1,2,3", 4172 "CounterHTOff": "0,1,2,3", 4173 "EventCode": "0xB7, 0xBB", 4174 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 4175 "MSRIndex": "0x1a6,0x1a7", 4176 "MSRValue": "0x043C000080", 4177 "Offcore": "1", 4178 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4179 "SampleAfterValue": "100003", 4180 "UMask": "0x1" 4181 }, 4182 { 4183 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 4184 "Counter": "0,1,2,3", 4185 "CounterHTOff": "0,1,2,3", 4186 "EventCode": "0xB7, 0xBB", 4187 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 4188 "MSRIndex": "0x1a6,0x1a7", 4189 "MSRValue": "0x013C000080", 4190 "Offcore": "1", 4191 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4192 "SampleAfterValue": "100003", 4193 "UMask": "0x1" 4194 }, 4195 { 4196 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 4197 "Counter": "0,1,2,3", 4198 "CounterHTOff": "0,1,2,3", 4199 "EventCode": "0xB7, 0xBB", 4200 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 4201 "MSRIndex": "0x1a6,0x1a7", 4202 "MSRValue": "0x103FC00080", 4203 "Offcore": "1", 4204 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4205 "SampleAfterValue": "100003", 4206 "UMask": "0x1" 4207 }, 4208 { 4209 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 4210 "Counter": "0,1,2,3", 4211 "CounterHTOff": "0,1,2,3", 4212 "EventCode": "0xB7, 0xBB", 4213 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 4214 "MSRIndex": "0x1a6,0x1a7", 4215 "MSRValue": "0x083FC00080", 4216 "Offcore": "1", 4217 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4218 "SampleAfterValue": "100003", 4219 "UMask": "0x1" 4220 }, 4221 { 4222 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 4223 "Counter": "0,1,2,3", 4224 "CounterHTOff": "0,1,2,3", 4225 "EventCode": "0xB7, 0xBB", 4226 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 4227 "MSRIndex": "0x1a6,0x1a7", 4228 "MSRValue": "0x023C000080", 4229 "Offcore": "1", 4230 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4231 "SampleAfterValue": "100003", 4232 "UMask": "0x1" 4233 }, 4234 { 4235 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 4236 "Counter": "0,1,2,3", 4237 "CounterHTOff": "0,1,2,3", 4238 "EventCode": "0xB7, 0xBB", 4239 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 4240 "MSRIndex": "0x1a6,0x1a7", 4241 "MSRValue": "0x00BC000080", 4242 "Offcore": "1", 4243 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4244 "SampleAfterValue": "100003", 4245 "UMask": "0x1" 4246 }, 4247 { 4248 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4249 "Counter": "0,1,2,3", 4250 "CounterHTOff": "0,1,2,3", 4251 "EventCode": "0xB7, 0xBB", 4252 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4253 "MSRIndex": "0x1a6,0x1a7", 4254 "MSRValue": "0x3F84000080", 4255 "Offcore": "1", 4256 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4257 "SampleAfterValue": "100003", 4258 "UMask": "0x1" 4259 }, 4260 { 4261 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4262 "Counter": "0,1,2,3", 4263 "CounterHTOff": "0,1,2,3", 4264 "EventCode": "0xB7, 0xBB", 4265 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4266 "MSRIndex": "0x1a6,0x1a7", 4267 "MSRValue": "0x1004000080", 4268 "Offcore": "1", 4269 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4270 "SampleAfterValue": "100003", 4271 "UMask": "0x1" 4272 }, 4273 { 4274 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4275 "Counter": "0,1,2,3", 4276 "CounterHTOff": "0,1,2,3", 4277 "EventCode": "0xB7, 0xBB", 4278 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4279 "MSRIndex": "0x1a6,0x1a7", 4280 "MSRValue": "0x0804000080", 4281 "Offcore": "1", 4282 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4283 "SampleAfterValue": "100003", 4284 "UMask": "0x1" 4285 }, 4286 { 4287 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4288 "Counter": "0,1,2,3", 4289 "CounterHTOff": "0,1,2,3", 4290 "EventCode": "0xB7, 0xBB", 4291 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4292 "MSRIndex": "0x1a6,0x1a7", 4293 "MSRValue": "0x0404000080", 4294 "Offcore": "1", 4295 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4296 "SampleAfterValue": "100003", 4297 "UMask": "0x1" 4298 }, 4299 { 4300 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4301 "Counter": "0,1,2,3", 4302 "CounterHTOff": "0,1,2,3", 4303 "EventCode": "0xB7, 0xBB", 4304 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4305 "MSRIndex": "0x1a6,0x1a7", 4306 "MSRValue": "0x0104000080", 4307 "Offcore": "1", 4308 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4309 "SampleAfterValue": "100003", 4310 "UMask": "0x1" 4311 }, 4312 { 4313 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 4314 "Counter": "0,1,2,3", 4315 "CounterHTOff": "0,1,2,3", 4316 "EventCode": "0xB7, 0xBB", 4317 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 4318 "MSRIndex": "0x1a6,0x1a7", 4319 "MSRValue": "0x0204000080", 4320 "Offcore": "1", 4321 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4322 "SampleAfterValue": "100003", 4323 "UMask": "0x1" 4324 }, 4325 { 4326 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4327 "Counter": "0,1,2,3", 4328 "CounterHTOff": "0,1,2,3", 4329 "EventCode": "0xB7, 0xBB", 4330 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4331 "MSRIndex": "0x1a6,0x1a7", 4332 "MSRValue": "0x0604000080", 4333 "Offcore": "1", 4334 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4335 "SampleAfterValue": "100003", 4336 "UMask": "0x1" 4337 }, 4338 { 4339 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 4340 "Counter": "0,1,2,3", 4341 "CounterHTOff": "0,1,2,3", 4342 "EventCode": "0xB7, 0xBB", 4343 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 4344 "MSRIndex": "0x1a6,0x1a7", 4345 "MSRValue": "0x0084000080", 4346 "Offcore": "1", 4347 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4348 "SampleAfterValue": "100003", 4349 "UMask": "0x1" 4350 }, 4351 { 4352 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4353 "Counter": "0,1,2,3", 4354 "CounterHTOff": "0,1,2,3", 4355 "EventCode": "0xB7, 0xBB", 4356 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4357 "MSRIndex": "0x1a6,0x1a7", 4358 "MSRValue": "0x063B800080", 4359 "Offcore": "1", 4360 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4361 "SampleAfterValue": "100003", 4362 "UMask": "0x1" 4363 }, 4364 { 4365 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4366 "Counter": "0,1,2,3", 4367 "CounterHTOff": "0,1,2,3", 4368 "EventCode": "0xB7, 0xBB", 4369 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4370 "MSRIndex": "0x1a6,0x1a7", 4371 "MSRValue": "0x3F90000080", 4372 "Offcore": "1", 4373 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4374 "SampleAfterValue": "100003", 4375 "UMask": "0x1" 4376 }, 4377 { 4378 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4379 "Counter": "0,1,2,3", 4380 "CounterHTOff": "0,1,2,3", 4381 "EventCode": "0xB7, 0xBB", 4382 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4383 "MSRIndex": "0x1a6,0x1a7", 4384 "MSRValue": "0x1010000080", 4385 "Offcore": "1", 4386 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4387 "SampleAfterValue": "100003", 4388 "UMask": "0x1" 4389 }, 4390 { 4391 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4392 "Counter": "0,1,2,3", 4393 "CounterHTOff": "0,1,2,3", 4394 "EventCode": "0xB7, 0xBB", 4395 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4396 "MSRIndex": "0x1a6,0x1a7", 4397 "MSRValue": "0x0810000080", 4398 "Offcore": "1", 4399 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4400 "SampleAfterValue": "100003", 4401 "UMask": "0x1" 4402 }, 4403 { 4404 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4405 "Counter": "0,1,2,3", 4406 "CounterHTOff": "0,1,2,3", 4407 "EventCode": "0xB7, 0xBB", 4408 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4409 "MSRIndex": "0x1a6,0x1a7", 4410 "MSRValue": "0x0410000080", 4411 "Offcore": "1", 4412 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4413 "SampleAfterValue": "100003", 4414 "UMask": "0x1" 4415 }, 4416 { 4417 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4418 "Counter": "0,1,2,3", 4419 "CounterHTOff": "0,1,2,3", 4420 "EventCode": "0xB7, 0xBB", 4421 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4422 "MSRIndex": "0x1a6,0x1a7", 4423 "MSRValue": "0x0110000080", 4424 "Offcore": "1", 4425 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4426 "SampleAfterValue": "100003", 4427 "UMask": "0x1" 4428 }, 4429 { 4430 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 4431 "Counter": "0,1,2,3", 4432 "CounterHTOff": "0,1,2,3", 4433 "EventCode": "0xB7, 0xBB", 4434 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4435 "MSRIndex": "0x1a6,0x1a7", 4436 "MSRValue": "0x0210000080", 4437 "Offcore": "1", 4438 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4439 "SampleAfterValue": "100003", 4440 "UMask": "0x1" 4441 }, 4442 { 4443 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 4444 "Counter": "0,1,2,3", 4445 "CounterHTOff": "0,1,2,3", 4446 "EventCode": "0xB7, 0xBB", 4447 "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4448 "MSRIndex": "0x1a6,0x1a7", 4449 "MSRValue": "0x0090000080", 4450 "Offcore": "1", 4451 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4452 "SampleAfterValue": "100003", 4453 "UMask": "0x1" 4454 }, 4455 { 4456 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", 4457 "Counter": "0,1,2,3", 4458 "CounterHTOff": "0,1,2,3", 4459 "EventCode": "0xB7, 0xBB", 4460 "EventName": "OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", 4461 "MSRIndex": "0x1a6,0x1a7", 4462 "MSRValue": "0x3FBC000100", 4463 "Offcore": "1", 4464 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4465 "SampleAfterValue": "100003", 4466 "UMask": "0x1" 4467 }, 4468 { 4469 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", 4470 "Counter": "0,1,2,3", 4471 "CounterHTOff": "0,1,2,3", 4472 "EventCode": "0xB7, 0xBB", 4473 "EventName": "OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", 4474 "MSRIndex": "0x1a6,0x1a7", 4475 "MSRValue": "0x103C000100", 4476 "Offcore": "1", 4477 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4478 "SampleAfterValue": "100003", 4479 "UMask": "0x1" 4480 }, 4481 { 4482 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 4483 "Counter": "0,1,2,3", 4484 "CounterHTOff": "0,1,2,3", 4485 "EventCode": "0xB7, 0xBB", 4486 "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 4487 "MSRIndex": "0x1a6,0x1a7", 4488 "MSRValue": "0x083C000100", 4489 "Offcore": "1", 4490 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4491 "SampleAfterValue": "100003", 4492 "UMask": "0x1" 4493 }, 4494 { 4495 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 4496 "Counter": "0,1,2,3", 4497 "CounterHTOff": "0,1,2,3", 4498 "EventCode": "0xB7, 0xBB", 4499 "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 4500 "MSRIndex": "0x1a6,0x1a7", 4501 "MSRValue": "0x043C000100", 4502 "Offcore": "1", 4503 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4504 "SampleAfterValue": "100003", 4505 "UMask": "0x1" 4506 }, 4507 { 4508 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", 4509 "Counter": "0,1,2,3", 4510 "CounterHTOff": "0,1,2,3", 4511 "EventCode": "0xB7, 0xBB", 4512 "EventName": "OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", 4513 "MSRIndex": "0x1a6,0x1a7", 4514 "MSRValue": "0x013C000100", 4515 "Offcore": "1", 4516 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4517 "SampleAfterValue": "100003", 4518 "UMask": "0x1" 4519 }, 4520 { 4521 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", 4522 "Counter": "0,1,2,3", 4523 "CounterHTOff": "0,1,2,3", 4524 "EventCode": "0xB7, 0xBB", 4525 "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", 4526 "MSRIndex": "0x1a6,0x1a7", 4527 "MSRValue": "0x103FC00100", 4528 "Offcore": "1", 4529 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4530 "SampleAfterValue": "100003", 4531 "UMask": "0x1" 4532 }, 4533 { 4534 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 4535 "Counter": "0,1,2,3", 4536 "CounterHTOff": "0,1,2,3", 4537 "EventCode": "0xB7, 0xBB", 4538 "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 4539 "MSRIndex": "0x1a6,0x1a7", 4540 "MSRValue": "0x083FC00100", 4541 "Offcore": "1", 4542 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4543 "SampleAfterValue": "100003", 4544 "UMask": "0x1" 4545 }, 4546 { 4547 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", 4548 "Counter": "0,1,2,3", 4549 "CounterHTOff": "0,1,2,3", 4550 "EventCode": "0xB7, 0xBB", 4551 "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", 4552 "MSRIndex": "0x1a6,0x1a7", 4553 "MSRValue": "0x023C000100", 4554 "Offcore": "1", 4555 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4556 "SampleAfterValue": "100003", 4557 "UMask": "0x1" 4558 }, 4559 { 4560 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", 4561 "Counter": "0,1,2,3", 4562 "CounterHTOff": "0,1,2,3", 4563 "EventCode": "0xB7, 0xBB", 4564 "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", 4565 "MSRIndex": "0x1a6,0x1a7", 4566 "MSRValue": "0x00BC000100", 4567 "Offcore": "1", 4568 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4569 "SampleAfterValue": "100003", 4570 "UMask": "0x1" 4571 }, 4572 { 4573 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4574 "Counter": "0,1,2,3", 4575 "CounterHTOff": "0,1,2,3", 4576 "EventCode": "0xB7, 0xBB", 4577 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4578 "MSRIndex": "0x1a6,0x1a7", 4579 "MSRValue": "0x3F84000100", 4580 "Offcore": "1", 4581 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4582 "SampleAfterValue": "100003", 4583 "UMask": "0x1" 4584 }, 4585 { 4586 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4587 "Counter": "0,1,2,3", 4588 "CounterHTOff": "0,1,2,3", 4589 "EventCode": "0xB7, 0xBB", 4590 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4591 "MSRIndex": "0x1a6,0x1a7", 4592 "MSRValue": "0x1004000100", 4593 "Offcore": "1", 4594 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4595 "SampleAfterValue": "100003", 4596 "UMask": "0x1" 4597 }, 4598 { 4599 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4600 "Counter": "0,1,2,3", 4601 "CounterHTOff": "0,1,2,3", 4602 "EventCode": "0xB7, 0xBB", 4603 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4604 "MSRIndex": "0x1a6,0x1a7", 4605 "MSRValue": "0x0804000100", 4606 "Offcore": "1", 4607 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4608 "SampleAfterValue": "100003", 4609 "UMask": "0x1" 4610 }, 4611 { 4612 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4613 "Counter": "0,1,2,3", 4614 "CounterHTOff": "0,1,2,3", 4615 "EventCode": "0xB7, 0xBB", 4616 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4617 "MSRIndex": "0x1a6,0x1a7", 4618 "MSRValue": "0x0404000100", 4619 "Offcore": "1", 4620 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4621 "SampleAfterValue": "100003", 4622 "UMask": "0x1" 4623 }, 4624 { 4625 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4626 "Counter": "0,1,2,3", 4627 "CounterHTOff": "0,1,2,3", 4628 "EventCode": "0xB7, 0xBB", 4629 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 4630 "MSRIndex": "0x1a6,0x1a7", 4631 "MSRValue": "0x0104000100", 4632 "Offcore": "1", 4633 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4634 "SampleAfterValue": "100003", 4635 "UMask": "0x1" 4636 }, 4637 { 4638 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 4639 "Counter": "0,1,2,3", 4640 "CounterHTOff": "0,1,2,3", 4641 "EventCode": "0xB7, 0xBB", 4642 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 4643 "MSRIndex": "0x1a6,0x1a7", 4644 "MSRValue": "0x0204000100", 4645 "Offcore": "1", 4646 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4647 "SampleAfterValue": "100003", 4648 "UMask": "0x1" 4649 }, 4650 { 4651 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4652 "Counter": "0,1,2,3", 4653 "CounterHTOff": "0,1,2,3", 4654 "EventCode": "0xB7, 0xBB", 4655 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 4656 "MSRIndex": "0x1a6,0x1a7", 4657 "MSRValue": "0x0604000100", 4658 "Offcore": "1", 4659 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4660 "SampleAfterValue": "100003", 4661 "UMask": "0x1" 4662 }, 4663 { 4664 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 4665 "Counter": "0,1,2,3", 4666 "CounterHTOff": "0,1,2,3", 4667 "EventCode": "0xB7, 0xBB", 4668 "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 4669 "MSRIndex": "0x1a6,0x1a7", 4670 "MSRValue": "0x0084000100", 4671 "Offcore": "1", 4672 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4673 "SampleAfterValue": "100003", 4674 "UMask": "0x1" 4675 }, 4676 { 4677 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4678 "Counter": "0,1,2,3", 4679 "CounterHTOff": "0,1,2,3", 4680 "EventCode": "0xB7, 0xBB", 4681 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 4682 "MSRIndex": "0x1a6,0x1a7", 4683 "MSRValue": "0x063B800100", 4684 "Offcore": "1", 4685 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4686 "SampleAfterValue": "100003", 4687 "UMask": "0x1" 4688 }, 4689 { 4690 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4691 "Counter": "0,1,2,3", 4692 "CounterHTOff": "0,1,2,3", 4693 "EventCode": "0xB7, 0xBB", 4694 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 4695 "MSRIndex": "0x1a6,0x1a7", 4696 "MSRValue": "0x3F90000100", 4697 "Offcore": "1", 4698 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4699 "SampleAfterValue": "100003", 4700 "UMask": "0x1" 4701 }, 4702 { 4703 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4704 "Counter": "0,1,2,3", 4705 "CounterHTOff": "0,1,2,3", 4706 "EventCode": "0xB7, 0xBB", 4707 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 4708 "MSRIndex": "0x1a6,0x1a7", 4709 "MSRValue": "0x1010000100", 4710 "Offcore": "1", 4711 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4712 "SampleAfterValue": "100003", 4713 "UMask": "0x1" 4714 }, 4715 { 4716 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4717 "Counter": "0,1,2,3", 4718 "CounterHTOff": "0,1,2,3", 4719 "EventCode": "0xB7, 0xBB", 4720 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 4721 "MSRIndex": "0x1a6,0x1a7", 4722 "MSRValue": "0x0810000100", 4723 "Offcore": "1", 4724 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4725 "SampleAfterValue": "100003", 4726 "UMask": "0x1" 4727 }, 4728 { 4729 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4730 "Counter": "0,1,2,3", 4731 "CounterHTOff": "0,1,2,3", 4732 "EventCode": "0xB7, 0xBB", 4733 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 4734 "MSRIndex": "0x1a6,0x1a7", 4735 "MSRValue": "0x0410000100", 4736 "Offcore": "1", 4737 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4738 "SampleAfterValue": "100003", 4739 "UMask": "0x1" 4740 }, 4741 { 4742 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4743 "Counter": "0,1,2,3", 4744 "CounterHTOff": "0,1,2,3", 4745 "EventCode": "0xB7, 0xBB", 4746 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 4747 "MSRIndex": "0x1a6,0x1a7", 4748 "MSRValue": "0x0110000100", 4749 "Offcore": "1", 4750 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4751 "SampleAfterValue": "100003", 4752 "UMask": "0x1" 4753 }, 4754 { 4755 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 4756 "Counter": "0,1,2,3", 4757 "CounterHTOff": "0,1,2,3", 4758 "EventCode": "0xB7, 0xBB", 4759 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 4760 "MSRIndex": "0x1a6,0x1a7", 4761 "MSRValue": "0x0210000100", 4762 "Offcore": "1", 4763 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4764 "SampleAfterValue": "100003", 4765 "UMask": "0x1" 4766 }, 4767 { 4768 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 4769 "Counter": "0,1,2,3", 4770 "CounterHTOff": "0,1,2,3", 4771 "EventCode": "0xB7, 0xBB", 4772 "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 4773 "MSRIndex": "0x1a6,0x1a7", 4774 "MSRValue": "0x0090000100", 4775 "Offcore": "1", 4776 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4777 "SampleAfterValue": "100003", 4778 "UMask": "0x1" 4779 }, 4780 { 4781 "BriefDescription": "Demand Data Read requests who miss L3 cache", 4782 "Counter": "0,1,2,3", 4783 "CounterHTOff": "0,1,2,3,4,5,6,7", 4784 "EventCode": "0xB0", 4785 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 4786 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 4787 "SampleAfterValue": "100003", 4788 "UMask": "0x10" 4789 }, 4790 { 4791 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 4792 "Counter": "0,1,2,3", 4793 "CounterHTOff": "0,1,2,3,4,5,6,7", 4794 "CounterMask": "1", 4795 "EventCode": "0x60", 4796 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 4797 "SampleAfterValue": "2000003", 4798 "UMask": "0x10" 4799 }, 4800 { 4801 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 4802 "Counter": "0,1,2,3", 4803 "CounterHTOff": "0,1,2,3,4,5,6,7", 4804 "EventCode": "0x60", 4805 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 4806 "SampleAfterValue": "2000003", 4807 "UMask": "0x10" 4808 }, 4809 { 4810 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 4811 "Counter": "0,1,2,3", 4812 "CounterHTOff": "0,1,2,3,4,5,6,7", 4813 "CounterMask": "6", 4814 "EventCode": "0x60", 4815 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 4816 "SampleAfterValue": "2000003", 4817 "UMask": "0x10" 4818 }, 4819 { 4820 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 4821 "Counter": "0,1,2,3", 4822 "CounterHTOff": "0,1,2,3", 4823 "Deprecated": "1", 4824 "EventCode": "0xB7, 0xBB", 4825 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 4826 "MSRIndex": "0x1a6,0x1a7", 4827 "MSRValue": "0x3FBC000491", 4828 "Offcore": "1", 4829 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4830 "SampleAfterValue": "100003", 4831 "UMask": "0x1" 4832 }, 4833 { 4834 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", 4835 "Counter": "0,1,2,3", 4836 "CounterHTOff": "0,1,2,3", 4837 "Deprecated": "1", 4838 "EventCode": "0xB7, 0xBB", 4839 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", 4840 "MSRIndex": "0x1a6,0x1a7", 4841 "MSRValue": "0x103C000491", 4842 "Offcore": "1", 4843 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4844 "SampleAfterValue": "100003", 4845 "UMask": "0x1" 4846 }, 4847 { 4848 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 4849 "Counter": "0,1,2,3", 4850 "CounterHTOff": "0,1,2,3", 4851 "Deprecated": "1", 4852 "EventCode": "0xB7, 0xBB", 4853 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 4854 "MSRIndex": "0x1a6,0x1a7", 4855 "MSRValue": "0x083C000491", 4856 "Offcore": "1", 4857 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4858 "SampleAfterValue": "100003", 4859 "UMask": "0x1" 4860 }, 4861 { 4862 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 4863 "Counter": "0,1,2,3", 4864 "CounterHTOff": "0,1,2,3", 4865 "Deprecated": "1", 4866 "EventCode": "0xB7, 0xBB", 4867 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 4868 "MSRIndex": "0x1a6,0x1a7", 4869 "MSRValue": "0x043C000491", 4870 "Offcore": "1", 4871 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4872 "SampleAfterValue": "100003", 4873 "UMask": "0x1" 4874 }, 4875 { 4876 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 4877 "Counter": "0,1,2,3", 4878 "CounterHTOff": "0,1,2,3", 4879 "Deprecated": "1", 4880 "EventCode": "0xB7, 0xBB", 4881 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 4882 "MSRIndex": "0x1a6,0x1a7", 4883 "MSRValue": "0x013C000491", 4884 "Offcore": "1", 4885 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4886 "SampleAfterValue": "100003", 4887 "UMask": "0x1" 4888 }, 4889 { 4890 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 4891 "Counter": "0,1,2,3", 4892 "CounterHTOff": "0,1,2,3", 4893 "Deprecated": "1", 4894 "EventCode": "0xB7, 0xBB", 4895 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 4896 "MSRIndex": "0x1a6,0x1a7", 4897 "MSRValue": "0x103FC00491", 4898 "Offcore": "1", 4899 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4900 "SampleAfterValue": "100003", 4901 "UMask": "0x1" 4902 }, 4903 { 4904 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 4905 "Counter": "0,1,2,3", 4906 "CounterHTOff": "0,1,2,3", 4907 "Deprecated": "1", 4908 "EventCode": "0xB7, 0xBB", 4909 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 4910 "MSRIndex": "0x1a6,0x1a7", 4911 "MSRValue": "0x083FC00491", 4912 "Offcore": "1", 4913 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4914 "SampleAfterValue": "100003", 4915 "UMask": "0x1" 4916 }, 4917 { 4918 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 4919 "Counter": "0,1,2,3", 4920 "CounterHTOff": "0,1,2,3", 4921 "Deprecated": "1", 4922 "EventCode": "0xB7, 0xBB", 4923 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", 4924 "MSRIndex": "0x1a6,0x1a7", 4925 "MSRValue": "0x023C000491", 4926 "Offcore": "1", 4927 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4928 "SampleAfterValue": "100003", 4929 "UMask": "0x1" 4930 }, 4931 { 4932 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 4933 "Counter": "0,1,2,3", 4934 "CounterHTOff": "0,1,2,3", 4935 "Deprecated": "1", 4936 "EventCode": "0xB7, 0xBB", 4937 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", 4938 "MSRIndex": "0x1a6,0x1a7", 4939 "MSRValue": "0x00BC000491", 4940 "Offcore": "1", 4941 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4942 "SampleAfterValue": "100003", 4943 "UMask": "0x1" 4944 }, 4945 { 4946 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4947 "Counter": "0,1,2,3", 4948 "CounterHTOff": "0,1,2,3", 4949 "Deprecated": "1", 4950 "EventCode": "0xB7, 0xBB", 4951 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 4952 "MSRIndex": "0x1a6,0x1a7", 4953 "MSRValue": "0x3F84000491", 4954 "Offcore": "1", 4955 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4956 "SampleAfterValue": "100003", 4957 "UMask": "0x1" 4958 }, 4959 { 4960 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4961 "Counter": "0,1,2,3", 4962 "CounterHTOff": "0,1,2,3", 4963 "Deprecated": "1", 4964 "EventCode": "0xB7, 0xBB", 4965 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 4966 "MSRIndex": "0x1a6,0x1a7", 4967 "MSRValue": "0x1004000491", 4968 "Offcore": "1", 4969 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4970 "SampleAfterValue": "100003", 4971 "UMask": "0x1" 4972 }, 4973 { 4974 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4975 "Counter": "0,1,2,3", 4976 "CounterHTOff": "0,1,2,3", 4977 "Deprecated": "1", 4978 "EventCode": "0xB7, 0xBB", 4979 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 4980 "MSRIndex": "0x1a6,0x1a7", 4981 "MSRValue": "0x0804000491", 4982 "Offcore": "1", 4983 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4984 "SampleAfterValue": "100003", 4985 "UMask": "0x1" 4986 }, 4987 { 4988 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4989 "Counter": "0,1,2,3", 4990 "CounterHTOff": "0,1,2,3", 4991 "Deprecated": "1", 4992 "EventCode": "0xB7, 0xBB", 4993 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 4994 "MSRIndex": "0x1a6,0x1a7", 4995 "MSRValue": "0x0404000491", 4996 "Offcore": "1", 4997 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4998 "SampleAfterValue": "100003", 4999 "UMask": "0x1" 5000 }, 5001 { 5002 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5003 "Counter": "0,1,2,3", 5004 "CounterHTOff": "0,1,2,3", 5005 "Deprecated": "1", 5006 "EventCode": "0xB7, 0xBB", 5007 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5008 "MSRIndex": "0x1a6,0x1a7", 5009 "MSRValue": "0x0104000491", 5010 "Offcore": "1", 5011 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5012 "SampleAfterValue": "100003", 5013 "UMask": "0x1" 5014 }, 5015 { 5016 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5017 "Counter": "0,1,2,3", 5018 "CounterHTOff": "0,1,2,3", 5019 "Deprecated": "1", 5020 "EventCode": "0xB7, 0xBB", 5021 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5022 "MSRIndex": "0x1a6,0x1a7", 5023 "MSRValue": "0x0204000491", 5024 "Offcore": "1", 5025 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5026 "SampleAfterValue": "100003", 5027 "UMask": "0x1" 5028 }, 5029 { 5030 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 5031 "Counter": "0,1,2,3", 5032 "CounterHTOff": "0,1,2,3", 5033 "Deprecated": "1", 5034 "EventCode": "0xB7, 0xBB", 5035 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 5036 "MSRIndex": "0x1a6,0x1a7", 5037 "MSRValue": "0x0604000491", 5038 "Offcore": "1", 5039 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5040 "SampleAfterValue": "100003", 5041 "UMask": "0x1" 5042 }, 5043 { 5044 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5045 "Counter": "0,1,2,3", 5046 "CounterHTOff": "0,1,2,3", 5047 "Deprecated": "1", 5048 "EventCode": "0xB7, 0xBB", 5049 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5050 "MSRIndex": "0x1a6,0x1a7", 5051 "MSRValue": "0x0084000491", 5052 "Offcore": "1", 5053 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5054 "SampleAfterValue": "100003", 5055 "UMask": "0x1" 5056 }, 5057 { 5058 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 5059 "Counter": "0,1,2,3", 5060 "CounterHTOff": "0,1,2,3", 5061 "Deprecated": "1", 5062 "EventCode": "0xB7, 0xBB", 5063 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 5064 "MSRIndex": "0x1a6,0x1a7", 5065 "MSRValue": "0x063B800491", 5066 "Offcore": "1", 5067 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5068 "SampleAfterValue": "100003", 5069 "UMask": "0x1" 5070 }, 5071 { 5072 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 5073 "Counter": "0,1,2,3", 5074 "CounterHTOff": "0,1,2,3", 5075 "Deprecated": "1", 5076 "EventCode": "0xB7, 0xBB", 5077 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 5078 "MSRIndex": "0x1a6,0x1a7", 5079 "MSRValue": "0x3F90000491", 5080 "Offcore": "1", 5081 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5082 "SampleAfterValue": "100003", 5083 "UMask": "0x1" 5084 }, 5085 { 5086 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 5087 "Counter": "0,1,2,3", 5088 "CounterHTOff": "0,1,2,3", 5089 "Deprecated": "1", 5090 "EventCode": "0xB7, 0xBB", 5091 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 5092 "MSRIndex": "0x1a6,0x1a7", 5093 "MSRValue": "0x1010000491", 5094 "Offcore": "1", 5095 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5096 "SampleAfterValue": "100003", 5097 "UMask": "0x1" 5098 }, 5099 { 5100 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 5101 "Counter": "0,1,2,3", 5102 "CounterHTOff": "0,1,2,3", 5103 "Deprecated": "1", 5104 "EventCode": "0xB7, 0xBB", 5105 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 5106 "MSRIndex": "0x1a6,0x1a7", 5107 "MSRValue": "0x0810000491", 5108 "Offcore": "1", 5109 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5110 "SampleAfterValue": "100003", 5111 "UMask": "0x1" 5112 }, 5113 { 5114 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 5115 "Counter": "0,1,2,3", 5116 "CounterHTOff": "0,1,2,3", 5117 "Deprecated": "1", 5118 "EventCode": "0xB7, 0xBB", 5119 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 5120 "MSRIndex": "0x1a6,0x1a7", 5121 "MSRValue": "0x0410000491", 5122 "Offcore": "1", 5123 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5124 "SampleAfterValue": "100003", 5125 "UMask": "0x1" 5126 }, 5127 { 5128 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 5129 "Counter": "0,1,2,3", 5130 "CounterHTOff": "0,1,2,3", 5131 "Deprecated": "1", 5132 "EventCode": "0xB7, 0xBB", 5133 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 5134 "MSRIndex": "0x1a6,0x1a7", 5135 "MSRValue": "0x0110000491", 5136 "Offcore": "1", 5137 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5138 "SampleAfterValue": "100003", 5139 "UMask": "0x1" 5140 }, 5141 { 5142 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 5143 "Counter": "0,1,2,3", 5144 "CounterHTOff": "0,1,2,3", 5145 "Deprecated": "1", 5146 "EventCode": "0xB7, 0xBB", 5147 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 5148 "MSRIndex": "0x1a6,0x1a7", 5149 "MSRValue": "0x0210000491", 5150 "Offcore": "1", 5151 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5152 "SampleAfterValue": "100003", 5153 "UMask": "0x1" 5154 }, 5155 { 5156 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 5157 "Counter": "0,1,2,3", 5158 "CounterHTOff": "0,1,2,3", 5159 "Deprecated": "1", 5160 "EventCode": "0xB7, 0xBB", 5161 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 5162 "MSRIndex": "0x1a6,0x1a7", 5163 "MSRValue": "0x0090000491", 5164 "Offcore": "1", 5165 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5166 "SampleAfterValue": "100003", 5167 "UMask": "0x1" 5168 }, 5169 { 5170 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 5171 "Counter": "0,1,2,3", 5172 "CounterHTOff": "0,1,2,3", 5173 "Deprecated": "1", 5174 "EventCode": "0xB7, 0xBB", 5175 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 5176 "MSRIndex": "0x1a6,0x1a7", 5177 "MSRValue": "0x3FBC000490", 5178 "Offcore": "1", 5179 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5180 "SampleAfterValue": "100003", 5181 "UMask": "0x1" 5182 }, 5183 { 5184 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", 5185 "Counter": "0,1,2,3", 5186 "CounterHTOff": "0,1,2,3", 5187 "Deprecated": "1", 5188 "EventCode": "0xB7, 0xBB", 5189 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", 5190 "MSRIndex": "0x1a6,0x1a7", 5191 "MSRValue": "0x103C000490", 5192 "Offcore": "1", 5193 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5194 "SampleAfterValue": "100003", 5195 "UMask": "0x1" 5196 }, 5197 { 5198 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 5199 "Counter": "0,1,2,3", 5200 "CounterHTOff": "0,1,2,3", 5201 "Deprecated": "1", 5202 "EventCode": "0xB7, 0xBB", 5203 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 5204 "MSRIndex": "0x1a6,0x1a7", 5205 "MSRValue": "0x083C000490", 5206 "Offcore": "1", 5207 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5208 "SampleAfterValue": "100003", 5209 "UMask": "0x1" 5210 }, 5211 { 5212 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 5213 "Counter": "0,1,2,3", 5214 "CounterHTOff": "0,1,2,3", 5215 "Deprecated": "1", 5216 "EventCode": "0xB7, 0xBB", 5217 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 5218 "MSRIndex": "0x1a6,0x1a7", 5219 "MSRValue": "0x043C000490", 5220 "Offcore": "1", 5221 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5222 "SampleAfterValue": "100003", 5223 "UMask": "0x1" 5224 }, 5225 { 5226 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 5227 "Counter": "0,1,2,3", 5228 "CounterHTOff": "0,1,2,3", 5229 "Deprecated": "1", 5230 "EventCode": "0xB7, 0xBB", 5231 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 5232 "MSRIndex": "0x1a6,0x1a7", 5233 "MSRValue": "0x013C000490", 5234 "Offcore": "1", 5235 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5236 "SampleAfterValue": "100003", 5237 "UMask": "0x1" 5238 }, 5239 { 5240 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 5241 "Counter": "0,1,2,3", 5242 "CounterHTOff": "0,1,2,3", 5243 "Deprecated": "1", 5244 "EventCode": "0xB7, 0xBB", 5245 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 5246 "MSRIndex": "0x1a6,0x1a7", 5247 "MSRValue": "0x103FC00490", 5248 "Offcore": "1", 5249 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5250 "SampleAfterValue": "100003", 5251 "UMask": "0x1" 5252 }, 5253 { 5254 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5255 "Counter": "0,1,2,3", 5256 "CounterHTOff": "0,1,2,3", 5257 "Deprecated": "1", 5258 "EventCode": "0xB7, 0xBB", 5259 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 5260 "MSRIndex": "0x1a6,0x1a7", 5261 "MSRValue": "0x083FC00490", 5262 "Offcore": "1", 5263 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5264 "SampleAfterValue": "100003", 5265 "UMask": "0x1" 5266 }, 5267 { 5268 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 5269 "Counter": "0,1,2,3", 5270 "CounterHTOff": "0,1,2,3", 5271 "Deprecated": "1", 5272 "EventCode": "0xB7, 0xBB", 5273 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", 5274 "MSRIndex": "0x1a6,0x1a7", 5275 "MSRValue": "0x023C000490", 5276 "Offcore": "1", 5277 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5278 "SampleAfterValue": "100003", 5279 "UMask": "0x1" 5280 }, 5281 { 5282 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", 5283 "Counter": "0,1,2,3", 5284 "CounterHTOff": "0,1,2,3", 5285 "Deprecated": "1", 5286 "EventCode": "0xB7, 0xBB", 5287 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", 5288 "MSRIndex": "0x1a6,0x1a7", 5289 "MSRValue": "0x00BC000490", 5290 "Offcore": "1", 5291 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5292 "SampleAfterValue": "100003", 5293 "UMask": "0x1" 5294 }, 5295 { 5296 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5297 "Counter": "0,1,2,3", 5298 "CounterHTOff": "0,1,2,3", 5299 "Deprecated": "1", 5300 "EventCode": "0xB7, 0xBB", 5301 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5302 "MSRIndex": "0x1a6,0x1a7", 5303 "MSRValue": "0x3F84000490", 5304 "Offcore": "1", 5305 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5306 "SampleAfterValue": "100003", 5307 "UMask": "0x1" 5308 }, 5309 { 5310 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 5311 "Counter": "0,1,2,3", 5312 "CounterHTOff": "0,1,2,3", 5313 "Deprecated": "1", 5314 "EventCode": "0xB7, 0xBB", 5315 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 5316 "MSRIndex": "0x1a6,0x1a7", 5317 "MSRValue": "0x1004000490", 5318 "Offcore": "1", 5319 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5320 "SampleAfterValue": "100003", 5321 "UMask": "0x1" 5322 }, 5323 { 5324 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 5325 "Counter": "0,1,2,3", 5326 "CounterHTOff": "0,1,2,3", 5327 "Deprecated": "1", 5328 "EventCode": "0xB7, 0xBB", 5329 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 5330 "MSRIndex": "0x1a6,0x1a7", 5331 "MSRValue": "0x0804000490", 5332 "Offcore": "1", 5333 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5334 "SampleAfterValue": "100003", 5335 "UMask": "0x1" 5336 }, 5337 { 5338 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 5339 "Counter": "0,1,2,3", 5340 "CounterHTOff": "0,1,2,3", 5341 "Deprecated": "1", 5342 "EventCode": "0xB7, 0xBB", 5343 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 5344 "MSRIndex": "0x1a6,0x1a7", 5345 "MSRValue": "0x0404000490", 5346 "Offcore": "1", 5347 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5348 "SampleAfterValue": "100003", 5349 "UMask": "0x1" 5350 }, 5351 { 5352 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5353 "Counter": "0,1,2,3", 5354 "CounterHTOff": "0,1,2,3", 5355 "Deprecated": "1", 5356 "EventCode": "0xB7, 0xBB", 5357 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5358 "MSRIndex": "0x1a6,0x1a7", 5359 "MSRValue": "0x0104000490", 5360 "Offcore": "1", 5361 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5362 "SampleAfterValue": "100003", 5363 "UMask": "0x1" 5364 }, 5365 { 5366 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5367 "Counter": "0,1,2,3", 5368 "CounterHTOff": "0,1,2,3", 5369 "Deprecated": "1", 5370 "EventCode": "0xB7, 0xBB", 5371 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5372 "MSRIndex": "0x1a6,0x1a7", 5373 "MSRValue": "0x0204000490", 5374 "Offcore": "1", 5375 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5376 "SampleAfterValue": "100003", 5377 "UMask": "0x1" 5378 }, 5379 { 5380 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 5381 "Counter": "0,1,2,3", 5382 "CounterHTOff": "0,1,2,3", 5383 "Deprecated": "1", 5384 "EventCode": "0xB7, 0xBB", 5385 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 5386 "MSRIndex": "0x1a6,0x1a7", 5387 "MSRValue": "0x0604000490", 5388 "Offcore": "1", 5389 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5390 "SampleAfterValue": "100003", 5391 "UMask": "0x1" 5392 }, 5393 { 5394 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5395 "Counter": "0,1,2,3", 5396 "CounterHTOff": "0,1,2,3", 5397 "Deprecated": "1", 5398 "EventCode": "0xB7, 0xBB", 5399 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5400 "MSRIndex": "0x1a6,0x1a7", 5401 "MSRValue": "0x0084000490", 5402 "Offcore": "1", 5403 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5404 "SampleAfterValue": "100003", 5405 "UMask": "0x1" 5406 }, 5407 { 5408 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 5409 "Counter": "0,1,2,3", 5410 "CounterHTOff": "0,1,2,3", 5411 "Deprecated": "1", 5412 "EventCode": "0xB7, 0xBB", 5413 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 5414 "MSRIndex": "0x1a6,0x1a7", 5415 "MSRValue": "0x063B800490", 5416 "Offcore": "1", 5417 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5418 "SampleAfterValue": "100003", 5419 "UMask": "0x1" 5420 }, 5421 { 5422 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 5423 "Counter": "0,1,2,3", 5424 "CounterHTOff": "0,1,2,3", 5425 "Deprecated": "1", 5426 "EventCode": "0xB7, 0xBB", 5427 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 5428 "MSRIndex": "0x1a6,0x1a7", 5429 "MSRValue": "0x3F90000490", 5430 "Offcore": "1", 5431 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5432 "SampleAfterValue": "100003", 5433 "UMask": "0x1" 5434 }, 5435 { 5436 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 5437 "Counter": "0,1,2,3", 5438 "CounterHTOff": "0,1,2,3", 5439 "Deprecated": "1", 5440 "EventCode": "0xB7, 0xBB", 5441 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 5442 "MSRIndex": "0x1a6,0x1a7", 5443 "MSRValue": "0x1010000490", 5444 "Offcore": "1", 5445 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5446 "SampleAfterValue": "100003", 5447 "UMask": "0x1" 5448 }, 5449 { 5450 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 5451 "Counter": "0,1,2,3", 5452 "CounterHTOff": "0,1,2,3", 5453 "Deprecated": "1", 5454 "EventCode": "0xB7, 0xBB", 5455 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 5456 "MSRIndex": "0x1a6,0x1a7", 5457 "MSRValue": "0x0810000490", 5458 "Offcore": "1", 5459 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5460 "SampleAfterValue": "100003", 5461 "UMask": "0x1" 5462 }, 5463 { 5464 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 5465 "Counter": "0,1,2,3", 5466 "CounterHTOff": "0,1,2,3", 5467 "Deprecated": "1", 5468 "EventCode": "0xB7, 0xBB", 5469 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 5470 "MSRIndex": "0x1a6,0x1a7", 5471 "MSRValue": "0x0410000490", 5472 "Offcore": "1", 5473 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5474 "SampleAfterValue": "100003", 5475 "UMask": "0x1" 5476 }, 5477 { 5478 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 5479 "Counter": "0,1,2,3", 5480 "CounterHTOff": "0,1,2,3", 5481 "Deprecated": "1", 5482 "EventCode": "0xB7, 0xBB", 5483 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 5484 "MSRIndex": "0x1a6,0x1a7", 5485 "MSRValue": "0x0110000490", 5486 "Offcore": "1", 5487 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5488 "SampleAfterValue": "100003", 5489 "UMask": "0x1" 5490 }, 5491 { 5492 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 5493 "Counter": "0,1,2,3", 5494 "CounterHTOff": "0,1,2,3", 5495 "Deprecated": "1", 5496 "EventCode": "0xB7, 0xBB", 5497 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 5498 "MSRIndex": "0x1a6,0x1a7", 5499 "MSRValue": "0x0210000490", 5500 "Offcore": "1", 5501 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5502 "SampleAfterValue": "100003", 5503 "UMask": "0x1" 5504 }, 5505 { 5506 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 5507 "Counter": "0,1,2,3", 5508 "CounterHTOff": "0,1,2,3", 5509 "Deprecated": "1", 5510 "EventCode": "0xB7, 0xBB", 5511 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 5512 "MSRIndex": "0x1a6,0x1a7", 5513 "MSRValue": "0x0090000490", 5514 "Offcore": "1", 5515 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5516 "SampleAfterValue": "100003", 5517 "UMask": "0x1" 5518 }, 5519 { 5520 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 5521 "Counter": "0,1,2,3", 5522 "CounterHTOff": "0,1,2,3", 5523 "Deprecated": "1", 5524 "EventCode": "0xB7, 0xBB", 5525 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 5526 "MSRIndex": "0x1a6,0x1a7", 5527 "MSRValue": "0x3FBC000120", 5528 "Offcore": "1", 5529 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5530 "SampleAfterValue": "100003", 5531 "UMask": "0x1" 5532 }, 5533 { 5534 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", 5535 "Counter": "0,1,2,3", 5536 "CounterHTOff": "0,1,2,3", 5537 "Deprecated": "1", 5538 "EventCode": "0xB7, 0xBB", 5539 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", 5540 "MSRIndex": "0x1a6,0x1a7", 5541 "MSRValue": "0x103C000120", 5542 "Offcore": "1", 5543 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5544 "SampleAfterValue": "100003", 5545 "UMask": "0x1" 5546 }, 5547 { 5548 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 5549 "Counter": "0,1,2,3", 5550 "CounterHTOff": "0,1,2,3", 5551 "Deprecated": "1", 5552 "EventCode": "0xB7, 0xBB", 5553 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 5554 "MSRIndex": "0x1a6,0x1a7", 5555 "MSRValue": "0x083C000120", 5556 "Offcore": "1", 5557 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5558 "SampleAfterValue": "100003", 5559 "UMask": "0x1" 5560 }, 5561 { 5562 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 5563 "Counter": "0,1,2,3", 5564 "CounterHTOff": "0,1,2,3", 5565 "Deprecated": "1", 5566 "EventCode": "0xB7, 0xBB", 5567 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 5568 "MSRIndex": "0x1a6,0x1a7", 5569 "MSRValue": "0x043C000120", 5570 "Offcore": "1", 5571 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5572 "SampleAfterValue": "100003", 5573 "UMask": "0x1" 5574 }, 5575 { 5576 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", 5577 "Counter": "0,1,2,3", 5578 "CounterHTOff": "0,1,2,3", 5579 "Deprecated": "1", 5580 "EventCode": "0xB7, 0xBB", 5581 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", 5582 "MSRIndex": "0x1a6,0x1a7", 5583 "MSRValue": "0x013C000120", 5584 "Offcore": "1", 5585 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5586 "SampleAfterValue": "100003", 5587 "UMask": "0x1" 5588 }, 5589 { 5590 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 5591 "Counter": "0,1,2,3", 5592 "CounterHTOff": "0,1,2,3", 5593 "Deprecated": "1", 5594 "EventCode": "0xB7, 0xBB", 5595 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 5596 "MSRIndex": "0x1a6,0x1a7", 5597 "MSRValue": "0x103FC00120", 5598 "Offcore": "1", 5599 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5600 "SampleAfterValue": "100003", 5601 "UMask": "0x1" 5602 }, 5603 { 5604 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5605 "Counter": "0,1,2,3", 5606 "CounterHTOff": "0,1,2,3", 5607 "Deprecated": "1", 5608 "EventCode": "0xB7, 0xBB", 5609 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 5610 "MSRIndex": "0x1a6,0x1a7", 5611 "MSRValue": "0x083FC00120", 5612 "Offcore": "1", 5613 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5614 "SampleAfterValue": "100003", 5615 "UMask": "0x1" 5616 }, 5617 { 5618 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", 5619 "Counter": "0,1,2,3", 5620 "CounterHTOff": "0,1,2,3", 5621 "Deprecated": "1", 5622 "EventCode": "0xB7, 0xBB", 5623 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS", 5624 "MSRIndex": "0x1a6,0x1a7", 5625 "MSRValue": "0x023C000120", 5626 "Offcore": "1", 5627 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5628 "SampleAfterValue": "100003", 5629 "UMask": "0x1" 5630 }, 5631 { 5632 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", 5633 "Counter": "0,1,2,3", 5634 "CounterHTOff": "0,1,2,3", 5635 "Deprecated": "1", 5636 "EventCode": "0xB7, 0xBB", 5637 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE", 5638 "MSRIndex": "0x1a6,0x1a7", 5639 "MSRValue": "0x00BC000120", 5640 "Offcore": "1", 5641 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5642 "SampleAfterValue": "100003", 5643 "UMask": "0x1" 5644 }, 5645 { 5646 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5647 "Counter": "0,1,2,3", 5648 "CounterHTOff": "0,1,2,3", 5649 "Deprecated": "1", 5650 "EventCode": "0xB7, 0xBB", 5651 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5652 "MSRIndex": "0x1a6,0x1a7", 5653 "MSRValue": "0x3F84000120", 5654 "Offcore": "1", 5655 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5656 "SampleAfterValue": "100003", 5657 "UMask": "0x1" 5658 }, 5659 { 5660 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 5661 "Counter": "0,1,2,3", 5662 "CounterHTOff": "0,1,2,3", 5663 "Deprecated": "1", 5664 "EventCode": "0xB7, 0xBB", 5665 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 5666 "MSRIndex": "0x1a6,0x1a7", 5667 "MSRValue": "0x1004000120", 5668 "Offcore": "1", 5669 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5670 "SampleAfterValue": "100003", 5671 "UMask": "0x1" 5672 }, 5673 { 5674 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 5675 "Counter": "0,1,2,3", 5676 "CounterHTOff": "0,1,2,3", 5677 "Deprecated": "1", 5678 "EventCode": "0xB7, 0xBB", 5679 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 5680 "MSRIndex": "0x1a6,0x1a7", 5681 "MSRValue": "0x0804000120", 5682 "Offcore": "1", 5683 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5684 "SampleAfterValue": "100003", 5685 "UMask": "0x1" 5686 }, 5687 { 5688 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 5689 "Counter": "0,1,2,3", 5690 "CounterHTOff": "0,1,2,3", 5691 "Deprecated": "1", 5692 "EventCode": "0xB7, 0xBB", 5693 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 5694 "MSRIndex": "0x1a6,0x1a7", 5695 "MSRValue": "0x0404000120", 5696 "Offcore": "1", 5697 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5698 "SampleAfterValue": "100003", 5699 "UMask": "0x1" 5700 }, 5701 { 5702 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5703 "Counter": "0,1,2,3", 5704 "CounterHTOff": "0,1,2,3", 5705 "Deprecated": "1", 5706 "EventCode": "0xB7, 0xBB", 5707 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 5708 "MSRIndex": "0x1a6,0x1a7", 5709 "MSRValue": "0x0104000120", 5710 "Offcore": "1", 5711 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5712 "SampleAfterValue": "100003", 5713 "UMask": "0x1" 5714 }, 5715 { 5716 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5717 "Counter": "0,1,2,3", 5718 "CounterHTOff": "0,1,2,3", 5719 "Deprecated": "1", 5720 "EventCode": "0xB7, 0xBB", 5721 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 5722 "MSRIndex": "0x1a6,0x1a7", 5723 "MSRValue": "0x0204000120", 5724 "Offcore": "1", 5725 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5726 "SampleAfterValue": "100003", 5727 "UMask": "0x1" 5728 }, 5729 { 5730 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 5731 "Counter": "0,1,2,3", 5732 "CounterHTOff": "0,1,2,3", 5733 "Deprecated": "1", 5734 "EventCode": "0xB7, 0xBB", 5735 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 5736 "MSRIndex": "0x1a6,0x1a7", 5737 "MSRValue": "0x0604000120", 5738 "Offcore": "1", 5739 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5740 "SampleAfterValue": "100003", 5741 "UMask": "0x1" 5742 }, 5743 { 5744 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5745 "Counter": "0,1,2,3", 5746 "CounterHTOff": "0,1,2,3", 5747 "Deprecated": "1", 5748 "EventCode": "0xB7, 0xBB", 5749 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 5750 "MSRIndex": "0x1a6,0x1a7", 5751 "MSRValue": "0x0084000120", 5752 "Offcore": "1", 5753 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5754 "SampleAfterValue": "100003", 5755 "UMask": "0x1" 5756 }, 5757 { 5758 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 5759 "Counter": "0,1,2,3", 5760 "CounterHTOff": "0,1,2,3", 5761 "Deprecated": "1", 5762 "EventCode": "0xB7, 0xBB", 5763 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 5764 "MSRIndex": "0x1a6,0x1a7", 5765 "MSRValue": "0x063B800120", 5766 "Offcore": "1", 5767 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5768 "SampleAfterValue": "100003", 5769 "UMask": "0x1" 5770 }, 5771 { 5772 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 5773 "Counter": "0,1,2,3", 5774 "CounterHTOff": "0,1,2,3", 5775 "Deprecated": "1", 5776 "EventCode": "0xB7, 0xBB", 5777 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 5778 "MSRIndex": "0x1a6,0x1a7", 5779 "MSRValue": "0x3F90000120", 5780 "Offcore": "1", 5781 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5782 "SampleAfterValue": "100003", 5783 "UMask": "0x1" 5784 }, 5785 { 5786 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 5787 "Counter": "0,1,2,3", 5788 "CounterHTOff": "0,1,2,3", 5789 "Deprecated": "1", 5790 "EventCode": "0xB7, 0xBB", 5791 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 5792 "MSRIndex": "0x1a6,0x1a7", 5793 "MSRValue": "0x1010000120", 5794 "Offcore": "1", 5795 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5796 "SampleAfterValue": "100003", 5797 "UMask": "0x1" 5798 }, 5799 { 5800 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 5801 "Counter": "0,1,2,3", 5802 "CounterHTOff": "0,1,2,3", 5803 "Deprecated": "1", 5804 "EventCode": "0xB7, 0xBB", 5805 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 5806 "MSRIndex": "0x1a6,0x1a7", 5807 "MSRValue": "0x0810000120", 5808 "Offcore": "1", 5809 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5810 "SampleAfterValue": "100003", 5811 "UMask": "0x1" 5812 }, 5813 { 5814 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 5815 "Counter": "0,1,2,3", 5816 "CounterHTOff": "0,1,2,3", 5817 "Deprecated": "1", 5818 "EventCode": "0xB7, 0xBB", 5819 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 5820 "MSRIndex": "0x1a6,0x1a7", 5821 "MSRValue": "0x0410000120", 5822 "Offcore": "1", 5823 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5824 "SampleAfterValue": "100003", 5825 "UMask": "0x1" 5826 }, 5827 { 5828 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 5829 "Counter": "0,1,2,3", 5830 "CounterHTOff": "0,1,2,3", 5831 "Deprecated": "1", 5832 "EventCode": "0xB7, 0xBB", 5833 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 5834 "MSRIndex": "0x1a6,0x1a7", 5835 "MSRValue": "0x0110000120", 5836 "Offcore": "1", 5837 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5838 "SampleAfterValue": "100003", 5839 "UMask": "0x1" 5840 }, 5841 { 5842 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 5843 "Counter": "0,1,2,3", 5844 "CounterHTOff": "0,1,2,3", 5845 "Deprecated": "1", 5846 "EventCode": "0xB7, 0xBB", 5847 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 5848 "MSRIndex": "0x1a6,0x1a7", 5849 "MSRValue": "0x0210000120", 5850 "Offcore": "1", 5851 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5852 "SampleAfterValue": "100003", 5853 "UMask": "0x1" 5854 }, 5855 { 5856 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 5857 "Counter": "0,1,2,3", 5858 "CounterHTOff": "0,1,2,3", 5859 "Deprecated": "1", 5860 "EventCode": "0xB7, 0xBB", 5861 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 5862 "MSRIndex": "0x1a6,0x1a7", 5863 "MSRValue": "0x0090000120", 5864 "Offcore": "1", 5865 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5866 "SampleAfterValue": "100003", 5867 "UMask": "0x1" 5868 }, 5869 { 5870 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP", 5871 "Counter": "0,1,2,3", 5872 "CounterHTOff": "0,1,2,3", 5873 "Deprecated": "1", 5874 "EventCode": "0xB7, 0xBB", 5875 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_SNOOP", 5876 "MSRIndex": "0x1a6,0x1a7", 5877 "MSRValue": "0x3FBC0007F7", 5878 "Offcore": "1", 5879 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5880 "SampleAfterValue": "100003", 5881 "UMask": "0x1" 5882 }, 5883 { 5884 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", 5885 "Counter": "0,1,2,3", 5886 "CounterHTOff": "0,1,2,3", 5887 "Deprecated": "1", 5888 "EventCode": "0xB7, 0xBB", 5889 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HITM_OTHER_CORE", 5890 "MSRIndex": "0x1a6,0x1a7", 5891 "MSRValue": "0x103C0007F7", 5892 "Offcore": "1", 5893 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5894 "SampleAfterValue": "100003", 5895 "UMask": "0x1" 5896 }, 5897 { 5898 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", 5899 "Counter": "0,1,2,3", 5900 "CounterHTOff": "0,1,2,3", 5901 "Deprecated": "1", 5902 "EventCode": "0xB7, 0xBB", 5903 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", 5904 "MSRIndex": "0x1a6,0x1a7", 5905 "MSRValue": "0x083C0007F7", 5906 "Offcore": "1", 5907 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5908 "SampleAfterValue": "100003", 5909 "UMask": "0x1" 5910 }, 5911 { 5912 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", 5913 "Counter": "0,1,2,3", 5914 "CounterHTOff": "0,1,2,3", 5915 "Deprecated": "1", 5916 "EventCode": "0xB7, 0xBB", 5917 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", 5918 "MSRIndex": "0x1a6,0x1a7", 5919 "MSRValue": "0x043C0007F7", 5920 "Offcore": "1", 5921 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5922 "SampleAfterValue": "100003", 5923 "UMask": "0x1" 5924 }, 5925 { 5926 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", 5927 "Counter": "0,1,2,3", 5928 "CounterHTOff": "0,1,2,3", 5929 "Deprecated": "1", 5930 "EventCode": "0xB7, 0xBB", 5931 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", 5932 "MSRIndex": "0x1a6,0x1a7", 5933 "MSRValue": "0x013C0007F7", 5934 "Offcore": "1", 5935 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5936 "SampleAfterValue": "100003", 5937 "UMask": "0x1" 5938 }, 5939 { 5940 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM", 5941 "Counter": "0,1,2,3", 5942 "CounterHTOff": "0,1,2,3", 5943 "Deprecated": "1", 5944 "EventCode": "0xB7, 0xBB", 5945 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.REMOTE_HITM", 5946 "MSRIndex": "0x1a6,0x1a7", 5947 "MSRValue": "0x103FC007F7", 5948 "Offcore": "1", 5949 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5950 "SampleAfterValue": "100003", 5951 "UMask": "0x1" 5952 }, 5953 { 5954 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", 5955 "Counter": "0,1,2,3", 5956 "CounterHTOff": "0,1,2,3", 5957 "Deprecated": "1", 5958 "EventCode": "0xB7, 0xBB", 5959 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", 5960 "MSRIndex": "0x1a6,0x1a7", 5961 "MSRValue": "0x083FC007F7", 5962 "Offcore": "1", 5963 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5964 "SampleAfterValue": "100003", 5965 "UMask": "0x1" 5966 }, 5967 { 5968 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS", 5969 "Counter": "0,1,2,3", 5970 "CounterHTOff": "0,1,2,3", 5971 "Deprecated": "1", 5972 "EventCode": "0xB7, 0xBB", 5973 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_MISS", 5974 "MSRIndex": "0x1a6,0x1a7", 5975 "MSRValue": "0x023C0007F7", 5976 "Offcore": "1", 5977 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5978 "SampleAfterValue": "100003", 5979 "UMask": "0x1" 5980 }, 5981 { 5982 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE", 5983 "Counter": "0,1,2,3", 5984 "CounterHTOff": "0,1,2,3", 5985 "Deprecated": "1", 5986 "EventCode": "0xB7, 0xBB", 5987 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_NONE", 5988 "MSRIndex": "0x1a6,0x1a7", 5989 "MSRValue": "0x00BC0007F7", 5990 "Offcore": "1", 5991 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5992 "SampleAfterValue": "100003", 5993 "UMask": "0x1" 5994 }, 5995 { 5996 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 5997 "Counter": "0,1,2,3", 5998 "CounterHTOff": "0,1,2,3", 5999 "Deprecated": "1", 6000 "EventCode": "0xB7, 0xBB", 6001 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6002 "MSRIndex": "0x1a6,0x1a7", 6003 "MSRValue": "0x3F840007F7", 6004 "Offcore": "1", 6005 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6006 "SampleAfterValue": "100003", 6007 "UMask": "0x1" 6008 }, 6009 { 6010 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6011 "Counter": "0,1,2,3", 6012 "CounterHTOff": "0,1,2,3", 6013 "Deprecated": "1", 6014 "EventCode": "0xB7, 0xBB", 6015 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6016 "MSRIndex": "0x1a6,0x1a7", 6017 "MSRValue": "0x10040007F7", 6018 "Offcore": "1", 6019 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6020 "SampleAfterValue": "100003", 6021 "UMask": "0x1" 6022 }, 6023 { 6024 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6025 "Counter": "0,1,2,3", 6026 "CounterHTOff": "0,1,2,3", 6027 "Deprecated": "1", 6028 "EventCode": "0xB7, 0xBB", 6029 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6030 "MSRIndex": "0x1a6,0x1a7", 6031 "MSRValue": "0x08040007F7", 6032 "Offcore": "1", 6033 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6034 "SampleAfterValue": "100003", 6035 "UMask": "0x1" 6036 }, 6037 { 6038 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6039 "Counter": "0,1,2,3", 6040 "CounterHTOff": "0,1,2,3", 6041 "Deprecated": "1", 6042 "EventCode": "0xB7, 0xBB", 6043 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6044 "MSRIndex": "0x1a6,0x1a7", 6045 "MSRValue": "0x04040007F7", 6046 "Offcore": "1", 6047 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6048 "SampleAfterValue": "100003", 6049 "UMask": "0x1" 6050 }, 6051 { 6052 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6053 "Counter": "0,1,2,3", 6054 "CounterHTOff": "0,1,2,3", 6055 "Deprecated": "1", 6056 "EventCode": "0xB7, 0xBB", 6057 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6058 "MSRIndex": "0x1a6,0x1a7", 6059 "MSRValue": "0x01040007F7", 6060 "Offcore": "1", 6061 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6062 "SampleAfterValue": "100003", 6063 "UMask": "0x1" 6064 }, 6065 { 6066 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6067 "Counter": "0,1,2,3", 6068 "CounterHTOff": "0,1,2,3", 6069 "Deprecated": "1", 6070 "EventCode": "0xB7, 0xBB", 6071 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6072 "MSRIndex": "0x1a6,0x1a7", 6073 "MSRValue": "0x02040007F7", 6074 "Offcore": "1", 6075 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6076 "SampleAfterValue": "100003", 6077 "UMask": "0x1" 6078 }, 6079 { 6080 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 6081 "Counter": "0,1,2,3", 6082 "CounterHTOff": "0,1,2,3", 6083 "Deprecated": "1", 6084 "EventCode": "0xB7, 0xBB", 6085 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 6086 "MSRIndex": "0x1a6,0x1a7", 6087 "MSRValue": "0x06040007F7", 6088 "Offcore": "1", 6089 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6090 "SampleAfterValue": "100003", 6091 "UMask": "0x1" 6092 }, 6093 { 6094 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6095 "Counter": "0,1,2,3", 6096 "CounterHTOff": "0,1,2,3", 6097 "Deprecated": "1", 6098 "EventCode": "0xB7, 0xBB", 6099 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6100 "MSRIndex": "0x1a6,0x1a7", 6101 "MSRValue": "0x00840007F7", 6102 "Offcore": "1", 6103 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6104 "SampleAfterValue": "100003", 6105 "UMask": "0x1" 6106 }, 6107 { 6108 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 6109 "Counter": "0,1,2,3", 6110 "CounterHTOff": "0,1,2,3", 6111 "Deprecated": "1", 6112 "EventCode": "0xB7, 0xBB", 6113 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 6114 "MSRIndex": "0x1a6,0x1a7", 6115 "MSRValue": "0x063B8007F7", 6116 "Offcore": "1", 6117 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6118 "SampleAfterValue": "100003", 6119 "UMask": "0x1" 6120 }, 6121 { 6122 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6123 "Counter": "0,1,2,3", 6124 "CounterHTOff": "0,1,2,3", 6125 "Deprecated": "1", 6126 "EventCode": "0xB7, 0xBB", 6127 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6128 "MSRIndex": "0x1a6,0x1a7", 6129 "MSRValue": "0x3F900007F7", 6130 "Offcore": "1", 6131 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6132 "SampleAfterValue": "100003", 6133 "UMask": "0x1" 6134 }, 6135 { 6136 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6137 "Counter": "0,1,2,3", 6138 "CounterHTOff": "0,1,2,3", 6139 "Deprecated": "1", 6140 "EventCode": "0xB7, 0xBB", 6141 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6142 "MSRIndex": "0x1a6,0x1a7", 6143 "MSRValue": "0x10100007F7", 6144 "Offcore": "1", 6145 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6146 "SampleAfterValue": "100003", 6147 "UMask": "0x1" 6148 }, 6149 { 6150 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6151 "Counter": "0,1,2,3", 6152 "CounterHTOff": "0,1,2,3", 6153 "Deprecated": "1", 6154 "EventCode": "0xB7, 0xBB", 6155 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6156 "MSRIndex": "0x1a6,0x1a7", 6157 "MSRValue": "0x08100007F7", 6158 "Offcore": "1", 6159 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6160 "SampleAfterValue": "100003", 6161 "UMask": "0x1" 6162 }, 6163 { 6164 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6165 "Counter": "0,1,2,3", 6166 "CounterHTOff": "0,1,2,3", 6167 "Deprecated": "1", 6168 "EventCode": "0xB7, 0xBB", 6169 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6170 "MSRIndex": "0x1a6,0x1a7", 6171 "MSRValue": "0x04100007F7", 6172 "Offcore": "1", 6173 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6174 "SampleAfterValue": "100003", 6175 "UMask": "0x1" 6176 }, 6177 { 6178 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6179 "Counter": "0,1,2,3", 6180 "CounterHTOff": "0,1,2,3", 6181 "Deprecated": "1", 6182 "EventCode": "0xB7, 0xBB", 6183 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6184 "MSRIndex": "0x1a6,0x1a7", 6185 "MSRValue": "0x01100007F7", 6186 "Offcore": "1", 6187 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6188 "SampleAfterValue": "100003", 6189 "UMask": "0x1" 6190 }, 6191 { 6192 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6193 "Counter": "0,1,2,3", 6194 "CounterHTOff": "0,1,2,3", 6195 "Deprecated": "1", 6196 "EventCode": "0xB7, 0xBB", 6197 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6198 "MSRIndex": "0x1a6,0x1a7", 6199 "MSRValue": "0x02100007F7", 6200 "Offcore": "1", 6201 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6202 "SampleAfterValue": "100003", 6203 "UMask": "0x1" 6204 }, 6205 { 6206 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6207 "Counter": "0,1,2,3", 6208 "CounterHTOff": "0,1,2,3", 6209 "Deprecated": "1", 6210 "EventCode": "0xB7, 0xBB", 6211 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6212 "MSRIndex": "0x1a6,0x1a7", 6213 "MSRValue": "0x00900007F7", 6214 "Offcore": "1", 6215 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6216 "SampleAfterValue": "100003", 6217 "UMask": "0x1" 6218 }, 6219 { 6220 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP", 6221 "Counter": "0,1,2,3", 6222 "CounterHTOff": "0,1,2,3", 6223 "Deprecated": "1", 6224 "EventCode": "0xB7, 0xBB", 6225 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", 6226 "MSRIndex": "0x1a6,0x1a7", 6227 "MSRValue": "0x3FBC000122", 6228 "Offcore": "1", 6229 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6230 "SampleAfterValue": "100003", 6231 "UMask": "0x1" 6232 }, 6233 { 6234 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", 6235 "Counter": "0,1,2,3", 6236 "CounterHTOff": "0,1,2,3", 6237 "Deprecated": "1", 6238 "EventCode": "0xB7, 0xBB", 6239 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HITM_OTHER_CORE", 6240 "MSRIndex": "0x1a6,0x1a7", 6241 "MSRValue": "0x103C000122", 6242 "Offcore": "1", 6243 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6244 "SampleAfterValue": "100003", 6245 "UMask": "0x1" 6246 }, 6247 { 6248 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 6249 "Counter": "0,1,2,3", 6250 "CounterHTOff": "0,1,2,3", 6251 "Deprecated": "1", 6252 "EventCode": "0xB7, 0xBB", 6253 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 6254 "MSRIndex": "0x1a6,0x1a7", 6255 "MSRValue": "0x083C000122", 6256 "Offcore": "1", 6257 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6258 "SampleAfterValue": "100003", 6259 "UMask": "0x1" 6260 }, 6261 { 6262 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6263 "Counter": "0,1,2,3", 6264 "CounterHTOff": "0,1,2,3", 6265 "Deprecated": "1", 6266 "EventCode": "0xB7, 0xBB", 6267 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6268 "MSRIndex": "0x1a6,0x1a7", 6269 "MSRValue": "0x043C000122", 6270 "Offcore": "1", 6271 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6272 "SampleAfterValue": "100003", 6273 "UMask": "0x1" 6274 }, 6275 { 6276 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", 6277 "Counter": "0,1,2,3", 6278 "CounterHTOff": "0,1,2,3", 6279 "Deprecated": "1", 6280 "EventCode": "0xB7, 0xBB", 6281 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", 6282 "MSRIndex": "0x1a6,0x1a7", 6283 "MSRValue": "0x013C000122", 6284 "Offcore": "1", 6285 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6286 "SampleAfterValue": "100003", 6287 "UMask": "0x1" 6288 }, 6289 { 6290 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM", 6291 "Counter": "0,1,2,3", 6292 "CounterHTOff": "0,1,2,3", 6293 "Deprecated": "1", 6294 "EventCode": "0xB7, 0xBB", 6295 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", 6296 "MSRIndex": "0x1a6,0x1a7", 6297 "MSRValue": "0x103FC00122", 6298 "Offcore": "1", 6299 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6300 "SampleAfterValue": "100003", 6301 "UMask": "0x1" 6302 }, 6303 { 6304 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 6305 "Counter": "0,1,2,3", 6306 "CounterHTOff": "0,1,2,3", 6307 "Deprecated": "1", 6308 "EventCode": "0xB7, 0xBB", 6309 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 6310 "MSRIndex": "0x1a6,0x1a7", 6311 "MSRValue": "0x083FC00122", 6312 "Offcore": "1", 6313 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6314 "SampleAfterValue": "100003", 6315 "UMask": "0x1" 6316 }, 6317 { 6318 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS", 6319 "Counter": "0,1,2,3", 6320 "CounterHTOff": "0,1,2,3", 6321 "Deprecated": "1", 6322 "EventCode": "0xB7, 0xBB", 6323 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", 6324 "MSRIndex": "0x1a6,0x1a7", 6325 "MSRValue": "0x023C000122", 6326 "Offcore": "1", 6327 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6328 "SampleAfterValue": "100003", 6329 "UMask": "0x1" 6330 }, 6331 { 6332 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE", 6333 "Counter": "0,1,2,3", 6334 "CounterHTOff": "0,1,2,3", 6335 "Deprecated": "1", 6336 "EventCode": "0xB7, 0xBB", 6337 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", 6338 "MSRIndex": "0x1a6,0x1a7", 6339 "MSRValue": "0x00BC000122", 6340 "Offcore": "1", 6341 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6342 "SampleAfterValue": "100003", 6343 "UMask": "0x1" 6344 }, 6345 { 6346 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6347 "Counter": "0,1,2,3", 6348 "CounterHTOff": "0,1,2,3", 6349 "Deprecated": "1", 6350 "EventCode": "0xB7, 0xBB", 6351 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6352 "MSRIndex": "0x1a6,0x1a7", 6353 "MSRValue": "0x3F84000122", 6354 "Offcore": "1", 6355 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6356 "SampleAfterValue": "100003", 6357 "UMask": "0x1" 6358 }, 6359 { 6360 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6361 "Counter": "0,1,2,3", 6362 "CounterHTOff": "0,1,2,3", 6363 "Deprecated": "1", 6364 "EventCode": "0xB7, 0xBB", 6365 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6366 "MSRIndex": "0x1a6,0x1a7", 6367 "MSRValue": "0x1004000122", 6368 "Offcore": "1", 6369 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6370 "SampleAfterValue": "100003", 6371 "UMask": "0x1" 6372 }, 6373 { 6374 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6375 "Counter": "0,1,2,3", 6376 "CounterHTOff": "0,1,2,3", 6377 "Deprecated": "1", 6378 "EventCode": "0xB7, 0xBB", 6379 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6380 "MSRIndex": "0x1a6,0x1a7", 6381 "MSRValue": "0x0804000122", 6382 "Offcore": "1", 6383 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6384 "SampleAfterValue": "100003", 6385 "UMask": "0x1" 6386 }, 6387 { 6388 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6389 "Counter": "0,1,2,3", 6390 "CounterHTOff": "0,1,2,3", 6391 "Deprecated": "1", 6392 "EventCode": "0xB7, 0xBB", 6393 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6394 "MSRIndex": "0x1a6,0x1a7", 6395 "MSRValue": "0x0404000122", 6396 "Offcore": "1", 6397 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6398 "SampleAfterValue": "100003", 6399 "UMask": "0x1" 6400 }, 6401 { 6402 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6403 "Counter": "0,1,2,3", 6404 "CounterHTOff": "0,1,2,3", 6405 "Deprecated": "1", 6406 "EventCode": "0xB7, 0xBB", 6407 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6408 "MSRIndex": "0x1a6,0x1a7", 6409 "MSRValue": "0x0104000122", 6410 "Offcore": "1", 6411 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6412 "SampleAfterValue": "100003", 6413 "UMask": "0x1" 6414 }, 6415 { 6416 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6417 "Counter": "0,1,2,3", 6418 "CounterHTOff": "0,1,2,3", 6419 "Deprecated": "1", 6420 "EventCode": "0xB7, 0xBB", 6421 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6422 "MSRIndex": "0x1a6,0x1a7", 6423 "MSRValue": "0x0204000122", 6424 "Offcore": "1", 6425 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6426 "SampleAfterValue": "100003", 6427 "UMask": "0x1" 6428 }, 6429 { 6430 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 6431 "Counter": "0,1,2,3", 6432 "CounterHTOff": "0,1,2,3", 6433 "Deprecated": "1", 6434 "EventCode": "0xB7, 0xBB", 6435 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 6436 "MSRIndex": "0x1a6,0x1a7", 6437 "MSRValue": "0x0604000122", 6438 "Offcore": "1", 6439 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6440 "SampleAfterValue": "100003", 6441 "UMask": "0x1" 6442 }, 6443 { 6444 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6445 "Counter": "0,1,2,3", 6446 "CounterHTOff": "0,1,2,3", 6447 "Deprecated": "1", 6448 "EventCode": "0xB7, 0xBB", 6449 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6450 "MSRIndex": "0x1a6,0x1a7", 6451 "MSRValue": "0x0084000122", 6452 "Offcore": "1", 6453 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6454 "SampleAfterValue": "100003", 6455 "UMask": "0x1" 6456 }, 6457 { 6458 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 6459 "Counter": "0,1,2,3", 6460 "CounterHTOff": "0,1,2,3", 6461 "Deprecated": "1", 6462 "EventCode": "0xB7, 0xBB", 6463 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 6464 "MSRIndex": "0x1a6,0x1a7", 6465 "MSRValue": "0x063B800122", 6466 "Offcore": "1", 6467 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6468 "SampleAfterValue": "100003", 6469 "UMask": "0x1" 6470 }, 6471 { 6472 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6473 "Counter": "0,1,2,3", 6474 "CounterHTOff": "0,1,2,3", 6475 "Deprecated": "1", 6476 "EventCode": "0xB7, 0xBB", 6477 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6478 "MSRIndex": "0x1a6,0x1a7", 6479 "MSRValue": "0x3F90000122", 6480 "Offcore": "1", 6481 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6482 "SampleAfterValue": "100003", 6483 "UMask": "0x1" 6484 }, 6485 { 6486 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6487 "Counter": "0,1,2,3", 6488 "CounterHTOff": "0,1,2,3", 6489 "Deprecated": "1", 6490 "EventCode": "0xB7, 0xBB", 6491 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6492 "MSRIndex": "0x1a6,0x1a7", 6493 "MSRValue": "0x1010000122", 6494 "Offcore": "1", 6495 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6496 "SampleAfterValue": "100003", 6497 "UMask": "0x1" 6498 }, 6499 { 6500 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6501 "Counter": "0,1,2,3", 6502 "CounterHTOff": "0,1,2,3", 6503 "Deprecated": "1", 6504 "EventCode": "0xB7, 0xBB", 6505 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6506 "MSRIndex": "0x1a6,0x1a7", 6507 "MSRValue": "0x0810000122", 6508 "Offcore": "1", 6509 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6510 "SampleAfterValue": "100003", 6511 "UMask": "0x1" 6512 }, 6513 { 6514 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6515 "Counter": "0,1,2,3", 6516 "CounterHTOff": "0,1,2,3", 6517 "Deprecated": "1", 6518 "EventCode": "0xB7, 0xBB", 6519 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6520 "MSRIndex": "0x1a6,0x1a7", 6521 "MSRValue": "0x0410000122", 6522 "Offcore": "1", 6523 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6524 "SampleAfterValue": "100003", 6525 "UMask": "0x1" 6526 }, 6527 { 6528 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6529 "Counter": "0,1,2,3", 6530 "CounterHTOff": "0,1,2,3", 6531 "Deprecated": "1", 6532 "EventCode": "0xB7, 0xBB", 6533 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6534 "MSRIndex": "0x1a6,0x1a7", 6535 "MSRValue": "0x0110000122", 6536 "Offcore": "1", 6537 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6538 "SampleAfterValue": "100003", 6539 "UMask": "0x1" 6540 }, 6541 { 6542 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6543 "Counter": "0,1,2,3", 6544 "CounterHTOff": "0,1,2,3", 6545 "Deprecated": "1", 6546 "EventCode": "0xB7, 0xBB", 6547 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6548 "MSRIndex": "0x1a6,0x1a7", 6549 "MSRValue": "0x0210000122", 6550 "Offcore": "1", 6551 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6552 "SampleAfterValue": "100003", 6553 "UMask": "0x1" 6554 }, 6555 { 6556 "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6557 "Counter": "0,1,2,3", 6558 "CounterHTOff": "0,1,2,3", 6559 "Deprecated": "1", 6560 "EventCode": "0xB7, 0xBB", 6561 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6562 "MSRIndex": "0x1a6,0x1a7", 6563 "MSRValue": "0x0090000122", 6564 "Offcore": "1", 6565 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6566 "SampleAfterValue": "100003", 6567 "UMask": "0x1" 6568 }, 6569 { 6570 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 6571 "Counter": "0,1,2,3", 6572 "CounterHTOff": "0,1,2,3", 6573 "Deprecated": "1", 6574 "EventCode": "0xB7, 0xBB", 6575 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 6576 "MSRIndex": "0x1a6,0x1a7", 6577 "MSRValue": "0x3FBC000004", 6578 "Offcore": "1", 6579 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6580 "SampleAfterValue": "100003", 6581 "UMask": "0x1" 6582 }, 6583 { 6584 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", 6585 "Counter": "0,1,2,3", 6586 "CounterHTOff": "0,1,2,3", 6587 "Deprecated": "1", 6588 "EventCode": "0xB7, 0xBB", 6589 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", 6590 "MSRIndex": "0x1a6,0x1a7", 6591 "MSRValue": "0x103C000004", 6592 "Offcore": "1", 6593 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6594 "SampleAfterValue": "100003", 6595 "UMask": "0x1" 6596 }, 6597 { 6598 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", 6599 "Counter": "0,1,2,3", 6600 "CounterHTOff": "0,1,2,3", 6601 "Deprecated": "1", 6602 "EventCode": "0xB7, 0xBB", 6603 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", 6604 "MSRIndex": "0x1a6,0x1a7", 6605 "MSRValue": "0x083C000004", 6606 "Offcore": "1", 6607 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6608 "SampleAfterValue": "100003", 6609 "UMask": "0x1" 6610 }, 6611 { 6612 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6613 "Counter": "0,1,2,3", 6614 "CounterHTOff": "0,1,2,3", 6615 "Deprecated": "1", 6616 "EventCode": "0xB7, 0xBB", 6617 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6618 "MSRIndex": "0x1a6,0x1a7", 6619 "MSRValue": "0x043C000004", 6620 "Offcore": "1", 6621 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6622 "SampleAfterValue": "100003", 6623 "UMask": "0x1" 6624 }, 6625 { 6626 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", 6627 "Counter": "0,1,2,3", 6628 "CounterHTOff": "0,1,2,3", 6629 "Deprecated": "1", 6630 "EventCode": "0xB7, 0xBB", 6631 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", 6632 "MSRIndex": "0x1a6,0x1a7", 6633 "MSRValue": "0x013C000004", 6634 "Offcore": "1", 6635 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6636 "SampleAfterValue": "100003", 6637 "UMask": "0x1" 6638 }, 6639 { 6640 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 6641 "Counter": "0,1,2,3", 6642 "CounterHTOff": "0,1,2,3", 6643 "Deprecated": "1", 6644 "EventCode": "0xB7, 0xBB", 6645 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 6646 "MSRIndex": "0x1a6,0x1a7", 6647 "MSRValue": "0x103FC00004", 6648 "Offcore": "1", 6649 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6650 "SampleAfterValue": "100003", 6651 "UMask": "0x1" 6652 }, 6653 { 6654 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 6655 "Counter": "0,1,2,3", 6656 "CounterHTOff": "0,1,2,3", 6657 "Deprecated": "1", 6658 "EventCode": "0xB7, 0xBB", 6659 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 6660 "MSRIndex": "0x1a6,0x1a7", 6661 "MSRValue": "0x083FC00004", 6662 "Offcore": "1", 6663 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6664 "SampleAfterValue": "100003", 6665 "UMask": "0x1" 6666 }, 6667 { 6668 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 6669 "Counter": "0,1,2,3", 6670 "CounterHTOff": "0,1,2,3", 6671 "Deprecated": "1", 6672 "EventCode": "0xB7, 0xBB", 6673 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 6674 "MSRIndex": "0x1a6,0x1a7", 6675 "MSRValue": "0x023C000004", 6676 "Offcore": "1", 6677 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6678 "SampleAfterValue": "100003", 6679 "UMask": "0x1" 6680 }, 6681 { 6682 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 6683 "Counter": "0,1,2,3", 6684 "CounterHTOff": "0,1,2,3", 6685 "Deprecated": "1", 6686 "EventCode": "0xB7, 0xBB", 6687 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 6688 "MSRIndex": "0x1a6,0x1a7", 6689 "MSRValue": "0x00BC000004", 6690 "Offcore": "1", 6691 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6692 "SampleAfterValue": "100003", 6693 "UMask": "0x1" 6694 }, 6695 { 6696 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6697 "Counter": "0,1,2,3", 6698 "CounterHTOff": "0,1,2,3", 6699 "Deprecated": "1", 6700 "EventCode": "0xB7, 0xBB", 6701 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 6702 "MSRIndex": "0x1a6,0x1a7", 6703 "MSRValue": "0x3F84000004", 6704 "Offcore": "1", 6705 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6706 "SampleAfterValue": "100003", 6707 "UMask": "0x1" 6708 }, 6709 { 6710 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6711 "Counter": "0,1,2,3", 6712 "CounterHTOff": "0,1,2,3", 6713 "Deprecated": "1", 6714 "EventCode": "0xB7, 0xBB", 6715 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 6716 "MSRIndex": "0x1a6,0x1a7", 6717 "MSRValue": "0x1004000004", 6718 "Offcore": "1", 6719 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6720 "SampleAfterValue": "100003", 6721 "UMask": "0x1" 6722 }, 6723 { 6724 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6725 "Counter": "0,1,2,3", 6726 "CounterHTOff": "0,1,2,3", 6727 "Deprecated": "1", 6728 "EventCode": "0xB7, 0xBB", 6729 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 6730 "MSRIndex": "0x1a6,0x1a7", 6731 "MSRValue": "0x0804000004", 6732 "Offcore": "1", 6733 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6734 "SampleAfterValue": "100003", 6735 "UMask": "0x1" 6736 }, 6737 { 6738 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6739 "Counter": "0,1,2,3", 6740 "CounterHTOff": "0,1,2,3", 6741 "Deprecated": "1", 6742 "EventCode": "0xB7, 0xBB", 6743 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 6744 "MSRIndex": "0x1a6,0x1a7", 6745 "MSRValue": "0x0404000004", 6746 "Offcore": "1", 6747 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6748 "SampleAfterValue": "100003", 6749 "UMask": "0x1" 6750 }, 6751 { 6752 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6753 "Counter": "0,1,2,3", 6754 "CounterHTOff": "0,1,2,3", 6755 "Deprecated": "1", 6756 "EventCode": "0xB7, 0xBB", 6757 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 6758 "MSRIndex": "0x1a6,0x1a7", 6759 "MSRValue": "0x0104000004", 6760 "Offcore": "1", 6761 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6762 "SampleAfterValue": "100003", 6763 "UMask": "0x1" 6764 }, 6765 { 6766 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6767 "Counter": "0,1,2,3", 6768 "CounterHTOff": "0,1,2,3", 6769 "Deprecated": "1", 6770 "EventCode": "0xB7, 0xBB", 6771 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 6772 "MSRIndex": "0x1a6,0x1a7", 6773 "MSRValue": "0x0204000004", 6774 "Offcore": "1", 6775 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6776 "SampleAfterValue": "100003", 6777 "UMask": "0x1" 6778 }, 6779 { 6780 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 6781 "Counter": "0,1,2,3", 6782 "CounterHTOff": "0,1,2,3", 6783 "Deprecated": "1", 6784 "EventCode": "0xB7, 0xBB", 6785 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 6786 "MSRIndex": "0x1a6,0x1a7", 6787 "MSRValue": "0x0604000004", 6788 "Offcore": "1", 6789 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6790 "SampleAfterValue": "100003", 6791 "UMask": "0x1" 6792 }, 6793 { 6794 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6795 "Counter": "0,1,2,3", 6796 "CounterHTOff": "0,1,2,3", 6797 "Deprecated": "1", 6798 "EventCode": "0xB7, 0xBB", 6799 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 6800 "MSRIndex": "0x1a6,0x1a7", 6801 "MSRValue": "0x0084000004", 6802 "Offcore": "1", 6803 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6804 "SampleAfterValue": "100003", 6805 "UMask": "0x1" 6806 }, 6807 { 6808 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 6809 "Counter": "0,1,2,3", 6810 "CounterHTOff": "0,1,2,3", 6811 "Deprecated": "1", 6812 "EventCode": "0xB7, 0xBB", 6813 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 6814 "MSRIndex": "0x1a6,0x1a7", 6815 "MSRValue": "0x063B800004", 6816 "Offcore": "1", 6817 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6818 "SampleAfterValue": "100003", 6819 "UMask": "0x1" 6820 }, 6821 { 6822 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6823 "Counter": "0,1,2,3", 6824 "CounterHTOff": "0,1,2,3", 6825 "Deprecated": "1", 6826 "EventCode": "0xB7, 0xBB", 6827 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 6828 "MSRIndex": "0x1a6,0x1a7", 6829 "MSRValue": "0x3F90000004", 6830 "Offcore": "1", 6831 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6832 "SampleAfterValue": "100003", 6833 "UMask": "0x1" 6834 }, 6835 { 6836 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6837 "Counter": "0,1,2,3", 6838 "CounterHTOff": "0,1,2,3", 6839 "Deprecated": "1", 6840 "EventCode": "0xB7, 0xBB", 6841 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 6842 "MSRIndex": "0x1a6,0x1a7", 6843 "MSRValue": "0x1010000004", 6844 "Offcore": "1", 6845 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6846 "SampleAfterValue": "100003", 6847 "UMask": "0x1" 6848 }, 6849 { 6850 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6851 "Counter": "0,1,2,3", 6852 "CounterHTOff": "0,1,2,3", 6853 "Deprecated": "1", 6854 "EventCode": "0xB7, 0xBB", 6855 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 6856 "MSRIndex": "0x1a6,0x1a7", 6857 "MSRValue": "0x0810000004", 6858 "Offcore": "1", 6859 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6860 "SampleAfterValue": "100003", 6861 "UMask": "0x1" 6862 }, 6863 { 6864 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6865 "Counter": "0,1,2,3", 6866 "CounterHTOff": "0,1,2,3", 6867 "Deprecated": "1", 6868 "EventCode": "0xB7, 0xBB", 6869 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 6870 "MSRIndex": "0x1a6,0x1a7", 6871 "MSRValue": "0x0410000004", 6872 "Offcore": "1", 6873 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6874 "SampleAfterValue": "100003", 6875 "UMask": "0x1" 6876 }, 6877 { 6878 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6879 "Counter": "0,1,2,3", 6880 "CounterHTOff": "0,1,2,3", 6881 "Deprecated": "1", 6882 "EventCode": "0xB7, 0xBB", 6883 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 6884 "MSRIndex": "0x1a6,0x1a7", 6885 "MSRValue": "0x0110000004", 6886 "Offcore": "1", 6887 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6888 "SampleAfterValue": "100003", 6889 "UMask": "0x1" 6890 }, 6891 { 6892 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6893 "Counter": "0,1,2,3", 6894 "CounterHTOff": "0,1,2,3", 6895 "Deprecated": "1", 6896 "EventCode": "0xB7, 0xBB", 6897 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 6898 "MSRIndex": "0x1a6,0x1a7", 6899 "MSRValue": "0x0210000004", 6900 "Offcore": "1", 6901 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6902 "SampleAfterValue": "100003", 6903 "UMask": "0x1" 6904 }, 6905 { 6906 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6907 "Counter": "0,1,2,3", 6908 "CounterHTOff": "0,1,2,3", 6909 "Deprecated": "1", 6910 "EventCode": "0xB7, 0xBB", 6911 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 6912 "MSRIndex": "0x1a6,0x1a7", 6913 "MSRValue": "0x0090000004", 6914 "Offcore": "1", 6915 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6916 "SampleAfterValue": "100003", 6917 "UMask": "0x1" 6918 }, 6919 { 6920 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 6921 "Counter": "0,1,2,3", 6922 "CounterHTOff": "0,1,2,3", 6923 "Deprecated": "1", 6924 "EventCode": "0xB7, 0xBB", 6925 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 6926 "MSRIndex": "0x1a6,0x1a7", 6927 "MSRValue": "0x3FBC000001", 6928 "Offcore": "1", 6929 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6930 "SampleAfterValue": "100003", 6931 "UMask": "0x1" 6932 }, 6933 { 6934 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", 6935 "Counter": "0,1,2,3", 6936 "CounterHTOff": "0,1,2,3", 6937 "Deprecated": "1", 6938 "EventCode": "0xB7, 0xBB", 6939 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", 6940 "MSRIndex": "0x1a6,0x1a7", 6941 "MSRValue": "0x103C000001", 6942 "Offcore": "1", 6943 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6944 "SampleAfterValue": "100003", 6945 "UMask": "0x1" 6946 }, 6947 { 6948 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 6949 "Counter": "0,1,2,3", 6950 "CounterHTOff": "0,1,2,3", 6951 "Deprecated": "1", 6952 "EventCode": "0xB7, 0xBB", 6953 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 6954 "MSRIndex": "0x1a6,0x1a7", 6955 "MSRValue": "0x083C000001", 6956 "Offcore": "1", 6957 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6958 "SampleAfterValue": "100003", 6959 "UMask": "0x1" 6960 }, 6961 { 6962 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6963 "Counter": "0,1,2,3", 6964 "CounterHTOff": "0,1,2,3", 6965 "Deprecated": "1", 6966 "EventCode": "0xB7, 0xBB", 6967 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 6968 "MSRIndex": "0x1a6,0x1a7", 6969 "MSRValue": "0x043C000001", 6970 "Offcore": "1", 6971 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6972 "SampleAfterValue": "100003", 6973 "UMask": "0x1" 6974 }, 6975 { 6976 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 6977 "Counter": "0,1,2,3", 6978 "CounterHTOff": "0,1,2,3", 6979 "Deprecated": "1", 6980 "EventCode": "0xB7, 0xBB", 6981 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 6982 "MSRIndex": "0x1a6,0x1a7", 6983 "MSRValue": "0x013C000001", 6984 "Offcore": "1", 6985 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6986 "SampleAfterValue": "100003", 6987 "UMask": "0x1" 6988 }, 6989 { 6990 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 6991 "Counter": "0,1,2,3", 6992 "CounterHTOff": "0,1,2,3", 6993 "Deprecated": "1", 6994 "EventCode": "0xB7, 0xBB", 6995 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 6996 "MSRIndex": "0x1a6,0x1a7", 6997 "MSRValue": "0x103FC00001", 6998 "Offcore": "1", 6999 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7000 "SampleAfterValue": "100003", 7001 "UMask": "0x1" 7002 }, 7003 { 7004 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 7005 "Counter": "0,1,2,3", 7006 "CounterHTOff": "0,1,2,3", 7007 "Deprecated": "1", 7008 "EventCode": "0xB7, 0xBB", 7009 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 7010 "MSRIndex": "0x1a6,0x1a7", 7011 "MSRValue": "0x083FC00001", 7012 "Offcore": "1", 7013 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7014 "SampleAfterValue": "100003", 7015 "UMask": "0x1" 7016 }, 7017 { 7018 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 7019 "Counter": "0,1,2,3", 7020 "CounterHTOff": "0,1,2,3", 7021 "Deprecated": "1", 7022 "EventCode": "0xB7, 0xBB", 7023 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 7024 "MSRIndex": "0x1a6,0x1a7", 7025 "MSRValue": "0x023C000001", 7026 "Offcore": "1", 7027 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7028 "SampleAfterValue": "100003", 7029 "UMask": "0x1" 7030 }, 7031 { 7032 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 7033 "Counter": "0,1,2,3", 7034 "CounterHTOff": "0,1,2,3", 7035 "Deprecated": "1", 7036 "EventCode": "0xB7, 0xBB", 7037 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 7038 "MSRIndex": "0x1a6,0x1a7", 7039 "MSRValue": "0x00BC000001", 7040 "Offcore": "1", 7041 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7042 "SampleAfterValue": "100003", 7043 "UMask": "0x1" 7044 }, 7045 { 7046 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7047 "Counter": "0,1,2,3", 7048 "CounterHTOff": "0,1,2,3", 7049 "Deprecated": "1", 7050 "EventCode": "0xB7, 0xBB", 7051 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7052 "MSRIndex": "0x1a6,0x1a7", 7053 "MSRValue": "0x3F84000001", 7054 "Offcore": "1", 7055 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7056 "SampleAfterValue": "100003", 7057 "UMask": "0x1" 7058 }, 7059 { 7060 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7061 "Counter": "0,1,2,3", 7062 "CounterHTOff": "0,1,2,3", 7063 "Deprecated": "1", 7064 "EventCode": "0xB7, 0xBB", 7065 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7066 "MSRIndex": "0x1a6,0x1a7", 7067 "MSRValue": "0x1004000001", 7068 "Offcore": "1", 7069 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7070 "SampleAfterValue": "100003", 7071 "UMask": "0x1" 7072 }, 7073 { 7074 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7075 "Counter": "0,1,2,3", 7076 "CounterHTOff": "0,1,2,3", 7077 "Deprecated": "1", 7078 "EventCode": "0xB7, 0xBB", 7079 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7080 "MSRIndex": "0x1a6,0x1a7", 7081 "MSRValue": "0x0804000001", 7082 "Offcore": "1", 7083 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7084 "SampleAfterValue": "100003", 7085 "UMask": "0x1" 7086 }, 7087 { 7088 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7089 "Counter": "0,1,2,3", 7090 "CounterHTOff": "0,1,2,3", 7091 "Deprecated": "1", 7092 "EventCode": "0xB7, 0xBB", 7093 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7094 "MSRIndex": "0x1a6,0x1a7", 7095 "MSRValue": "0x0404000001", 7096 "Offcore": "1", 7097 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7098 "SampleAfterValue": "100003", 7099 "UMask": "0x1" 7100 }, 7101 { 7102 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7103 "Counter": "0,1,2,3", 7104 "CounterHTOff": "0,1,2,3", 7105 "Deprecated": "1", 7106 "EventCode": "0xB7, 0xBB", 7107 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7108 "MSRIndex": "0x1a6,0x1a7", 7109 "MSRValue": "0x0104000001", 7110 "Offcore": "1", 7111 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7112 "SampleAfterValue": "100003", 7113 "UMask": "0x1" 7114 }, 7115 { 7116 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7117 "Counter": "0,1,2,3", 7118 "CounterHTOff": "0,1,2,3", 7119 "Deprecated": "1", 7120 "EventCode": "0xB7, 0xBB", 7121 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7122 "MSRIndex": "0x1a6,0x1a7", 7123 "MSRValue": "0x0204000001", 7124 "Offcore": "1", 7125 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7126 "SampleAfterValue": "100003", 7127 "UMask": "0x1" 7128 }, 7129 { 7130 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 7131 "Counter": "0,1,2,3", 7132 "CounterHTOff": "0,1,2,3", 7133 "Deprecated": "1", 7134 "EventCode": "0xB7, 0xBB", 7135 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 7136 "MSRIndex": "0x1a6,0x1a7", 7137 "MSRValue": "0x0604000001", 7138 "Offcore": "1", 7139 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7140 "SampleAfterValue": "100003", 7141 "UMask": "0x1" 7142 }, 7143 { 7144 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7145 "Counter": "0,1,2,3", 7146 "CounterHTOff": "0,1,2,3", 7147 "Deprecated": "1", 7148 "EventCode": "0xB7, 0xBB", 7149 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7150 "MSRIndex": "0x1a6,0x1a7", 7151 "MSRValue": "0x0084000001", 7152 "Offcore": "1", 7153 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7154 "SampleAfterValue": "100003", 7155 "UMask": "0x1" 7156 }, 7157 { 7158 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 7159 "Counter": "0,1,2,3", 7160 "CounterHTOff": "0,1,2,3", 7161 "Deprecated": "1", 7162 "EventCode": "0xB7, 0xBB", 7163 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 7164 "MSRIndex": "0x1a6,0x1a7", 7165 "MSRValue": "0x063B800001", 7166 "Offcore": "1", 7167 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7168 "SampleAfterValue": "100003", 7169 "UMask": "0x1" 7170 }, 7171 { 7172 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7173 "Counter": "0,1,2,3", 7174 "CounterHTOff": "0,1,2,3", 7175 "Deprecated": "1", 7176 "EventCode": "0xB7, 0xBB", 7177 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7178 "MSRIndex": "0x1a6,0x1a7", 7179 "MSRValue": "0x3F90000001", 7180 "Offcore": "1", 7181 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7182 "SampleAfterValue": "100003", 7183 "UMask": "0x1" 7184 }, 7185 { 7186 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7187 "Counter": "0,1,2,3", 7188 "CounterHTOff": "0,1,2,3", 7189 "Deprecated": "1", 7190 "EventCode": "0xB7, 0xBB", 7191 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7192 "MSRIndex": "0x1a6,0x1a7", 7193 "MSRValue": "0x1010000001", 7194 "Offcore": "1", 7195 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7196 "SampleAfterValue": "100003", 7197 "UMask": "0x1" 7198 }, 7199 { 7200 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7201 "Counter": "0,1,2,3", 7202 "CounterHTOff": "0,1,2,3", 7203 "Deprecated": "1", 7204 "EventCode": "0xB7, 0xBB", 7205 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7206 "MSRIndex": "0x1a6,0x1a7", 7207 "MSRValue": "0x0810000001", 7208 "Offcore": "1", 7209 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7210 "SampleAfterValue": "100003", 7211 "UMask": "0x1" 7212 }, 7213 { 7214 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7215 "Counter": "0,1,2,3", 7216 "CounterHTOff": "0,1,2,3", 7217 "Deprecated": "1", 7218 "EventCode": "0xB7, 0xBB", 7219 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7220 "MSRIndex": "0x1a6,0x1a7", 7221 "MSRValue": "0x0410000001", 7222 "Offcore": "1", 7223 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7224 "SampleAfterValue": "100003", 7225 "UMask": "0x1" 7226 }, 7227 { 7228 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7229 "Counter": "0,1,2,3", 7230 "CounterHTOff": "0,1,2,3", 7231 "Deprecated": "1", 7232 "EventCode": "0xB7, 0xBB", 7233 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7234 "MSRIndex": "0x1a6,0x1a7", 7235 "MSRValue": "0x0110000001", 7236 "Offcore": "1", 7237 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7238 "SampleAfterValue": "100003", 7239 "UMask": "0x1" 7240 }, 7241 { 7242 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7243 "Counter": "0,1,2,3", 7244 "CounterHTOff": "0,1,2,3", 7245 "Deprecated": "1", 7246 "EventCode": "0xB7, 0xBB", 7247 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7248 "MSRIndex": "0x1a6,0x1a7", 7249 "MSRValue": "0x0210000001", 7250 "Offcore": "1", 7251 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7252 "SampleAfterValue": "100003", 7253 "UMask": "0x1" 7254 }, 7255 { 7256 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7257 "Counter": "0,1,2,3", 7258 "CounterHTOff": "0,1,2,3", 7259 "Deprecated": "1", 7260 "EventCode": "0xB7, 0xBB", 7261 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7262 "MSRIndex": "0x1a6,0x1a7", 7263 "MSRValue": "0x0090000001", 7264 "Offcore": "1", 7265 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7266 "SampleAfterValue": "100003", 7267 "UMask": "0x1" 7268 }, 7269 { 7270 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", 7271 "Counter": "0,1,2,3", 7272 "CounterHTOff": "0,1,2,3", 7273 "Deprecated": "1", 7274 "EventCode": "0xB7, 0xBB", 7275 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 7276 "MSRIndex": "0x1a6,0x1a7", 7277 "MSRValue": "0x3FBC000002", 7278 "Offcore": "1", 7279 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7280 "SampleAfterValue": "100003", 7281 "UMask": "0x1" 7282 }, 7283 { 7284 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", 7285 "Counter": "0,1,2,3", 7286 "CounterHTOff": "0,1,2,3", 7287 "Deprecated": "1", 7288 "EventCode": "0xB7, 0xBB", 7289 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", 7290 "MSRIndex": "0x1a6,0x1a7", 7291 "MSRValue": "0x103C000002", 7292 "Offcore": "1", 7293 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7294 "SampleAfterValue": "100003", 7295 "UMask": "0x1" 7296 }, 7297 { 7298 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 7299 "Counter": "0,1,2,3", 7300 "CounterHTOff": "0,1,2,3", 7301 "Deprecated": "1", 7302 "EventCode": "0xB7, 0xBB", 7303 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 7304 "MSRIndex": "0x1a6,0x1a7", 7305 "MSRValue": "0x083C000002", 7306 "Offcore": "1", 7307 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7308 "SampleAfterValue": "100003", 7309 "UMask": "0x1" 7310 }, 7311 { 7312 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 7313 "Counter": "0,1,2,3", 7314 "CounterHTOff": "0,1,2,3", 7315 "Deprecated": "1", 7316 "EventCode": "0xB7, 0xBB", 7317 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 7318 "MSRIndex": "0x1a6,0x1a7", 7319 "MSRValue": "0x043C000002", 7320 "Offcore": "1", 7321 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7322 "SampleAfterValue": "100003", 7323 "UMask": "0x1" 7324 }, 7325 { 7326 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", 7327 "Counter": "0,1,2,3", 7328 "CounterHTOff": "0,1,2,3", 7329 "Deprecated": "1", 7330 "EventCode": "0xB7, 0xBB", 7331 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", 7332 "MSRIndex": "0x1a6,0x1a7", 7333 "MSRValue": "0x013C000002", 7334 "Offcore": "1", 7335 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7336 "SampleAfterValue": "100003", 7337 "UMask": "0x1" 7338 }, 7339 { 7340 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", 7341 "Counter": "0,1,2,3", 7342 "CounterHTOff": "0,1,2,3", 7343 "Deprecated": "1", 7344 "EventCode": "0xB7, 0xBB", 7345 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", 7346 "MSRIndex": "0x1a6,0x1a7", 7347 "MSRValue": "0x103FC00002", 7348 "Offcore": "1", 7349 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7350 "SampleAfterValue": "100003", 7351 "UMask": "0x1" 7352 }, 7353 { 7354 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 7355 "Counter": "0,1,2,3", 7356 "CounterHTOff": "0,1,2,3", 7357 "Deprecated": "1", 7358 "EventCode": "0xB7, 0xBB", 7359 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 7360 "MSRIndex": "0x1a6,0x1a7", 7361 "MSRValue": "0x083FC00002", 7362 "Offcore": "1", 7363 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7364 "SampleAfterValue": "100003", 7365 "UMask": "0x1" 7366 }, 7367 { 7368 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", 7369 "Counter": "0,1,2,3", 7370 "CounterHTOff": "0,1,2,3", 7371 "Deprecated": "1", 7372 "EventCode": "0xB7, 0xBB", 7373 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", 7374 "MSRIndex": "0x1a6,0x1a7", 7375 "MSRValue": "0x023C000002", 7376 "Offcore": "1", 7377 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7378 "SampleAfterValue": "100003", 7379 "UMask": "0x1" 7380 }, 7381 { 7382 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", 7383 "Counter": "0,1,2,3", 7384 "CounterHTOff": "0,1,2,3", 7385 "Deprecated": "1", 7386 "EventCode": "0xB7, 0xBB", 7387 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", 7388 "MSRIndex": "0x1a6,0x1a7", 7389 "MSRValue": "0x00BC000002", 7390 "Offcore": "1", 7391 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7392 "SampleAfterValue": "100003", 7393 "UMask": "0x1" 7394 }, 7395 { 7396 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7397 "Counter": "0,1,2,3", 7398 "CounterHTOff": "0,1,2,3", 7399 "Deprecated": "1", 7400 "EventCode": "0xB7, 0xBB", 7401 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7402 "MSRIndex": "0x1a6,0x1a7", 7403 "MSRValue": "0x3F84000002", 7404 "Offcore": "1", 7405 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7406 "SampleAfterValue": "100003", 7407 "UMask": "0x1" 7408 }, 7409 { 7410 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7411 "Counter": "0,1,2,3", 7412 "CounterHTOff": "0,1,2,3", 7413 "Deprecated": "1", 7414 "EventCode": "0xB7, 0xBB", 7415 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7416 "MSRIndex": "0x1a6,0x1a7", 7417 "MSRValue": "0x1004000002", 7418 "Offcore": "1", 7419 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7420 "SampleAfterValue": "100003", 7421 "UMask": "0x1" 7422 }, 7423 { 7424 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7425 "Counter": "0,1,2,3", 7426 "CounterHTOff": "0,1,2,3", 7427 "Deprecated": "1", 7428 "EventCode": "0xB7, 0xBB", 7429 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7430 "MSRIndex": "0x1a6,0x1a7", 7431 "MSRValue": "0x0804000002", 7432 "Offcore": "1", 7433 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7434 "SampleAfterValue": "100003", 7435 "UMask": "0x1" 7436 }, 7437 { 7438 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7439 "Counter": "0,1,2,3", 7440 "CounterHTOff": "0,1,2,3", 7441 "Deprecated": "1", 7442 "EventCode": "0xB7, 0xBB", 7443 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7444 "MSRIndex": "0x1a6,0x1a7", 7445 "MSRValue": "0x0404000002", 7446 "Offcore": "1", 7447 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7448 "SampleAfterValue": "100003", 7449 "UMask": "0x1" 7450 }, 7451 { 7452 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7453 "Counter": "0,1,2,3", 7454 "CounterHTOff": "0,1,2,3", 7455 "Deprecated": "1", 7456 "EventCode": "0xB7, 0xBB", 7457 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7458 "MSRIndex": "0x1a6,0x1a7", 7459 "MSRValue": "0x0104000002", 7460 "Offcore": "1", 7461 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7462 "SampleAfterValue": "100003", 7463 "UMask": "0x1" 7464 }, 7465 { 7466 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7467 "Counter": "0,1,2,3", 7468 "CounterHTOff": "0,1,2,3", 7469 "Deprecated": "1", 7470 "EventCode": "0xB7, 0xBB", 7471 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7472 "MSRIndex": "0x1a6,0x1a7", 7473 "MSRValue": "0x0204000002", 7474 "Offcore": "1", 7475 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7476 "SampleAfterValue": "100003", 7477 "UMask": "0x1" 7478 }, 7479 { 7480 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 7481 "Counter": "0,1,2,3", 7482 "CounterHTOff": "0,1,2,3", 7483 "Deprecated": "1", 7484 "EventCode": "0xB7, 0xBB", 7485 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 7486 "MSRIndex": "0x1a6,0x1a7", 7487 "MSRValue": "0x0604000002", 7488 "Offcore": "1", 7489 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7490 "SampleAfterValue": "100003", 7491 "UMask": "0x1" 7492 }, 7493 { 7494 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7495 "Counter": "0,1,2,3", 7496 "CounterHTOff": "0,1,2,3", 7497 "Deprecated": "1", 7498 "EventCode": "0xB7, 0xBB", 7499 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7500 "MSRIndex": "0x1a6,0x1a7", 7501 "MSRValue": "0x0084000002", 7502 "Offcore": "1", 7503 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7504 "SampleAfterValue": "100003", 7505 "UMask": "0x1" 7506 }, 7507 { 7508 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 7509 "Counter": "0,1,2,3", 7510 "CounterHTOff": "0,1,2,3", 7511 "Deprecated": "1", 7512 "EventCode": "0xB7, 0xBB", 7513 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 7514 "MSRIndex": "0x1a6,0x1a7", 7515 "MSRValue": "0x063B800002", 7516 "Offcore": "1", 7517 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7518 "SampleAfterValue": "100003", 7519 "UMask": "0x1" 7520 }, 7521 { 7522 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7523 "Counter": "0,1,2,3", 7524 "CounterHTOff": "0,1,2,3", 7525 "Deprecated": "1", 7526 "EventCode": "0xB7, 0xBB", 7527 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7528 "MSRIndex": "0x1a6,0x1a7", 7529 "MSRValue": "0x3F90000002", 7530 "Offcore": "1", 7531 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7532 "SampleAfterValue": "100003", 7533 "UMask": "0x1" 7534 }, 7535 { 7536 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7537 "Counter": "0,1,2,3", 7538 "CounterHTOff": "0,1,2,3", 7539 "Deprecated": "1", 7540 "EventCode": "0xB7, 0xBB", 7541 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7542 "MSRIndex": "0x1a6,0x1a7", 7543 "MSRValue": "0x1010000002", 7544 "Offcore": "1", 7545 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7546 "SampleAfterValue": "100003", 7547 "UMask": "0x1" 7548 }, 7549 { 7550 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7551 "Counter": "0,1,2,3", 7552 "CounterHTOff": "0,1,2,3", 7553 "Deprecated": "1", 7554 "EventCode": "0xB7, 0xBB", 7555 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7556 "MSRIndex": "0x1a6,0x1a7", 7557 "MSRValue": "0x0810000002", 7558 "Offcore": "1", 7559 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7560 "SampleAfterValue": "100003", 7561 "UMask": "0x1" 7562 }, 7563 { 7564 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7565 "Counter": "0,1,2,3", 7566 "CounterHTOff": "0,1,2,3", 7567 "Deprecated": "1", 7568 "EventCode": "0xB7, 0xBB", 7569 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7570 "MSRIndex": "0x1a6,0x1a7", 7571 "MSRValue": "0x0410000002", 7572 "Offcore": "1", 7573 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7574 "SampleAfterValue": "100003", 7575 "UMask": "0x1" 7576 }, 7577 { 7578 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7579 "Counter": "0,1,2,3", 7580 "CounterHTOff": "0,1,2,3", 7581 "Deprecated": "1", 7582 "EventCode": "0xB7, 0xBB", 7583 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7584 "MSRIndex": "0x1a6,0x1a7", 7585 "MSRValue": "0x0110000002", 7586 "Offcore": "1", 7587 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7588 "SampleAfterValue": "100003", 7589 "UMask": "0x1" 7590 }, 7591 { 7592 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7593 "Counter": "0,1,2,3", 7594 "CounterHTOff": "0,1,2,3", 7595 "Deprecated": "1", 7596 "EventCode": "0xB7, 0xBB", 7597 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7598 "MSRIndex": "0x1a6,0x1a7", 7599 "MSRValue": "0x0210000002", 7600 "Offcore": "1", 7601 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7602 "SampleAfterValue": "100003", 7603 "UMask": "0x1" 7604 }, 7605 { 7606 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7607 "Counter": "0,1,2,3", 7608 "CounterHTOff": "0,1,2,3", 7609 "Deprecated": "1", 7610 "EventCode": "0xB7, 0xBB", 7611 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7612 "MSRIndex": "0x1a6,0x1a7", 7613 "MSRValue": "0x0090000002", 7614 "Offcore": "1", 7615 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7616 "SampleAfterValue": "100003", 7617 "UMask": "0x1" 7618 }, 7619 { 7620 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP", 7621 "Counter": "0,1,2,3", 7622 "CounterHTOff": "0,1,2,3", 7623 "Deprecated": "1", 7624 "EventCode": "0xB7, 0xBB", 7625 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", 7626 "MSRIndex": "0x1a6,0x1a7", 7627 "MSRValue": "0x3FBC008000", 7628 "Offcore": "1", 7629 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7630 "SampleAfterValue": "100003", 7631 "UMask": "0x1" 7632 }, 7633 { 7634 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE", 7635 "Counter": "0,1,2,3", 7636 "CounterHTOff": "0,1,2,3", 7637 "Deprecated": "1", 7638 "EventCode": "0xB7, 0xBB", 7639 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HITM_OTHER_CORE", 7640 "MSRIndex": "0x1a6,0x1a7", 7641 "MSRValue": "0x103C008000", 7642 "Offcore": "1", 7643 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7644 "SampleAfterValue": "100003", 7645 "UMask": "0x1" 7646 }, 7647 { 7648 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", 7649 "Counter": "0,1,2,3", 7650 "CounterHTOff": "0,1,2,3", 7651 "Deprecated": "1", 7652 "EventCode": "0xB7, 0xBB", 7653 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", 7654 "MSRIndex": "0x1a6,0x1a7", 7655 "MSRValue": "0x083C008000", 7656 "Offcore": "1", 7657 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7658 "SampleAfterValue": "100003", 7659 "UMask": "0x1" 7660 }, 7661 { 7662 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", 7663 "Counter": "0,1,2,3", 7664 "CounterHTOff": "0,1,2,3", 7665 "Deprecated": "1", 7666 "EventCode": "0xB7, 0xBB", 7667 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", 7668 "MSRIndex": "0x1a6,0x1a7", 7669 "MSRValue": "0x043C008000", 7670 "Offcore": "1", 7671 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7672 "SampleAfterValue": "100003", 7673 "UMask": "0x1" 7674 }, 7675 { 7676 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", 7677 "Counter": "0,1,2,3", 7678 "CounterHTOff": "0,1,2,3", 7679 "Deprecated": "1", 7680 "EventCode": "0xB7, 0xBB", 7681 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.NO_SNOOP_NEEDED", 7682 "MSRIndex": "0x1a6,0x1a7", 7683 "MSRValue": "0x013C008000", 7684 "Offcore": "1", 7685 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7686 "SampleAfterValue": "100003", 7687 "UMask": "0x1" 7688 }, 7689 { 7690 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM", 7691 "Counter": "0,1,2,3", 7692 "CounterHTOff": "0,1,2,3", 7693 "Deprecated": "1", 7694 "EventCode": "0xB7, 0xBB", 7695 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HITM", 7696 "MSRIndex": "0x1a6,0x1a7", 7697 "MSRValue": "0x103FC08000", 7698 "Offcore": "1", 7699 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7700 "SampleAfterValue": "100003", 7701 "UMask": "0x1" 7702 }, 7703 { 7704 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", 7705 "Counter": "0,1,2,3", 7706 "CounterHTOff": "0,1,2,3", 7707 "Deprecated": "1", 7708 "EventCode": "0xB7, 0xBB", 7709 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HIT_FORWARD", 7710 "MSRIndex": "0x1a6,0x1a7", 7711 "MSRValue": "0x083FC08000", 7712 "Offcore": "1", 7713 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7714 "SampleAfterValue": "100003", 7715 "UMask": "0x1" 7716 }, 7717 { 7718 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS", 7719 "Counter": "0,1,2,3", 7720 "CounterHTOff": "0,1,2,3", 7721 "Deprecated": "1", 7722 "EventCode": "0xB7, 0xBB", 7723 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", 7724 "MSRIndex": "0x1a6,0x1a7", 7725 "MSRValue": "0x023C008000", 7726 "Offcore": "1", 7727 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7728 "SampleAfterValue": "100003", 7729 "UMask": "0x1" 7730 }, 7731 { 7732 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE", 7733 "Counter": "0,1,2,3", 7734 "CounterHTOff": "0,1,2,3", 7735 "Deprecated": "1", 7736 "EventCode": "0xB7, 0xBB", 7737 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", 7738 "MSRIndex": "0x1a6,0x1a7", 7739 "MSRValue": "0x00BC008000", 7740 "Offcore": "1", 7741 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7742 "SampleAfterValue": "100003", 7743 "UMask": "0x1" 7744 }, 7745 { 7746 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7747 "Counter": "0,1,2,3", 7748 "CounterHTOff": "0,1,2,3", 7749 "Deprecated": "1", 7750 "EventCode": "0xB7, 0xBB", 7751 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 7752 "MSRIndex": "0x1a6,0x1a7", 7753 "MSRValue": "0x3F84008000", 7754 "Offcore": "1", 7755 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7756 "SampleAfterValue": "100003", 7757 "UMask": "0x1" 7758 }, 7759 { 7760 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7761 "Counter": "0,1,2,3", 7762 "CounterHTOff": "0,1,2,3", 7763 "Deprecated": "1", 7764 "EventCode": "0xB7, 0xBB", 7765 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 7766 "MSRIndex": "0x1a6,0x1a7", 7767 "MSRValue": "0x1004008000", 7768 "Offcore": "1", 7769 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7770 "SampleAfterValue": "100003", 7771 "UMask": "0x1" 7772 }, 7773 { 7774 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7775 "Counter": "0,1,2,3", 7776 "CounterHTOff": "0,1,2,3", 7777 "Deprecated": "1", 7778 "EventCode": "0xB7, 0xBB", 7779 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 7780 "MSRIndex": "0x1a6,0x1a7", 7781 "MSRValue": "0x0804008000", 7782 "Offcore": "1", 7783 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7784 "SampleAfterValue": "100003", 7785 "UMask": "0x1" 7786 }, 7787 { 7788 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7789 "Counter": "0,1,2,3", 7790 "CounterHTOff": "0,1,2,3", 7791 "Deprecated": "1", 7792 "EventCode": "0xB7, 0xBB", 7793 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 7794 "MSRIndex": "0x1a6,0x1a7", 7795 "MSRValue": "0x0404008000", 7796 "Offcore": "1", 7797 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7798 "SampleAfterValue": "100003", 7799 "UMask": "0x1" 7800 }, 7801 { 7802 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7803 "Counter": "0,1,2,3", 7804 "CounterHTOff": "0,1,2,3", 7805 "Deprecated": "1", 7806 "EventCode": "0xB7, 0xBB", 7807 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 7808 "MSRIndex": "0x1a6,0x1a7", 7809 "MSRValue": "0x0104008000", 7810 "Offcore": "1", 7811 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7812 "SampleAfterValue": "100003", 7813 "UMask": "0x1" 7814 }, 7815 { 7816 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7817 "Counter": "0,1,2,3", 7818 "CounterHTOff": "0,1,2,3", 7819 "Deprecated": "1", 7820 "EventCode": "0xB7, 0xBB", 7821 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 7822 "MSRIndex": "0x1a6,0x1a7", 7823 "MSRValue": "0x0204008000", 7824 "Offcore": "1", 7825 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7826 "SampleAfterValue": "100003", 7827 "UMask": "0x1" 7828 }, 7829 { 7830 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 7831 "Counter": "0,1,2,3", 7832 "CounterHTOff": "0,1,2,3", 7833 "Deprecated": "1", 7834 "EventCode": "0xB7, 0xBB", 7835 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 7836 "MSRIndex": "0x1a6,0x1a7", 7837 "MSRValue": "0x0604008000", 7838 "Offcore": "1", 7839 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7840 "SampleAfterValue": "100003", 7841 "UMask": "0x1" 7842 }, 7843 { 7844 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7845 "Counter": "0,1,2,3", 7846 "CounterHTOff": "0,1,2,3", 7847 "Deprecated": "1", 7848 "EventCode": "0xB7, 0xBB", 7849 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 7850 "MSRIndex": "0x1a6,0x1a7", 7851 "MSRValue": "0x0084008000", 7852 "Offcore": "1", 7853 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7854 "SampleAfterValue": "100003", 7855 "UMask": "0x1" 7856 }, 7857 { 7858 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 7859 "Counter": "0,1,2,3", 7860 "CounterHTOff": "0,1,2,3", 7861 "Deprecated": "1", 7862 "EventCode": "0xB7, 0xBB", 7863 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 7864 "MSRIndex": "0x1a6,0x1a7", 7865 "MSRValue": "0x063B808000", 7866 "Offcore": "1", 7867 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7868 "SampleAfterValue": "100003", 7869 "UMask": "0x1" 7870 }, 7871 { 7872 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7873 "Counter": "0,1,2,3", 7874 "CounterHTOff": "0,1,2,3", 7875 "Deprecated": "1", 7876 "EventCode": "0xB7, 0xBB", 7877 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 7878 "MSRIndex": "0x1a6,0x1a7", 7879 "MSRValue": "0x3F90008000", 7880 "Offcore": "1", 7881 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7882 "SampleAfterValue": "100003", 7883 "UMask": "0x1" 7884 }, 7885 { 7886 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7887 "Counter": "0,1,2,3", 7888 "CounterHTOff": "0,1,2,3", 7889 "Deprecated": "1", 7890 "EventCode": "0xB7, 0xBB", 7891 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 7892 "MSRIndex": "0x1a6,0x1a7", 7893 "MSRValue": "0x1010008000", 7894 "Offcore": "1", 7895 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7896 "SampleAfterValue": "100003", 7897 "UMask": "0x1" 7898 }, 7899 { 7900 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7901 "Counter": "0,1,2,3", 7902 "CounterHTOff": "0,1,2,3", 7903 "Deprecated": "1", 7904 "EventCode": "0xB7, 0xBB", 7905 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 7906 "MSRIndex": "0x1a6,0x1a7", 7907 "MSRValue": "0x0810008000", 7908 "Offcore": "1", 7909 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7910 "SampleAfterValue": "100003", 7911 "UMask": "0x1" 7912 }, 7913 { 7914 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7915 "Counter": "0,1,2,3", 7916 "CounterHTOff": "0,1,2,3", 7917 "Deprecated": "1", 7918 "EventCode": "0xB7, 0xBB", 7919 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 7920 "MSRIndex": "0x1a6,0x1a7", 7921 "MSRValue": "0x0410008000", 7922 "Offcore": "1", 7923 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7924 "SampleAfterValue": "100003", 7925 "UMask": "0x1" 7926 }, 7927 { 7928 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7929 "Counter": "0,1,2,3", 7930 "CounterHTOff": "0,1,2,3", 7931 "Deprecated": "1", 7932 "EventCode": "0xB7, 0xBB", 7933 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 7934 "MSRIndex": "0x1a6,0x1a7", 7935 "MSRValue": "0x0110008000", 7936 "Offcore": "1", 7937 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7938 "SampleAfterValue": "100003", 7939 "UMask": "0x1" 7940 }, 7941 { 7942 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7943 "Counter": "0,1,2,3", 7944 "CounterHTOff": "0,1,2,3", 7945 "Deprecated": "1", 7946 "EventCode": "0xB7, 0xBB", 7947 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 7948 "MSRIndex": "0x1a6,0x1a7", 7949 "MSRValue": "0x0210008000", 7950 "Offcore": "1", 7951 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7952 "SampleAfterValue": "100003", 7953 "UMask": "0x1" 7954 }, 7955 { 7956 "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7957 "Counter": "0,1,2,3", 7958 "CounterHTOff": "0,1,2,3", 7959 "Deprecated": "1", 7960 "EventCode": "0xB7, 0xBB", 7961 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 7962 "MSRIndex": "0x1a6,0x1a7", 7963 "MSRValue": "0x0090008000", 7964 "Offcore": "1", 7965 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7966 "SampleAfterValue": "100003", 7967 "UMask": "0x1" 7968 }, 7969 { 7970 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 7971 "Counter": "0,1,2,3", 7972 "CounterHTOff": "0,1,2,3", 7973 "Deprecated": "1", 7974 "EventCode": "0xB7, 0xBB", 7975 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 7976 "MSRIndex": "0x1a6,0x1a7", 7977 "MSRValue": "0x3FBC000400", 7978 "Offcore": "1", 7979 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7980 "SampleAfterValue": "100003", 7981 "UMask": "0x1" 7982 }, 7983 { 7984 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", 7985 "Counter": "0,1,2,3", 7986 "CounterHTOff": "0,1,2,3", 7987 "Deprecated": "1", 7988 "EventCode": "0xB7, 0xBB", 7989 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", 7990 "MSRIndex": "0x1a6,0x1a7", 7991 "MSRValue": "0x103C000400", 7992 "Offcore": "1", 7993 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7994 "SampleAfterValue": "100003", 7995 "UMask": "0x1" 7996 }, 7997 { 7998 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", 7999 "Counter": "0,1,2,3", 8000 "CounterHTOff": "0,1,2,3", 8001 "Deprecated": "1", 8002 "EventCode": "0xB7, 0xBB", 8003 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", 8004 "MSRIndex": "0x1a6,0x1a7", 8005 "MSRValue": "0x083C000400", 8006 "Offcore": "1", 8007 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8008 "SampleAfterValue": "100003", 8009 "UMask": "0x1" 8010 }, 8011 { 8012 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8013 "Counter": "0,1,2,3", 8014 "CounterHTOff": "0,1,2,3", 8015 "Deprecated": "1", 8016 "EventCode": "0xB7, 0xBB", 8017 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8018 "MSRIndex": "0x1a6,0x1a7", 8019 "MSRValue": "0x043C000400", 8020 "Offcore": "1", 8021 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8022 "SampleAfterValue": "100003", 8023 "UMask": "0x1" 8024 }, 8025 { 8026 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", 8027 "Counter": "0,1,2,3", 8028 "CounterHTOff": "0,1,2,3", 8029 "Deprecated": "1", 8030 "EventCode": "0xB7, 0xBB", 8031 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", 8032 "MSRIndex": "0x1a6,0x1a7", 8033 "MSRValue": "0x013C000400", 8034 "Offcore": "1", 8035 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8036 "SampleAfterValue": "100003", 8037 "UMask": "0x1" 8038 }, 8039 { 8040 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 8041 "Counter": "0,1,2,3", 8042 "CounterHTOff": "0,1,2,3", 8043 "Deprecated": "1", 8044 "EventCode": "0xB7, 0xBB", 8045 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 8046 "MSRIndex": "0x1a6,0x1a7", 8047 "MSRValue": "0x103FC00400", 8048 "Offcore": "1", 8049 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8050 "SampleAfterValue": "100003", 8051 "UMask": "0x1" 8052 }, 8053 { 8054 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 8055 "Counter": "0,1,2,3", 8056 "CounterHTOff": "0,1,2,3", 8057 "Deprecated": "1", 8058 "EventCode": "0xB7, 0xBB", 8059 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 8060 "MSRIndex": "0x1a6,0x1a7", 8061 "MSRValue": "0x083FC00400", 8062 "Offcore": "1", 8063 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8064 "SampleAfterValue": "100003", 8065 "UMask": "0x1" 8066 }, 8067 { 8068 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", 8069 "Counter": "0,1,2,3", 8070 "CounterHTOff": "0,1,2,3", 8071 "Deprecated": "1", 8072 "EventCode": "0xB7, 0xBB", 8073 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", 8074 "MSRIndex": "0x1a6,0x1a7", 8075 "MSRValue": "0x023C000400", 8076 "Offcore": "1", 8077 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8078 "SampleAfterValue": "100003", 8079 "UMask": "0x1" 8080 }, 8081 { 8082 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", 8083 "Counter": "0,1,2,3", 8084 "CounterHTOff": "0,1,2,3", 8085 "Deprecated": "1", 8086 "EventCode": "0xB7, 0xBB", 8087 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", 8088 "MSRIndex": "0x1a6,0x1a7", 8089 "MSRValue": "0x00BC000400", 8090 "Offcore": "1", 8091 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8092 "SampleAfterValue": "100003", 8093 "UMask": "0x1" 8094 }, 8095 { 8096 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8097 "Counter": "0,1,2,3", 8098 "CounterHTOff": "0,1,2,3", 8099 "Deprecated": "1", 8100 "EventCode": "0xB7, 0xBB", 8101 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8102 "MSRIndex": "0x1a6,0x1a7", 8103 "MSRValue": "0x3F84000400", 8104 "Offcore": "1", 8105 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8106 "SampleAfterValue": "100003", 8107 "UMask": "0x1" 8108 }, 8109 { 8110 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8111 "Counter": "0,1,2,3", 8112 "CounterHTOff": "0,1,2,3", 8113 "Deprecated": "1", 8114 "EventCode": "0xB7, 0xBB", 8115 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8116 "MSRIndex": "0x1a6,0x1a7", 8117 "MSRValue": "0x1004000400", 8118 "Offcore": "1", 8119 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8120 "SampleAfterValue": "100003", 8121 "UMask": "0x1" 8122 }, 8123 { 8124 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8125 "Counter": "0,1,2,3", 8126 "CounterHTOff": "0,1,2,3", 8127 "Deprecated": "1", 8128 "EventCode": "0xB7, 0xBB", 8129 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8130 "MSRIndex": "0x1a6,0x1a7", 8131 "MSRValue": "0x0804000400", 8132 "Offcore": "1", 8133 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8134 "SampleAfterValue": "100003", 8135 "UMask": "0x1" 8136 }, 8137 { 8138 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8139 "Counter": "0,1,2,3", 8140 "CounterHTOff": "0,1,2,3", 8141 "Deprecated": "1", 8142 "EventCode": "0xB7, 0xBB", 8143 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8144 "MSRIndex": "0x1a6,0x1a7", 8145 "MSRValue": "0x0404000400", 8146 "Offcore": "1", 8147 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8148 "SampleAfterValue": "100003", 8149 "UMask": "0x1" 8150 }, 8151 { 8152 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8153 "Counter": "0,1,2,3", 8154 "CounterHTOff": "0,1,2,3", 8155 "Deprecated": "1", 8156 "EventCode": "0xB7, 0xBB", 8157 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8158 "MSRIndex": "0x1a6,0x1a7", 8159 "MSRValue": "0x0104000400", 8160 "Offcore": "1", 8161 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8162 "SampleAfterValue": "100003", 8163 "UMask": "0x1" 8164 }, 8165 { 8166 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8167 "Counter": "0,1,2,3", 8168 "CounterHTOff": "0,1,2,3", 8169 "Deprecated": "1", 8170 "EventCode": "0xB7, 0xBB", 8171 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8172 "MSRIndex": "0x1a6,0x1a7", 8173 "MSRValue": "0x0204000400", 8174 "Offcore": "1", 8175 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8176 "SampleAfterValue": "100003", 8177 "UMask": "0x1" 8178 }, 8179 { 8180 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 8181 "Counter": "0,1,2,3", 8182 "CounterHTOff": "0,1,2,3", 8183 "Deprecated": "1", 8184 "EventCode": "0xB7, 0xBB", 8185 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 8186 "MSRIndex": "0x1a6,0x1a7", 8187 "MSRValue": "0x0604000400", 8188 "Offcore": "1", 8189 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8190 "SampleAfterValue": "100003", 8191 "UMask": "0x1" 8192 }, 8193 { 8194 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8195 "Counter": "0,1,2,3", 8196 "CounterHTOff": "0,1,2,3", 8197 "Deprecated": "1", 8198 "EventCode": "0xB7, 0xBB", 8199 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8200 "MSRIndex": "0x1a6,0x1a7", 8201 "MSRValue": "0x0084000400", 8202 "Offcore": "1", 8203 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8204 "SampleAfterValue": "100003", 8205 "UMask": "0x1" 8206 }, 8207 { 8208 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 8209 "Counter": "0,1,2,3", 8210 "CounterHTOff": "0,1,2,3", 8211 "Deprecated": "1", 8212 "EventCode": "0xB7, 0xBB", 8213 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 8214 "MSRIndex": "0x1a6,0x1a7", 8215 "MSRValue": "0x063B800400", 8216 "Offcore": "1", 8217 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8218 "SampleAfterValue": "100003", 8219 "UMask": "0x1" 8220 }, 8221 { 8222 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8223 "Counter": "0,1,2,3", 8224 "CounterHTOff": "0,1,2,3", 8225 "Deprecated": "1", 8226 "EventCode": "0xB7, 0xBB", 8227 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8228 "MSRIndex": "0x1a6,0x1a7", 8229 "MSRValue": "0x3F90000400", 8230 "Offcore": "1", 8231 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8232 "SampleAfterValue": "100003", 8233 "UMask": "0x1" 8234 }, 8235 { 8236 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8237 "Counter": "0,1,2,3", 8238 "CounterHTOff": "0,1,2,3", 8239 "Deprecated": "1", 8240 "EventCode": "0xB7, 0xBB", 8241 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8242 "MSRIndex": "0x1a6,0x1a7", 8243 "MSRValue": "0x1010000400", 8244 "Offcore": "1", 8245 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8246 "SampleAfterValue": "100003", 8247 "UMask": "0x1" 8248 }, 8249 { 8250 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8251 "Counter": "0,1,2,3", 8252 "CounterHTOff": "0,1,2,3", 8253 "Deprecated": "1", 8254 "EventCode": "0xB7, 0xBB", 8255 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8256 "MSRIndex": "0x1a6,0x1a7", 8257 "MSRValue": "0x0810000400", 8258 "Offcore": "1", 8259 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8260 "SampleAfterValue": "100003", 8261 "UMask": "0x1" 8262 }, 8263 { 8264 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8265 "Counter": "0,1,2,3", 8266 "CounterHTOff": "0,1,2,3", 8267 "Deprecated": "1", 8268 "EventCode": "0xB7, 0xBB", 8269 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8270 "MSRIndex": "0x1a6,0x1a7", 8271 "MSRValue": "0x0410000400", 8272 "Offcore": "1", 8273 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8274 "SampleAfterValue": "100003", 8275 "UMask": "0x1" 8276 }, 8277 { 8278 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8279 "Counter": "0,1,2,3", 8280 "CounterHTOff": "0,1,2,3", 8281 "Deprecated": "1", 8282 "EventCode": "0xB7, 0xBB", 8283 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8284 "MSRIndex": "0x1a6,0x1a7", 8285 "MSRValue": "0x0110000400", 8286 "Offcore": "1", 8287 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8288 "SampleAfterValue": "100003", 8289 "UMask": "0x1" 8290 }, 8291 { 8292 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8293 "Counter": "0,1,2,3", 8294 "CounterHTOff": "0,1,2,3", 8295 "Deprecated": "1", 8296 "EventCode": "0xB7, 0xBB", 8297 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8298 "MSRIndex": "0x1a6,0x1a7", 8299 "MSRValue": "0x0210000400", 8300 "Offcore": "1", 8301 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8302 "SampleAfterValue": "100003", 8303 "UMask": "0x1" 8304 }, 8305 { 8306 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 8307 "Counter": "0,1,2,3", 8308 "CounterHTOff": "0,1,2,3", 8309 "Deprecated": "1", 8310 "EventCode": "0xB7, 0xBB", 8311 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 8312 "MSRIndex": "0x1a6,0x1a7", 8313 "MSRValue": "0x0090000400", 8314 "Offcore": "1", 8315 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8316 "SampleAfterValue": "100003", 8317 "UMask": "0x1" 8318 }, 8319 { 8320 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 8321 "Counter": "0,1,2,3", 8322 "CounterHTOff": "0,1,2,3", 8323 "Deprecated": "1", 8324 "EventCode": "0xB7, 0xBB", 8325 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 8326 "MSRIndex": "0x1a6,0x1a7", 8327 "MSRValue": "0x3FBC000010", 8328 "Offcore": "1", 8329 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8330 "SampleAfterValue": "100003", 8331 "UMask": "0x1" 8332 }, 8333 { 8334 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", 8335 "Counter": "0,1,2,3", 8336 "CounterHTOff": "0,1,2,3", 8337 "Deprecated": "1", 8338 "EventCode": "0xB7, 0xBB", 8339 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", 8340 "MSRIndex": "0x1a6,0x1a7", 8341 "MSRValue": "0x103C000010", 8342 "Offcore": "1", 8343 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8344 "SampleAfterValue": "100003", 8345 "UMask": "0x1" 8346 }, 8347 { 8348 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 8349 "Counter": "0,1,2,3", 8350 "CounterHTOff": "0,1,2,3", 8351 "Deprecated": "1", 8352 "EventCode": "0xB7, 0xBB", 8353 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 8354 "MSRIndex": "0x1a6,0x1a7", 8355 "MSRValue": "0x083C000010", 8356 "Offcore": "1", 8357 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8358 "SampleAfterValue": "100003", 8359 "UMask": "0x1" 8360 }, 8361 { 8362 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8363 "Counter": "0,1,2,3", 8364 "CounterHTOff": "0,1,2,3", 8365 "Deprecated": "1", 8366 "EventCode": "0xB7, 0xBB", 8367 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8368 "MSRIndex": "0x1a6,0x1a7", 8369 "MSRValue": "0x043C000010", 8370 "Offcore": "1", 8371 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8372 "SampleAfterValue": "100003", 8373 "UMask": "0x1" 8374 }, 8375 { 8376 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 8377 "Counter": "0,1,2,3", 8378 "CounterHTOff": "0,1,2,3", 8379 "Deprecated": "1", 8380 "EventCode": "0xB7, 0xBB", 8381 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 8382 "MSRIndex": "0x1a6,0x1a7", 8383 "MSRValue": "0x013C000010", 8384 "Offcore": "1", 8385 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8386 "SampleAfterValue": "100003", 8387 "UMask": "0x1" 8388 }, 8389 { 8390 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 8391 "Counter": "0,1,2,3", 8392 "CounterHTOff": "0,1,2,3", 8393 "Deprecated": "1", 8394 "EventCode": "0xB7, 0xBB", 8395 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 8396 "MSRIndex": "0x1a6,0x1a7", 8397 "MSRValue": "0x103FC00010", 8398 "Offcore": "1", 8399 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8400 "SampleAfterValue": "100003", 8401 "UMask": "0x1" 8402 }, 8403 { 8404 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 8405 "Counter": "0,1,2,3", 8406 "CounterHTOff": "0,1,2,3", 8407 "Deprecated": "1", 8408 "EventCode": "0xB7, 0xBB", 8409 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 8410 "MSRIndex": "0x1a6,0x1a7", 8411 "MSRValue": "0x083FC00010", 8412 "Offcore": "1", 8413 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8414 "SampleAfterValue": "100003", 8415 "UMask": "0x1" 8416 }, 8417 { 8418 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", 8419 "Counter": "0,1,2,3", 8420 "CounterHTOff": "0,1,2,3", 8421 "Deprecated": "1", 8422 "EventCode": "0xB7, 0xBB", 8423 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", 8424 "MSRIndex": "0x1a6,0x1a7", 8425 "MSRValue": "0x023C000010", 8426 "Offcore": "1", 8427 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8428 "SampleAfterValue": "100003", 8429 "UMask": "0x1" 8430 }, 8431 { 8432 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", 8433 "Counter": "0,1,2,3", 8434 "CounterHTOff": "0,1,2,3", 8435 "Deprecated": "1", 8436 "EventCode": "0xB7, 0xBB", 8437 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", 8438 "MSRIndex": "0x1a6,0x1a7", 8439 "MSRValue": "0x00BC000010", 8440 "Offcore": "1", 8441 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8442 "SampleAfterValue": "100003", 8443 "UMask": "0x1" 8444 }, 8445 { 8446 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8447 "Counter": "0,1,2,3", 8448 "CounterHTOff": "0,1,2,3", 8449 "Deprecated": "1", 8450 "EventCode": "0xB7, 0xBB", 8451 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8452 "MSRIndex": "0x1a6,0x1a7", 8453 "MSRValue": "0x3F84000010", 8454 "Offcore": "1", 8455 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8456 "SampleAfterValue": "100003", 8457 "UMask": "0x1" 8458 }, 8459 { 8460 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8461 "Counter": "0,1,2,3", 8462 "CounterHTOff": "0,1,2,3", 8463 "Deprecated": "1", 8464 "EventCode": "0xB7, 0xBB", 8465 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8466 "MSRIndex": "0x1a6,0x1a7", 8467 "MSRValue": "0x1004000010", 8468 "Offcore": "1", 8469 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8470 "SampleAfterValue": "100003", 8471 "UMask": "0x1" 8472 }, 8473 { 8474 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8475 "Counter": "0,1,2,3", 8476 "CounterHTOff": "0,1,2,3", 8477 "Deprecated": "1", 8478 "EventCode": "0xB7, 0xBB", 8479 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8480 "MSRIndex": "0x1a6,0x1a7", 8481 "MSRValue": "0x0804000010", 8482 "Offcore": "1", 8483 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8484 "SampleAfterValue": "100003", 8485 "UMask": "0x1" 8486 }, 8487 { 8488 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8489 "Counter": "0,1,2,3", 8490 "CounterHTOff": "0,1,2,3", 8491 "Deprecated": "1", 8492 "EventCode": "0xB7, 0xBB", 8493 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8494 "MSRIndex": "0x1a6,0x1a7", 8495 "MSRValue": "0x0404000010", 8496 "Offcore": "1", 8497 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8498 "SampleAfterValue": "100003", 8499 "UMask": "0x1" 8500 }, 8501 { 8502 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8503 "Counter": "0,1,2,3", 8504 "CounterHTOff": "0,1,2,3", 8505 "Deprecated": "1", 8506 "EventCode": "0xB7, 0xBB", 8507 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8508 "MSRIndex": "0x1a6,0x1a7", 8509 "MSRValue": "0x0104000010", 8510 "Offcore": "1", 8511 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8512 "SampleAfterValue": "100003", 8513 "UMask": "0x1" 8514 }, 8515 { 8516 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8517 "Counter": "0,1,2,3", 8518 "CounterHTOff": "0,1,2,3", 8519 "Deprecated": "1", 8520 "EventCode": "0xB7, 0xBB", 8521 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8522 "MSRIndex": "0x1a6,0x1a7", 8523 "MSRValue": "0x0204000010", 8524 "Offcore": "1", 8525 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8526 "SampleAfterValue": "100003", 8527 "UMask": "0x1" 8528 }, 8529 { 8530 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 8531 "Counter": "0,1,2,3", 8532 "CounterHTOff": "0,1,2,3", 8533 "Deprecated": "1", 8534 "EventCode": "0xB7, 0xBB", 8535 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 8536 "MSRIndex": "0x1a6,0x1a7", 8537 "MSRValue": "0x0604000010", 8538 "Offcore": "1", 8539 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8540 "SampleAfterValue": "100003", 8541 "UMask": "0x1" 8542 }, 8543 { 8544 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8545 "Counter": "0,1,2,3", 8546 "CounterHTOff": "0,1,2,3", 8547 "Deprecated": "1", 8548 "EventCode": "0xB7, 0xBB", 8549 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8550 "MSRIndex": "0x1a6,0x1a7", 8551 "MSRValue": "0x0084000010", 8552 "Offcore": "1", 8553 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8554 "SampleAfterValue": "100003", 8555 "UMask": "0x1" 8556 }, 8557 { 8558 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 8559 "Counter": "0,1,2,3", 8560 "CounterHTOff": "0,1,2,3", 8561 "Deprecated": "1", 8562 "EventCode": "0xB7, 0xBB", 8563 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 8564 "MSRIndex": "0x1a6,0x1a7", 8565 "MSRValue": "0x063B800010", 8566 "Offcore": "1", 8567 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8568 "SampleAfterValue": "100003", 8569 "UMask": "0x1" 8570 }, 8571 { 8572 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8573 "Counter": "0,1,2,3", 8574 "CounterHTOff": "0,1,2,3", 8575 "Deprecated": "1", 8576 "EventCode": "0xB7, 0xBB", 8577 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8578 "MSRIndex": "0x1a6,0x1a7", 8579 "MSRValue": "0x3F90000010", 8580 "Offcore": "1", 8581 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8582 "SampleAfterValue": "100003", 8583 "UMask": "0x1" 8584 }, 8585 { 8586 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8587 "Counter": "0,1,2,3", 8588 "CounterHTOff": "0,1,2,3", 8589 "Deprecated": "1", 8590 "EventCode": "0xB7, 0xBB", 8591 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8592 "MSRIndex": "0x1a6,0x1a7", 8593 "MSRValue": "0x1010000010", 8594 "Offcore": "1", 8595 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8596 "SampleAfterValue": "100003", 8597 "UMask": "0x1" 8598 }, 8599 { 8600 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8601 "Counter": "0,1,2,3", 8602 "CounterHTOff": "0,1,2,3", 8603 "Deprecated": "1", 8604 "EventCode": "0xB7, 0xBB", 8605 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8606 "MSRIndex": "0x1a6,0x1a7", 8607 "MSRValue": "0x0810000010", 8608 "Offcore": "1", 8609 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8610 "SampleAfterValue": "100003", 8611 "UMask": "0x1" 8612 }, 8613 { 8614 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8615 "Counter": "0,1,2,3", 8616 "CounterHTOff": "0,1,2,3", 8617 "Deprecated": "1", 8618 "EventCode": "0xB7, 0xBB", 8619 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8620 "MSRIndex": "0x1a6,0x1a7", 8621 "MSRValue": "0x0410000010", 8622 "Offcore": "1", 8623 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8624 "SampleAfterValue": "100003", 8625 "UMask": "0x1" 8626 }, 8627 { 8628 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8629 "Counter": "0,1,2,3", 8630 "CounterHTOff": "0,1,2,3", 8631 "Deprecated": "1", 8632 "EventCode": "0xB7, 0xBB", 8633 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8634 "MSRIndex": "0x1a6,0x1a7", 8635 "MSRValue": "0x0110000010", 8636 "Offcore": "1", 8637 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8638 "SampleAfterValue": "100003", 8639 "UMask": "0x1" 8640 }, 8641 { 8642 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8643 "Counter": "0,1,2,3", 8644 "CounterHTOff": "0,1,2,3", 8645 "Deprecated": "1", 8646 "EventCode": "0xB7, 0xBB", 8647 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8648 "MSRIndex": "0x1a6,0x1a7", 8649 "MSRValue": "0x0210000010", 8650 "Offcore": "1", 8651 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8652 "SampleAfterValue": "100003", 8653 "UMask": "0x1" 8654 }, 8655 { 8656 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 8657 "Counter": "0,1,2,3", 8658 "CounterHTOff": "0,1,2,3", 8659 "Deprecated": "1", 8660 "EventCode": "0xB7, 0xBB", 8661 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 8662 "MSRIndex": "0x1a6,0x1a7", 8663 "MSRValue": "0x0090000010", 8664 "Offcore": "1", 8665 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8666 "SampleAfterValue": "100003", 8667 "UMask": "0x1" 8668 }, 8669 { 8670 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", 8671 "Counter": "0,1,2,3", 8672 "CounterHTOff": "0,1,2,3", 8673 "Deprecated": "1", 8674 "EventCode": "0xB7, 0xBB", 8675 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", 8676 "MSRIndex": "0x1a6,0x1a7", 8677 "MSRValue": "0x3FBC000020", 8678 "Offcore": "1", 8679 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8680 "SampleAfterValue": "100003", 8681 "UMask": "0x1" 8682 }, 8683 { 8684 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", 8685 "Counter": "0,1,2,3", 8686 "CounterHTOff": "0,1,2,3", 8687 "Deprecated": "1", 8688 "EventCode": "0xB7, 0xBB", 8689 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", 8690 "MSRIndex": "0x1a6,0x1a7", 8691 "MSRValue": "0x103C000020", 8692 "Offcore": "1", 8693 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8694 "SampleAfterValue": "100003", 8695 "UMask": "0x1" 8696 }, 8697 { 8698 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 8699 "Counter": "0,1,2,3", 8700 "CounterHTOff": "0,1,2,3", 8701 "Deprecated": "1", 8702 "EventCode": "0xB7, 0xBB", 8703 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 8704 "MSRIndex": "0x1a6,0x1a7", 8705 "MSRValue": "0x083C000020", 8706 "Offcore": "1", 8707 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8708 "SampleAfterValue": "100003", 8709 "UMask": "0x1" 8710 }, 8711 { 8712 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8713 "Counter": "0,1,2,3", 8714 "CounterHTOff": "0,1,2,3", 8715 "Deprecated": "1", 8716 "EventCode": "0xB7, 0xBB", 8717 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 8718 "MSRIndex": "0x1a6,0x1a7", 8719 "MSRValue": "0x043C000020", 8720 "Offcore": "1", 8721 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8722 "SampleAfterValue": "100003", 8723 "UMask": "0x1" 8724 }, 8725 { 8726 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", 8727 "Counter": "0,1,2,3", 8728 "CounterHTOff": "0,1,2,3", 8729 "Deprecated": "1", 8730 "EventCode": "0xB7, 0xBB", 8731 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", 8732 "MSRIndex": "0x1a6,0x1a7", 8733 "MSRValue": "0x013C000020", 8734 "Offcore": "1", 8735 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8736 "SampleAfterValue": "100003", 8737 "UMask": "0x1" 8738 }, 8739 { 8740 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", 8741 "Counter": "0,1,2,3", 8742 "CounterHTOff": "0,1,2,3", 8743 "Deprecated": "1", 8744 "EventCode": "0xB7, 0xBB", 8745 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", 8746 "MSRIndex": "0x1a6,0x1a7", 8747 "MSRValue": "0x103FC00020", 8748 "Offcore": "1", 8749 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8750 "SampleAfterValue": "100003", 8751 "UMask": "0x1" 8752 }, 8753 { 8754 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 8755 "Counter": "0,1,2,3", 8756 "CounterHTOff": "0,1,2,3", 8757 "Deprecated": "1", 8758 "EventCode": "0xB7, 0xBB", 8759 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 8760 "MSRIndex": "0x1a6,0x1a7", 8761 "MSRValue": "0x083FC00020", 8762 "Offcore": "1", 8763 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8764 "SampleAfterValue": "100003", 8765 "UMask": "0x1" 8766 }, 8767 { 8768 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", 8769 "Counter": "0,1,2,3", 8770 "CounterHTOff": "0,1,2,3", 8771 "Deprecated": "1", 8772 "EventCode": "0xB7, 0xBB", 8773 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS", 8774 "MSRIndex": "0x1a6,0x1a7", 8775 "MSRValue": "0x023C000020", 8776 "Offcore": "1", 8777 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8778 "SampleAfterValue": "100003", 8779 "UMask": "0x1" 8780 }, 8781 { 8782 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", 8783 "Counter": "0,1,2,3", 8784 "CounterHTOff": "0,1,2,3", 8785 "Deprecated": "1", 8786 "EventCode": "0xB7, 0xBB", 8787 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE", 8788 "MSRIndex": "0x1a6,0x1a7", 8789 "MSRValue": "0x00BC000020", 8790 "Offcore": "1", 8791 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8792 "SampleAfterValue": "100003", 8793 "UMask": "0x1" 8794 }, 8795 { 8796 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8797 "Counter": "0,1,2,3", 8798 "CounterHTOff": "0,1,2,3", 8799 "Deprecated": "1", 8800 "EventCode": "0xB7, 0xBB", 8801 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 8802 "MSRIndex": "0x1a6,0x1a7", 8803 "MSRValue": "0x3F84000020", 8804 "Offcore": "1", 8805 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8806 "SampleAfterValue": "100003", 8807 "UMask": "0x1" 8808 }, 8809 { 8810 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8811 "Counter": "0,1,2,3", 8812 "CounterHTOff": "0,1,2,3", 8813 "Deprecated": "1", 8814 "EventCode": "0xB7, 0xBB", 8815 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 8816 "MSRIndex": "0x1a6,0x1a7", 8817 "MSRValue": "0x1004000020", 8818 "Offcore": "1", 8819 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8820 "SampleAfterValue": "100003", 8821 "UMask": "0x1" 8822 }, 8823 { 8824 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8825 "Counter": "0,1,2,3", 8826 "CounterHTOff": "0,1,2,3", 8827 "Deprecated": "1", 8828 "EventCode": "0xB7, 0xBB", 8829 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 8830 "MSRIndex": "0x1a6,0x1a7", 8831 "MSRValue": "0x0804000020", 8832 "Offcore": "1", 8833 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8834 "SampleAfterValue": "100003", 8835 "UMask": "0x1" 8836 }, 8837 { 8838 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8839 "Counter": "0,1,2,3", 8840 "CounterHTOff": "0,1,2,3", 8841 "Deprecated": "1", 8842 "EventCode": "0xB7, 0xBB", 8843 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 8844 "MSRIndex": "0x1a6,0x1a7", 8845 "MSRValue": "0x0404000020", 8846 "Offcore": "1", 8847 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8848 "SampleAfterValue": "100003", 8849 "UMask": "0x1" 8850 }, 8851 { 8852 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8853 "Counter": "0,1,2,3", 8854 "CounterHTOff": "0,1,2,3", 8855 "Deprecated": "1", 8856 "EventCode": "0xB7, 0xBB", 8857 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 8858 "MSRIndex": "0x1a6,0x1a7", 8859 "MSRValue": "0x0104000020", 8860 "Offcore": "1", 8861 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8862 "SampleAfterValue": "100003", 8863 "UMask": "0x1" 8864 }, 8865 { 8866 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8867 "Counter": "0,1,2,3", 8868 "CounterHTOff": "0,1,2,3", 8869 "Deprecated": "1", 8870 "EventCode": "0xB7, 0xBB", 8871 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 8872 "MSRIndex": "0x1a6,0x1a7", 8873 "MSRValue": "0x0204000020", 8874 "Offcore": "1", 8875 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8876 "SampleAfterValue": "100003", 8877 "UMask": "0x1" 8878 }, 8879 { 8880 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 8881 "Counter": "0,1,2,3", 8882 "CounterHTOff": "0,1,2,3", 8883 "Deprecated": "1", 8884 "EventCode": "0xB7, 0xBB", 8885 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 8886 "MSRIndex": "0x1a6,0x1a7", 8887 "MSRValue": "0x0604000020", 8888 "Offcore": "1", 8889 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8890 "SampleAfterValue": "100003", 8891 "UMask": "0x1" 8892 }, 8893 { 8894 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8895 "Counter": "0,1,2,3", 8896 "CounterHTOff": "0,1,2,3", 8897 "Deprecated": "1", 8898 "EventCode": "0xB7, 0xBB", 8899 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 8900 "MSRIndex": "0x1a6,0x1a7", 8901 "MSRValue": "0x0084000020", 8902 "Offcore": "1", 8903 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8904 "SampleAfterValue": "100003", 8905 "UMask": "0x1" 8906 }, 8907 { 8908 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 8909 "Counter": "0,1,2,3", 8910 "CounterHTOff": "0,1,2,3", 8911 "Deprecated": "1", 8912 "EventCode": "0xB7, 0xBB", 8913 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 8914 "MSRIndex": "0x1a6,0x1a7", 8915 "MSRValue": "0x063B800020", 8916 "Offcore": "1", 8917 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8918 "SampleAfterValue": "100003", 8919 "UMask": "0x1" 8920 }, 8921 { 8922 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8923 "Counter": "0,1,2,3", 8924 "CounterHTOff": "0,1,2,3", 8925 "Deprecated": "1", 8926 "EventCode": "0xB7, 0xBB", 8927 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 8928 "MSRIndex": "0x1a6,0x1a7", 8929 "MSRValue": "0x3F90000020", 8930 "Offcore": "1", 8931 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8932 "SampleAfterValue": "100003", 8933 "UMask": "0x1" 8934 }, 8935 { 8936 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8937 "Counter": "0,1,2,3", 8938 "CounterHTOff": "0,1,2,3", 8939 "Deprecated": "1", 8940 "EventCode": "0xB7, 0xBB", 8941 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 8942 "MSRIndex": "0x1a6,0x1a7", 8943 "MSRValue": "0x1010000020", 8944 "Offcore": "1", 8945 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8946 "SampleAfterValue": "100003", 8947 "UMask": "0x1" 8948 }, 8949 { 8950 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8951 "Counter": "0,1,2,3", 8952 "CounterHTOff": "0,1,2,3", 8953 "Deprecated": "1", 8954 "EventCode": "0xB7, 0xBB", 8955 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 8956 "MSRIndex": "0x1a6,0x1a7", 8957 "MSRValue": "0x0810000020", 8958 "Offcore": "1", 8959 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8960 "SampleAfterValue": "100003", 8961 "UMask": "0x1" 8962 }, 8963 { 8964 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8965 "Counter": "0,1,2,3", 8966 "CounterHTOff": "0,1,2,3", 8967 "Deprecated": "1", 8968 "EventCode": "0xB7, 0xBB", 8969 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 8970 "MSRIndex": "0x1a6,0x1a7", 8971 "MSRValue": "0x0410000020", 8972 "Offcore": "1", 8973 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8974 "SampleAfterValue": "100003", 8975 "UMask": "0x1" 8976 }, 8977 { 8978 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8979 "Counter": "0,1,2,3", 8980 "CounterHTOff": "0,1,2,3", 8981 "Deprecated": "1", 8982 "EventCode": "0xB7, 0xBB", 8983 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 8984 "MSRIndex": "0x1a6,0x1a7", 8985 "MSRValue": "0x0110000020", 8986 "Offcore": "1", 8987 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8988 "SampleAfterValue": "100003", 8989 "UMask": "0x1" 8990 }, 8991 { 8992 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8993 "Counter": "0,1,2,3", 8994 "CounterHTOff": "0,1,2,3", 8995 "Deprecated": "1", 8996 "EventCode": "0xB7, 0xBB", 8997 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 8998 "MSRIndex": "0x1a6,0x1a7", 8999 "MSRValue": "0x0210000020", 9000 "Offcore": "1", 9001 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9002 "SampleAfterValue": "100003", 9003 "UMask": "0x1" 9004 }, 9005 { 9006 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 9007 "Counter": "0,1,2,3", 9008 "CounterHTOff": "0,1,2,3", 9009 "Deprecated": "1", 9010 "EventCode": "0xB7, 0xBB", 9011 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 9012 "MSRIndex": "0x1a6,0x1a7", 9013 "MSRValue": "0x0090000020", 9014 "Offcore": "1", 9015 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9016 "SampleAfterValue": "100003", 9017 "UMask": "0x1" 9018 }, 9019 { 9020 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 9021 "Counter": "0,1,2,3", 9022 "CounterHTOff": "0,1,2,3", 9023 "Deprecated": "1", 9024 "EventCode": "0xB7, 0xBB", 9025 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 9026 "MSRIndex": "0x1a6,0x1a7", 9027 "MSRValue": "0x3FBC000080", 9028 "Offcore": "1", 9029 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9030 "SampleAfterValue": "100003", 9031 "UMask": "0x1" 9032 }, 9033 { 9034 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", 9035 "Counter": "0,1,2,3", 9036 "CounterHTOff": "0,1,2,3", 9037 "Deprecated": "1", 9038 "EventCode": "0xB7, 0xBB", 9039 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", 9040 "MSRIndex": "0x1a6,0x1a7", 9041 "MSRValue": "0x103C000080", 9042 "Offcore": "1", 9043 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9044 "SampleAfterValue": "100003", 9045 "UMask": "0x1" 9046 }, 9047 { 9048 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 9049 "Counter": "0,1,2,3", 9050 "CounterHTOff": "0,1,2,3", 9051 "Deprecated": "1", 9052 "EventCode": "0xB7, 0xBB", 9053 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", 9054 "MSRIndex": "0x1a6,0x1a7", 9055 "MSRValue": "0x083C000080", 9056 "Offcore": "1", 9057 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9058 "SampleAfterValue": "100003", 9059 "UMask": "0x1" 9060 }, 9061 { 9062 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 9063 "Counter": "0,1,2,3", 9064 "CounterHTOff": "0,1,2,3", 9065 "Deprecated": "1", 9066 "EventCode": "0xB7, 0xBB", 9067 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", 9068 "MSRIndex": "0x1a6,0x1a7", 9069 "MSRValue": "0x043C000080", 9070 "Offcore": "1", 9071 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9072 "SampleAfterValue": "100003", 9073 "UMask": "0x1" 9074 }, 9075 { 9076 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 9077 "Counter": "0,1,2,3", 9078 "CounterHTOff": "0,1,2,3", 9079 "Deprecated": "1", 9080 "EventCode": "0xB7, 0xBB", 9081 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", 9082 "MSRIndex": "0x1a6,0x1a7", 9083 "MSRValue": "0x013C000080", 9084 "Offcore": "1", 9085 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9086 "SampleAfterValue": "100003", 9087 "UMask": "0x1" 9088 }, 9089 { 9090 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 9091 "Counter": "0,1,2,3", 9092 "CounterHTOff": "0,1,2,3", 9093 "Deprecated": "1", 9094 "EventCode": "0xB7, 0xBB", 9095 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 9096 "MSRIndex": "0x1a6,0x1a7", 9097 "MSRValue": "0x103FC00080", 9098 "Offcore": "1", 9099 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9100 "SampleAfterValue": "100003", 9101 "UMask": "0x1" 9102 }, 9103 { 9104 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9105 "Counter": "0,1,2,3", 9106 "CounterHTOff": "0,1,2,3", 9107 "Deprecated": "1", 9108 "EventCode": "0xB7, 0xBB", 9109 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 9110 "MSRIndex": "0x1a6,0x1a7", 9111 "MSRValue": "0x083FC00080", 9112 "Offcore": "1", 9113 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9114 "SampleAfterValue": "100003", 9115 "UMask": "0x1" 9116 }, 9117 { 9118 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 9119 "Counter": "0,1,2,3", 9120 "CounterHTOff": "0,1,2,3", 9121 "Deprecated": "1", 9122 "EventCode": "0xB7, 0xBB", 9123 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", 9124 "MSRIndex": "0x1a6,0x1a7", 9125 "MSRValue": "0x023C000080", 9126 "Offcore": "1", 9127 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9128 "SampleAfterValue": "100003", 9129 "UMask": "0x1" 9130 }, 9131 { 9132 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 9133 "Counter": "0,1,2,3", 9134 "CounterHTOff": "0,1,2,3", 9135 "Deprecated": "1", 9136 "EventCode": "0xB7, 0xBB", 9137 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", 9138 "MSRIndex": "0x1a6,0x1a7", 9139 "MSRValue": "0x00BC000080", 9140 "Offcore": "1", 9141 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9142 "SampleAfterValue": "100003", 9143 "UMask": "0x1" 9144 }, 9145 { 9146 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 9147 "Counter": "0,1,2,3", 9148 "CounterHTOff": "0,1,2,3", 9149 "Deprecated": "1", 9150 "EventCode": "0xB7, 0xBB", 9151 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 9152 "MSRIndex": "0x1a6,0x1a7", 9153 "MSRValue": "0x3F84000080", 9154 "Offcore": "1", 9155 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9156 "SampleAfterValue": "100003", 9157 "UMask": "0x1" 9158 }, 9159 { 9160 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 9161 "Counter": "0,1,2,3", 9162 "CounterHTOff": "0,1,2,3", 9163 "Deprecated": "1", 9164 "EventCode": "0xB7, 0xBB", 9165 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 9166 "MSRIndex": "0x1a6,0x1a7", 9167 "MSRValue": "0x1004000080", 9168 "Offcore": "1", 9169 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9170 "SampleAfterValue": "100003", 9171 "UMask": "0x1" 9172 }, 9173 { 9174 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 9175 "Counter": "0,1,2,3", 9176 "CounterHTOff": "0,1,2,3", 9177 "Deprecated": "1", 9178 "EventCode": "0xB7, 0xBB", 9179 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 9180 "MSRIndex": "0x1a6,0x1a7", 9181 "MSRValue": "0x0804000080", 9182 "Offcore": "1", 9183 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9184 "SampleAfterValue": "100003", 9185 "UMask": "0x1" 9186 }, 9187 { 9188 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 9189 "Counter": "0,1,2,3", 9190 "CounterHTOff": "0,1,2,3", 9191 "Deprecated": "1", 9192 "EventCode": "0xB7, 0xBB", 9193 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 9194 "MSRIndex": "0x1a6,0x1a7", 9195 "MSRValue": "0x0404000080", 9196 "Offcore": "1", 9197 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9198 "SampleAfterValue": "100003", 9199 "UMask": "0x1" 9200 }, 9201 { 9202 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 9203 "Counter": "0,1,2,3", 9204 "CounterHTOff": "0,1,2,3", 9205 "Deprecated": "1", 9206 "EventCode": "0xB7, 0xBB", 9207 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 9208 "MSRIndex": "0x1a6,0x1a7", 9209 "MSRValue": "0x0104000080", 9210 "Offcore": "1", 9211 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9212 "SampleAfterValue": "100003", 9213 "UMask": "0x1" 9214 }, 9215 { 9216 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 9217 "Counter": "0,1,2,3", 9218 "CounterHTOff": "0,1,2,3", 9219 "Deprecated": "1", 9220 "EventCode": "0xB7, 0xBB", 9221 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 9222 "MSRIndex": "0x1a6,0x1a7", 9223 "MSRValue": "0x0204000080", 9224 "Offcore": "1", 9225 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9226 "SampleAfterValue": "100003", 9227 "UMask": "0x1" 9228 }, 9229 { 9230 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9231 "Counter": "0,1,2,3", 9232 "CounterHTOff": "0,1,2,3", 9233 "Deprecated": "1", 9234 "EventCode": "0xB7, 0xBB", 9235 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9236 "MSRIndex": "0x1a6,0x1a7", 9237 "MSRValue": "0x0604000080", 9238 "Offcore": "1", 9239 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9240 "SampleAfterValue": "100003", 9241 "UMask": "0x1" 9242 }, 9243 { 9244 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 9245 "Counter": "0,1,2,3", 9246 "CounterHTOff": "0,1,2,3", 9247 "Deprecated": "1", 9248 "EventCode": "0xB7, 0xBB", 9249 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 9250 "MSRIndex": "0x1a6,0x1a7", 9251 "MSRValue": "0x0084000080", 9252 "Offcore": "1", 9253 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9254 "SampleAfterValue": "100003", 9255 "UMask": "0x1" 9256 }, 9257 { 9258 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9259 "Counter": "0,1,2,3", 9260 "CounterHTOff": "0,1,2,3", 9261 "Deprecated": "1", 9262 "EventCode": "0xB7, 0xBB", 9263 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9264 "MSRIndex": "0x1a6,0x1a7", 9265 "MSRValue": "0x063B800080", 9266 "Offcore": "1", 9267 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9268 "SampleAfterValue": "100003", 9269 "UMask": "0x1" 9270 }, 9271 { 9272 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 9273 "Counter": "0,1,2,3", 9274 "CounterHTOff": "0,1,2,3", 9275 "Deprecated": "1", 9276 "EventCode": "0xB7, 0xBB", 9277 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 9278 "MSRIndex": "0x1a6,0x1a7", 9279 "MSRValue": "0x3F90000080", 9280 "Offcore": "1", 9281 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9282 "SampleAfterValue": "100003", 9283 "UMask": "0x1" 9284 }, 9285 { 9286 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 9287 "Counter": "0,1,2,3", 9288 "CounterHTOff": "0,1,2,3", 9289 "Deprecated": "1", 9290 "EventCode": "0xB7, 0xBB", 9291 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 9292 "MSRIndex": "0x1a6,0x1a7", 9293 "MSRValue": "0x1010000080", 9294 "Offcore": "1", 9295 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9296 "SampleAfterValue": "100003", 9297 "UMask": "0x1" 9298 }, 9299 { 9300 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 9301 "Counter": "0,1,2,3", 9302 "CounterHTOff": "0,1,2,3", 9303 "Deprecated": "1", 9304 "EventCode": "0xB7, 0xBB", 9305 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 9306 "MSRIndex": "0x1a6,0x1a7", 9307 "MSRValue": "0x0810000080", 9308 "Offcore": "1", 9309 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9310 "SampleAfterValue": "100003", 9311 "UMask": "0x1" 9312 }, 9313 { 9314 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 9315 "Counter": "0,1,2,3", 9316 "CounterHTOff": "0,1,2,3", 9317 "Deprecated": "1", 9318 "EventCode": "0xB7, 0xBB", 9319 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 9320 "MSRIndex": "0x1a6,0x1a7", 9321 "MSRValue": "0x0410000080", 9322 "Offcore": "1", 9323 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9324 "SampleAfterValue": "100003", 9325 "UMask": "0x1" 9326 }, 9327 { 9328 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 9329 "Counter": "0,1,2,3", 9330 "CounterHTOff": "0,1,2,3", 9331 "Deprecated": "1", 9332 "EventCode": "0xB7, 0xBB", 9333 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 9334 "MSRIndex": "0x1a6,0x1a7", 9335 "MSRValue": "0x0110000080", 9336 "Offcore": "1", 9337 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9338 "SampleAfterValue": "100003", 9339 "UMask": "0x1" 9340 }, 9341 { 9342 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 9343 "Counter": "0,1,2,3", 9344 "CounterHTOff": "0,1,2,3", 9345 "Deprecated": "1", 9346 "EventCode": "0xB7, 0xBB", 9347 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 9348 "MSRIndex": "0x1a6,0x1a7", 9349 "MSRValue": "0x0210000080", 9350 "Offcore": "1", 9351 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9352 "SampleAfterValue": "100003", 9353 "UMask": "0x1" 9354 }, 9355 { 9356 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 9357 "Counter": "0,1,2,3", 9358 "CounterHTOff": "0,1,2,3", 9359 "Deprecated": "1", 9360 "EventCode": "0xB7, 0xBB", 9361 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 9362 "MSRIndex": "0x1a6,0x1a7", 9363 "MSRValue": "0x0090000080", 9364 "Offcore": "1", 9365 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9366 "SampleAfterValue": "100003", 9367 "UMask": "0x1" 9368 }, 9369 { 9370 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", 9371 "Counter": "0,1,2,3", 9372 "CounterHTOff": "0,1,2,3", 9373 "Deprecated": "1", 9374 "EventCode": "0xB7, 0xBB", 9375 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", 9376 "MSRIndex": "0x1a6,0x1a7", 9377 "MSRValue": "0x3FBC000100", 9378 "Offcore": "1", 9379 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9380 "SampleAfterValue": "100003", 9381 "UMask": "0x1" 9382 }, 9383 { 9384 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", 9385 "Counter": "0,1,2,3", 9386 "CounterHTOff": "0,1,2,3", 9387 "Deprecated": "1", 9388 "EventCode": "0xB7, 0xBB", 9389 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", 9390 "MSRIndex": "0x1a6,0x1a7", 9391 "MSRValue": "0x103C000100", 9392 "Offcore": "1", 9393 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9394 "SampleAfterValue": "100003", 9395 "UMask": "0x1" 9396 }, 9397 { 9398 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 9399 "Counter": "0,1,2,3", 9400 "CounterHTOff": "0,1,2,3", 9401 "Deprecated": "1", 9402 "EventCode": "0xB7, 0xBB", 9403 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", 9404 "MSRIndex": "0x1a6,0x1a7", 9405 "MSRValue": "0x083C000100", 9406 "Offcore": "1", 9407 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9408 "SampleAfterValue": "100003", 9409 "UMask": "0x1" 9410 }, 9411 { 9412 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 9413 "Counter": "0,1,2,3", 9414 "CounterHTOff": "0,1,2,3", 9415 "Deprecated": "1", 9416 "EventCode": "0xB7, 0xBB", 9417 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", 9418 "MSRIndex": "0x1a6,0x1a7", 9419 "MSRValue": "0x043C000100", 9420 "Offcore": "1", 9421 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9422 "SampleAfterValue": "100003", 9423 "UMask": "0x1" 9424 }, 9425 { 9426 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", 9427 "Counter": "0,1,2,3", 9428 "CounterHTOff": "0,1,2,3", 9429 "Deprecated": "1", 9430 "EventCode": "0xB7, 0xBB", 9431 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", 9432 "MSRIndex": "0x1a6,0x1a7", 9433 "MSRValue": "0x013C000100", 9434 "Offcore": "1", 9435 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9436 "SampleAfterValue": "100003", 9437 "UMask": "0x1" 9438 }, 9439 { 9440 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", 9441 "Counter": "0,1,2,3", 9442 "CounterHTOff": "0,1,2,3", 9443 "Deprecated": "1", 9444 "EventCode": "0xB7, 0xBB", 9445 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", 9446 "MSRIndex": "0x1a6,0x1a7", 9447 "MSRValue": "0x103FC00100", 9448 "Offcore": "1", 9449 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9450 "SampleAfterValue": "100003", 9451 "UMask": "0x1" 9452 }, 9453 { 9454 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9455 "Counter": "0,1,2,3", 9456 "CounterHTOff": "0,1,2,3", 9457 "Deprecated": "1", 9458 "EventCode": "0xB7, 0xBB", 9459 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 9460 "MSRIndex": "0x1a6,0x1a7", 9461 "MSRValue": "0x083FC00100", 9462 "Offcore": "1", 9463 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9464 "SampleAfterValue": "100003", 9465 "UMask": "0x1" 9466 }, 9467 { 9468 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", 9469 "Counter": "0,1,2,3", 9470 "CounterHTOff": "0,1,2,3", 9471 "Deprecated": "1", 9472 "EventCode": "0xB7, 0xBB", 9473 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", 9474 "MSRIndex": "0x1a6,0x1a7", 9475 "MSRValue": "0x023C000100", 9476 "Offcore": "1", 9477 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9478 "SampleAfterValue": "100003", 9479 "UMask": "0x1" 9480 }, 9481 { 9482 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", 9483 "Counter": "0,1,2,3", 9484 "CounterHTOff": "0,1,2,3", 9485 "Deprecated": "1", 9486 "EventCode": "0xB7, 0xBB", 9487 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", 9488 "MSRIndex": "0x1a6,0x1a7", 9489 "MSRValue": "0x00BC000100", 9490 "Offcore": "1", 9491 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9492 "SampleAfterValue": "100003", 9493 "UMask": "0x1" 9494 }, 9495 { 9496 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 9497 "Counter": "0,1,2,3", 9498 "CounterHTOff": "0,1,2,3", 9499 "Deprecated": "1", 9500 "EventCode": "0xB7, 0xBB", 9501 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 9502 "MSRIndex": "0x1a6,0x1a7", 9503 "MSRValue": "0x3F84000100", 9504 "Offcore": "1", 9505 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9506 "SampleAfterValue": "100003", 9507 "UMask": "0x1" 9508 }, 9509 { 9510 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 9511 "Counter": "0,1,2,3", 9512 "CounterHTOff": "0,1,2,3", 9513 "Deprecated": "1", 9514 "EventCode": "0xB7, 0xBB", 9515 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", 9516 "MSRIndex": "0x1a6,0x1a7", 9517 "MSRValue": "0x1004000100", 9518 "Offcore": "1", 9519 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9520 "SampleAfterValue": "100003", 9521 "UMask": "0x1" 9522 }, 9523 { 9524 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 9525 "Counter": "0,1,2,3", 9526 "CounterHTOff": "0,1,2,3", 9527 "Deprecated": "1", 9528 "EventCode": "0xB7, 0xBB", 9529 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", 9530 "MSRIndex": "0x1a6,0x1a7", 9531 "MSRValue": "0x0804000100", 9532 "Offcore": "1", 9533 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9534 "SampleAfterValue": "100003", 9535 "UMask": "0x1" 9536 }, 9537 { 9538 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 9539 "Counter": "0,1,2,3", 9540 "CounterHTOff": "0,1,2,3", 9541 "Deprecated": "1", 9542 "EventCode": "0xB7, 0xBB", 9543 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", 9544 "MSRIndex": "0x1a6,0x1a7", 9545 "MSRValue": "0x0404000100", 9546 "Offcore": "1", 9547 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9548 "SampleAfterValue": "100003", 9549 "UMask": "0x1" 9550 }, 9551 { 9552 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 9553 "Counter": "0,1,2,3", 9554 "CounterHTOff": "0,1,2,3", 9555 "Deprecated": "1", 9556 "EventCode": "0xB7, 0xBB", 9557 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", 9558 "MSRIndex": "0x1a6,0x1a7", 9559 "MSRValue": "0x0104000100", 9560 "Offcore": "1", 9561 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9562 "SampleAfterValue": "100003", 9563 "UMask": "0x1" 9564 }, 9565 { 9566 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 9567 "Counter": "0,1,2,3", 9568 "CounterHTOff": "0,1,2,3", 9569 "Deprecated": "1", 9570 "EventCode": "0xB7, 0xBB", 9571 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 9572 "MSRIndex": "0x1a6,0x1a7", 9573 "MSRValue": "0x0204000100", 9574 "Offcore": "1", 9575 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9576 "SampleAfterValue": "100003", 9577 "UMask": "0x1" 9578 }, 9579 { 9580 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9581 "Counter": "0,1,2,3", 9582 "CounterHTOff": "0,1,2,3", 9583 "Deprecated": "1", 9584 "EventCode": "0xB7, 0xBB", 9585 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 9586 "MSRIndex": "0x1a6,0x1a7", 9587 "MSRValue": "0x0604000100", 9588 "Offcore": "1", 9589 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9590 "SampleAfterValue": "100003", 9591 "UMask": "0x1" 9592 }, 9593 { 9594 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 9595 "Counter": "0,1,2,3", 9596 "CounterHTOff": "0,1,2,3", 9597 "Deprecated": "1", 9598 "EventCode": "0xB7, 0xBB", 9599 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 9600 "MSRIndex": "0x1a6,0x1a7", 9601 "MSRValue": "0x0084000100", 9602 "Offcore": "1", 9603 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9604 "SampleAfterValue": "100003", 9605 "UMask": "0x1" 9606 }, 9607 { 9608 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9609 "Counter": "0,1,2,3", 9610 "CounterHTOff": "0,1,2,3", 9611 "Deprecated": "1", 9612 "EventCode": "0xB7, 0xBB", 9613 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 9614 "MSRIndex": "0x1a6,0x1a7", 9615 "MSRValue": "0x063B800100", 9616 "Offcore": "1", 9617 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9618 "SampleAfterValue": "100003", 9619 "UMask": "0x1" 9620 }, 9621 { 9622 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 9623 "Counter": "0,1,2,3", 9624 "CounterHTOff": "0,1,2,3", 9625 "Deprecated": "1", 9626 "EventCode": "0xB7, 0xBB", 9627 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", 9628 "MSRIndex": "0x1a6,0x1a7", 9629 "MSRValue": "0x3F90000100", 9630 "Offcore": "1", 9631 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9632 "SampleAfterValue": "100003", 9633 "UMask": "0x1" 9634 }, 9635 { 9636 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 9637 "Counter": "0,1,2,3", 9638 "CounterHTOff": "0,1,2,3", 9639 "Deprecated": "1", 9640 "EventCode": "0xB7, 0xBB", 9641 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", 9642 "MSRIndex": "0x1a6,0x1a7", 9643 "MSRValue": "0x1010000100", 9644 "Offcore": "1", 9645 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9646 "SampleAfterValue": "100003", 9647 "UMask": "0x1" 9648 }, 9649 { 9650 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 9651 "Counter": "0,1,2,3", 9652 "CounterHTOff": "0,1,2,3", 9653 "Deprecated": "1", 9654 "EventCode": "0xB7, 0xBB", 9655 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", 9656 "MSRIndex": "0x1a6,0x1a7", 9657 "MSRValue": "0x0810000100", 9658 "Offcore": "1", 9659 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9660 "SampleAfterValue": "100003", 9661 "UMask": "0x1" 9662 }, 9663 { 9664 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 9665 "Counter": "0,1,2,3", 9666 "CounterHTOff": "0,1,2,3", 9667 "Deprecated": "1", 9668 "EventCode": "0xB7, 0xBB", 9669 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", 9670 "MSRIndex": "0x1a6,0x1a7", 9671 "MSRValue": "0x0410000100", 9672 "Offcore": "1", 9673 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9674 "SampleAfterValue": "100003", 9675 "UMask": "0x1" 9676 }, 9677 { 9678 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 9679 "Counter": "0,1,2,3", 9680 "CounterHTOff": "0,1,2,3", 9681 "Deprecated": "1", 9682 "EventCode": "0xB7, 0xBB", 9683 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", 9684 "MSRIndex": "0x1a6,0x1a7", 9685 "MSRValue": "0x0110000100", 9686 "Offcore": "1", 9687 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9688 "SampleAfterValue": "100003", 9689 "UMask": "0x1" 9690 }, 9691 { 9692 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 9693 "Counter": "0,1,2,3", 9694 "CounterHTOff": "0,1,2,3", 9695 "Deprecated": "1", 9696 "EventCode": "0xB7, 0xBB", 9697 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", 9698 "MSRIndex": "0x1a6,0x1a7", 9699 "MSRValue": "0x0210000100", 9700 "Offcore": "1", 9701 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9702 "SampleAfterValue": "100003", 9703 "UMask": "0x1" 9704 }, 9705 { 9706 "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 9707 "Counter": "0,1,2,3", 9708 "CounterHTOff": "0,1,2,3", 9709 "Deprecated": "1", 9710 "EventCode": "0xB7, 0xBB", 9711 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", 9712 "MSRIndex": "0x1a6,0x1a7", 9713 "MSRValue": "0x0090000100", 9714 "Offcore": "1", 9715 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 9716 "SampleAfterValue": "100003", 9717 "UMask": "0x1" 9718 }, 9719 { 9720 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 9721 "Counter": "0,1,2,3", 9722 "CounterHTOff": "0,1,2,3,4,5,6,7", 9723 "EventCode": "0xC9", 9724 "EventName": "RTM_RETIRED.ABORTED", 9725 "PEBS": "1", 9726 "PublicDescription": "Number of times RTM abort was triggered.", 9727 "SampleAfterValue": "2000003", 9728 "UMask": "0x4" 9729 }, 9730 { 9731 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 9732 "Counter": "0,1,2,3", 9733 "CounterHTOff": "0,1,2,3,4,5,6,7", 9734 "EventCode": "0xC9", 9735 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 9736 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 9737 "SampleAfterValue": "2000003", 9738 "UMask": "0x80" 9739 }, 9740 { 9741 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 9742 "Counter": "0,1,2,3", 9743 "CounterHTOff": "0,1,2,3,4,5,6,7", 9744 "EventCode": "0xC9", 9745 "EventName": "RTM_RETIRED.ABORTED_MEM", 9746 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 9747 "SampleAfterValue": "2000003", 9748 "UMask": "0x8" 9749 }, 9750 { 9751 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 9752 "Counter": "0,1,2,3", 9753 "CounterHTOff": "0,1,2,3,4,5,6,7", 9754 "EventCode": "0xC9", 9755 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 9756 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 9757 "SampleAfterValue": "2000003", 9758 "UMask": "0x40" 9759 }, 9760 { 9761 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 9762 "Counter": "0,1,2,3", 9763 "CounterHTOff": "0,1,2,3,4,5,6,7", 9764 "EventCode": "0xC9", 9765 "EventName": "RTM_RETIRED.ABORTED_TIMER", 9766 "SampleAfterValue": "2000003", 9767 "UMask": "0x10" 9768 }, 9769 { 9770 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 9771 "Counter": "0,1,2,3", 9772 "CounterHTOff": "0,1,2,3,4,5,6,7", 9773 "EventCode": "0xC9", 9774 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 9775 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 9776 "SampleAfterValue": "2000003", 9777 "UMask": "0x20" 9778 }, 9779 { 9780 "BriefDescription": "Number of times an RTM execution successfully committed", 9781 "Counter": "0,1,2,3", 9782 "CounterHTOff": "0,1,2,3,4,5,6,7", 9783 "EventCode": "0xC9", 9784 "EventName": "RTM_RETIRED.COMMIT", 9785 "PublicDescription": "Number of times RTM commit succeeded.", 9786 "SampleAfterValue": "2000003", 9787 "UMask": "0x2" 9788 }, 9789 { 9790 "BriefDescription": "Number of times an RTM execution started.", 9791 "Counter": "0,1,2,3", 9792 "CounterHTOff": "0,1,2,3,4,5,6,7", 9793 "EventCode": "0xC9", 9794 "EventName": "RTM_RETIRED.START", 9795 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 9796 "SampleAfterValue": "2000003", 9797 "UMask": "0x1" 9798 }, 9799 { 9800 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 9801 "Counter": "0,1,2,3", 9802 "CounterHTOff": "0,1,2,3,4,5,6,7", 9803 "EventCode": "0x5d", 9804 "EventName": "TX_EXEC.MISC1", 9805 "SampleAfterValue": "2000003", 9806 "UMask": "0x1" 9807 }, 9808 { 9809 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 9810 "Counter": "0,1,2,3", 9811 "CounterHTOff": "0,1,2,3,4,5,6,7", 9812 "EventCode": "0x5d", 9813 "EventName": "TX_EXEC.MISC2", 9814 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 9815 "SampleAfterValue": "2000003", 9816 "UMask": "0x2" 9817 }, 9818 { 9819 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 9820 "Counter": "0,1,2,3", 9821 "CounterHTOff": "0,1,2,3,4,5,6,7", 9822 "EventCode": "0x5d", 9823 "EventName": "TX_EXEC.MISC3", 9824 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 9825 "SampleAfterValue": "2000003", 9826 "UMask": "0x4" 9827 }, 9828 { 9829 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 9830 "Counter": "0,1,2,3", 9831 "CounterHTOff": "0,1,2,3,4,5,6,7", 9832 "EventCode": "0x5d", 9833 "EventName": "TX_EXEC.MISC4", 9834 "PublicDescription": "RTM region detected inside HLE.", 9835 "SampleAfterValue": "2000003", 9836 "UMask": "0x8" 9837 }, 9838 { 9839 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 9840 "Counter": "0,1,2,3", 9841 "CounterHTOff": "0,1,2,3,4,5,6,7", 9842 "EventCode": "0x5d", 9843 "EventName": "TX_EXEC.MISC5", 9844 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 9845 "SampleAfterValue": "2000003", 9846 "UMask": "0x10" 9847 }, 9848 { 9849 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 9850 "Counter": "0,1,2,3", 9851 "CounterHTOff": "0,1,2,3,4,5,6,7", 9852 "EventCode": "0x54", 9853 "EventName": "TX_MEM.ABORT_CAPACITY", 9854 "SampleAfterValue": "2000003", 9855 "UMask": "0x2" 9856 }, 9857 { 9858 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 9859 "Counter": "0,1,2,3", 9860 "CounterHTOff": "0,1,2,3,4,5,6,7", 9861 "EventCode": "0x54", 9862 "EventName": "TX_MEM.ABORT_CONFLICT", 9863 "PublicDescription": "Number of times a TSX line had a cache conflict.", 9864 "SampleAfterValue": "2000003", 9865 "UMask": "0x1" 9866 }, 9867 { 9868 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 9869 "Counter": "0,1,2,3", 9870 "CounterHTOff": "0,1,2,3,4,5,6,7", 9871 "EventCode": "0x54", 9872 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 9873 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 9874 "SampleAfterValue": "2000003", 9875 "UMask": "0x10" 9876 }, 9877 { 9878 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 9879 "Counter": "0,1,2,3", 9880 "CounterHTOff": "0,1,2,3,4,5,6,7", 9881 "EventCode": "0x54", 9882 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 9883 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 9884 "SampleAfterValue": "2000003", 9885 "UMask": "0x8" 9886 }, 9887 { 9888 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 9889 "Counter": "0,1,2,3", 9890 "CounterHTOff": "0,1,2,3,4,5,6,7", 9891 "EventCode": "0x54", 9892 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 9893 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 9894 "SampleAfterValue": "2000003", 9895 "UMask": "0x20" 9896 }, 9897 { 9898 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 9899 "Counter": "0,1,2,3", 9900 "CounterHTOff": "0,1,2,3,4,5,6,7", 9901 "EventCode": "0x54", 9902 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 9903 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 9904 "SampleAfterValue": "2000003", 9905 "UMask": "0x4" 9906 }, 9907 { 9908 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 9909 "Counter": "0,1,2,3", 9910 "CounterHTOff": "0,1,2,3,4,5,6,7", 9911 "EventCode": "0x54", 9912 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 9913 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 9914 "SampleAfterValue": "2000003", 9915 "UMask": "0x40" 9916 } 9917]