1[
2    {
3        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3",
6        "EventCode": "0x54",
7        "EventName": "TX_MEM.ABORT_CONFLICT",
8        "PEBScounters": "0,1,2,3",
9        "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
10        "SampleAfterValue": "100003",
11        "Speculative": "1",
12        "UMask": "0x1"
13    },
14    {
15        "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
16        "CollectPEBSRecord": "2",
17        "Counter": "0,1,2,3,4,5,6,7",
18        "EventCode": "0xc8",
19        "EventName": "HLE_RETIRED.ABORTED",
20        "PEBScounters": "0,1,2,3,4,5,6,7",
21        "PublicDescription": "Counts the number of times HLE abort was triggered.",
22        "SampleAfterValue": "100003",
23        "UMask": "0x4"
24    },
25    {
26        "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.",
27        "CollectPEBSRecord": "2",
28        "Counter": "0,1,2,3",
29        "EventCode": "0xB7, 0xBB",
30        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
31        "MSRIndex": "0x1a6,0x1a7",
32        "MSRValue": "0x3FFFC00001",
33        "Offcore": "1",
34        "PEBScounters": "0,1,2,3",
35        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
36        "SampleAfterValue": "100003",
37        "Speculative": "1",
38        "UMask": "0x1"
39    },
40    {
41        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
42        "CollectPEBSRecord": "2",
43        "Counter": "0,1,2,3,4,5,6,7",
44        "Data_LA": "1",
45        "EventCode": "0xcd",
46        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
47        "MSRIndex": "0x3F6",
48        "MSRValue": "0x10",
49        "PEBS": "2",
50        "PEBScounters": "0,1,2,3,4,5,6,7",
51        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
52        "SampleAfterValue": "20011",
53        "TakenAlone": "1",
54        "UMask": "0x1"
55    },
56    {
57        "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that was not supplied by the L3 cache.",
58        "CollectPEBSRecord": "2",
59        "Counter": "0,1,2,3",
60        "EventCode": "0xB7, 0xBB",
61        "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
62        "MSRIndex": "0x1a6,0x1a7",
63        "MSRValue": "0x3FFFC00010",
64        "Offcore": "1",
65        "PEBScounters": "0,1,2,3",
66        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
67        "SampleAfterValue": "100003",
68        "Speculative": "1",
69        "UMask": "0x1"
70    },
71    {
72        "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
73        "CollectPEBSRecord": "2",
74        "Counter": "0,1,2,3,4,5,6,7",
75        "EventCode": "0xc8",
76        "EventName": "HLE_RETIRED.ABORTED_MEM",
77        "PEBScounters": "0,1,2,3,4,5,6,7",
78        "PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
79        "SampleAfterValue": "100003",
80        "UMask": "0x8"
81    },
82    {
83        "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
84        "CollectPEBSRecord": "2",
85        "Counter": "0,1,2,3",
86        "EventCode": "0x54",
87        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
88        "PEBScounters": "0,1,2,3",
89        "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
90        "SampleAfterValue": "100003",
91        "Speculative": "1",
92        "UMask": "0x20"
93    },
94    {
95        "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
96        "CollectPEBSRecord": "2",
97        "Counter": "0,1,2,3",
98        "EventCode": "0x54",
99        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
100        "PEBScounters": "0,1,2,3",
101        "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
102        "SampleAfterValue": "100003",
103        "Speculative": "1",
104        "UMask": "0x8"
105    },
106    {
107        "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
108        "CollectPEBSRecord": "2",
109        "Counter": "0,1,2,3,4,5,6,7",
110        "EventCode": "0x5d",
111        "EventName": "TX_EXEC.MISC3",
112        "PEBScounters": "0,1,2,3,4,5,6,7",
113        "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
114        "SampleAfterValue": "100003",
115        "Speculative": "1",
116        "UMask": "0x4"
117    },
118    {
119        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
120        "CollectPEBSRecord": "2",
121        "Counter": "0,1,2,3,4,5,6,7",
122        "EventCode": "0x5d",
123        "EventName": "TX_EXEC.MISC2",
124        "PEBScounters": "0,1,2,3,4,5,6,7",
125        "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
126        "SampleAfterValue": "100003",
127        "Speculative": "1",
128        "UMask": "0x2"
129    },
130    {
131        "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.",
132        "CollectPEBSRecord": "2",
133        "Counter": "0,1,2,3",
134        "CounterMask": "1",
135        "EventCode": "0x60",
136        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
137        "PEBScounters": "0,1,2,3",
138        "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
139        "SampleAfterValue": "1000003",
140        "Speculative": "1",
141        "UMask": "0x10"
142    },
143    {
144        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.",
145        "CollectPEBSRecord": "2",
146        "Counter": "0,1,2,3",
147        "EventCode": "0xB7, 0xBB",
148        "EventName": "OCR.DEMAND_RFO.L3_MISS",
149        "MSRIndex": "0x1a6,0x1a7",
150        "MSRValue": "0x3FFFC00002",
151        "Offcore": "1",
152        "PEBScounters": "0,1,2,3",
153        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
154        "SampleAfterValue": "100003",
155        "Speculative": "1",
156        "UMask": "0x1"
157    },
158    {
159        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
160        "CollectPEBSRecord": "2",
161        "Counter": "0,1,2,3,4,5,6,7",
162        "Data_LA": "1",
163        "EventCode": "0xcd",
164        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
165        "MSRIndex": "0x3F6",
166        "MSRValue": "0x200",
167        "PEBS": "2",
168        "PEBScounters": "0,1,2,3,4,5,6,7",
169        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
170        "SampleAfterValue": "101",
171        "TakenAlone": "1",
172        "UMask": "0x1"
173    },
174    {
175        "BriefDescription": "Number of times an RTM execution successfully committed",
176        "CollectPEBSRecord": "2",
177        "Counter": "0,1,2,3,4,5,6,7",
178        "EventCode": "0xc9",
179        "EventName": "RTM_RETIRED.COMMIT",
180        "PEBScounters": "0,1,2,3,4,5,6,7",
181        "PublicDescription": "Counts the number of times RTM commit succeeded.",
182        "SampleAfterValue": "100003",
183        "UMask": "0x2"
184    },
185    {
186        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
187        "CollectPEBSRecord": "2",
188        "Counter": "0,1,2,3",
189        "EventCode": "0x54",
190        "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
191        "PEBScounters": "0,1,2,3",
192        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
193        "SampleAfterValue": "100003",
194        "Speculative": "1",
195        "UMask": "0x2"
196    },
197    {
198        "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
199        "CollectPEBSRecord": "2",
200        "Counter": "0,1,2,3,4,5,6,7",
201        "EventCode": "0xc8",
202        "EventName": "HLE_RETIRED.ABORTED_EVENTS",
203        "PEBScounters": "0,1,2,3,4,5,6,7",
204        "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
205        "SampleAfterValue": "100003",
206        "UMask": "0x80"
207    },
208    {
209        "BriefDescription": "Number of times an HLE execution successfully committed",
210        "CollectPEBSRecord": "2",
211        "Counter": "0,1,2,3,4,5,6,7",
212        "EventCode": "0xc8",
213        "EventName": "HLE_RETIRED.COMMIT",
214        "PEBScounters": "0,1,2,3,4,5,6,7",
215        "PublicDescription": "Counts the number of times HLE commit succeeded.",
216        "SampleAfterValue": "100003",
217        "UMask": "0x2"
218    },
219    {
220        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
221        "CollectPEBSRecord": "2",
222        "Counter": "0,1,2,3,4,5,6,7",
223        "EventCode": "0xc9",
224        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
225        "PEBScounters": "0,1,2,3,4,5,6,7",
226        "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
227        "SampleAfterValue": "100003",
228        "UMask": "0x40"
229    },
230    {
231        "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
232        "CollectPEBSRecord": "2",
233        "Counter": "0,1,2,3,4,5,6,7",
234        "EventCode": "0xc3",
235        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
236        "PEBScounters": "0,1,2,3,4,5,6,7",
237        "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
238        "SampleAfterValue": "100003",
239        "Speculative": "1",
240        "UMask": "0x2"
241    },
242    {
243        "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
244        "CollectPEBSRecord": "2",
245        "Counter": "0,1,2,3",
246        "EventCode": "0x54",
247        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
248        "PEBScounters": "0,1,2,3",
249        "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
250        "SampleAfterValue": "100003",
251        "Speculative": "1",
252        "UMask": "0x10"
253    },
254    {
255        "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.",
256        "CollectPEBSRecord": "2",
257        "Counter": "0,1,2,3",
258        "EventCode": "0xB7, 0xBB",
259        "EventName": "OCR.STREAMING_WR.L3_MISS",
260        "MSRIndex": "0x1a6,0x1a7",
261        "MSRValue": "0x3FFFC00800",
262        "Offcore": "1",
263        "PEBScounters": "0,1,2,3",
264        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
265        "SampleAfterValue": "100003",
266        "Speculative": "1",
267        "UMask": "0x1"
268    },
269    {
270        "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
271        "CollectPEBSRecord": "2",
272        "Counter": "0,1,2,3",
273        "EventCode": "0x54",
274        "EventName": "TX_MEM.ABORT_CAPACITY_READ",
275        "PEBScounters": "0,1,2,3",
276        "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
277        "SampleAfterValue": "100003",
278        "Speculative": "1",
279        "UMask": "0x80"
280    },
281    {
282        "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.",
283        "CollectPEBSRecord": "2",
284        "Counter": "0,1,2,3",
285        "EventCode": "0xB7, 0xBB",
286        "EventName": "OCR.OTHER.L3_MISS",
287        "MSRIndex": "0x1a6,0x1a7",
288        "MSRValue": "0x3FFFC08000",
289        "Offcore": "1",
290        "PEBScounters": "0,1,2,3",
291        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
292        "SampleAfterValue": "100003",
293        "Speculative": "1",
294        "UMask": "0x1"
295    },
296    {
297        "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.",
298        "CollectPEBSRecord": "2",
299        "Counter": "0,1,2,3",
300        "EventCode": "0xB7, 0xBB",
301        "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
302        "MSRIndex": "0x1a6,0x1a7",
303        "MSRValue": "0x3FFFC00020",
304        "Offcore": "1",
305        "PEBScounters": "0,1,2,3",
306        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
307        "SampleAfterValue": "100003",
308        "Speculative": "1",
309        "UMask": "0x1"
310    },
311    {
312        "BriefDescription": "Demand Data Read requests who miss L3 cache",
313        "CollectPEBSRecord": "2",
314        "Counter": "0,1,2,3",
315        "EventCode": "0xb0",
316        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
317        "PEBScounters": "0,1,2,3",
318        "PublicDescription": "Demand Data Read requests who miss L3 cache.",
319        "SampleAfterValue": "100003",
320        "Speculative": "1",
321        "UMask": "0x10"
322    },
323    {
324        "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
325        "CollectPEBSRecord": "2",
326        "Counter": "0,1,2,3",
327        "CounterMask": "2",
328        "EventCode": "0xA3",
329        "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
330        "PEBScounters": "0,1,2,3",
331        "SampleAfterValue": "1000003",
332        "Speculative": "1",
333        "UMask": "0x2"
334    },
335    {
336        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
337        "CollectPEBSRecord": "2",
338        "Counter": "0,1,2,3,4,5,6,7",
339        "EventCode": "0xc9",
340        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
341        "PEBScounters": "0,1,2,3,4,5,6,7",
342        "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
343        "SampleAfterValue": "100003",
344        "UMask": "0x20"
345    },
346    {
347        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
348        "CollectPEBSRecord": "2",
349        "Counter": "0,1,2,3,4,5,6,7",
350        "EventCode": "0xc9",
351        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
352        "PEBScounters": "0,1,2,3,4,5,6,7",
353        "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
354        "SampleAfterValue": "100003",
355        "UMask": "0x80"
356    },
357    {
358        "BriefDescription": "Number of times an HLE execution started.",
359        "CollectPEBSRecord": "2",
360        "Counter": "0,1,2,3,4,5,6,7",
361        "EventCode": "0xc8",
362        "EventName": "HLE_RETIRED.START",
363        "PEBScounters": "0,1,2,3,4,5,6,7",
364        "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.",
365        "SampleAfterValue": "100003",
366        "UMask": "0x1"
367    },
368    {
369        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
370        "CollectPEBSRecord": "2",
371        "Counter": "0,1,2,3,4,5,6,7",
372        "Data_LA": "1",
373        "EventCode": "0xcd",
374        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
375        "MSRIndex": "0x3F6",
376        "MSRValue": "0x4",
377        "PEBS": "2",
378        "PEBScounters": "0,1,2,3,4,5,6,7",
379        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
380        "SampleAfterValue": "100003",
381        "TakenAlone": "1",
382        "UMask": "0x1"
383    },
384    {
385        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
386        "CollectPEBSRecord": "2",
387        "Counter": "0,1,2,3,4,5,6,7",
388        "Data_LA": "1",
389        "EventCode": "0xcd",
390        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
391        "MSRIndex": "0x3F6",
392        "MSRValue": "0x80",
393        "PEBS": "2",
394        "PEBScounters": "0,1,2,3,4,5,6,7",
395        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
396        "SampleAfterValue": "1009",
397        "TakenAlone": "1",
398        "UMask": "0x1"
399    },
400    {
401        "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
402        "CollectPEBSRecord": "2",
403        "Counter": "0,1,2,3",
404        "EventCode": "0x54",
405        "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
406        "PEBScounters": "0,1,2,3",
407        "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.",
408        "SampleAfterValue": "100003",
409        "Speculative": "1",
410        "UMask": "0x40"
411    },
412    {
413        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
414        "CollectPEBSRecord": "2",
415        "Counter": "0,1,2,3,4,5,6,7",
416        "Data_LA": "1",
417        "EventCode": "0xcd",
418        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
419        "MSRIndex": "0x3F6",
420        "MSRValue": "0x8",
421        "PEBS": "2",
422        "PEBScounters": "0,1,2,3,4,5,6,7",
423        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
424        "SampleAfterValue": "50021",
425        "TakenAlone": "1",
426        "UMask": "0x1"
427    },
428    {
429        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
430        "CollectPEBSRecord": "2",
431        "Counter": "0,1,2,3,4,5,6,7",
432        "Data_LA": "1",
433        "EventCode": "0xcd",
434        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
435        "MSRIndex": "0x3F6",
436        "MSRValue": "0x100",
437        "PEBS": "2",
438        "PEBScounters": "0,1,2,3,4,5,6,7",
439        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
440        "SampleAfterValue": "503",
441        "TakenAlone": "1",
442        "UMask": "0x1"
443    },
444    {
445        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
446        "CollectPEBSRecord": "2",
447        "Counter": "0,1,2,3",
448        "CounterMask": "6",
449        "EventCode": "0xa3",
450        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
451        "PEBScounters": "0,1,2,3",
452        "SampleAfterValue": "1000003",
453        "Speculative": "1",
454        "UMask": "0x6"
455    },
456    {
457        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
458        "CollectPEBSRecord": "2",
459        "Counter": "0,1,2,3,4,5,6,7",
460        "Data_LA": "1",
461        "EventCode": "0xcd",
462        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
463        "MSRIndex": "0x3F6",
464        "MSRValue": "0x40",
465        "PEBS": "2",
466        "PEBScounters": "0,1,2,3,4,5,6,7",
467        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
468        "SampleAfterValue": "2003",
469        "TakenAlone": "1",
470        "UMask": "0x1"
471    },
472    {
473        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
474        "CollectPEBSRecord": "2",
475        "Counter": "0,1,2,3,4,5,6,7",
476        "Data_LA": "1",
477        "EventCode": "0xcd",
478        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
479        "MSRIndex": "0x3F6",
480        "MSRValue": "0x20",
481        "PEBS": "2",
482        "PEBScounters": "0,1,2,3,4,5,6,7",
483        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
484        "SampleAfterValue": "100007",
485        "TakenAlone": "1",
486        "UMask": "0x1"
487    },
488    {
489        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
490        "CollectPEBSRecord": "2",
491        "Counter": "0,1,2,3,4,5,6,7",
492        "EventCode": "0xc9",
493        "EventName": "RTM_RETIRED.ABORTED_MEM",
494        "PEBScounters": "0,1,2,3,4,5,6,7",
495        "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
496        "SampleAfterValue": "100003",
497        "UMask": "0x8"
498    },
499    {
500        "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.",
501        "CollectPEBSRecord": "2",
502        "Counter": "0,1,2,3",
503        "EventCode": "0xB7, 0xBB",
504        "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
505        "MSRIndex": "0x1a6,0x1a7",
506        "MSRValue": "0x3FFFC00400",
507        "Offcore": "1",
508        "PEBScounters": "0,1,2,3",
509        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
510        "SampleAfterValue": "100003",
511        "Speculative": "1",
512        "UMask": "0x1"
513    },
514    {
515        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.",
516        "CollectPEBSRecord": "2",
517        "Counter": "0,1,2,3",
518        "EventCode": "0xB7, 0xBB",
519        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
520        "MSRIndex": "0x1a6,0x1a7",
521        "MSRValue": "0x3FFFC00004",
522        "Offcore": "1",
523        "PEBScounters": "0,1,2,3",
524        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
525        "SampleAfterValue": "100003",
526        "Speculative": "1",
527        "UMask": "0x1"
528    },
529    {
530        "BriefDescription": "Number of times an RTM execution aborted.",
531        "CollectPEBSRecord": "2",
532        "Counter": "0,1,2,3,4,5,6,7",
533        "EventCode": "0xc9",
534        "EventName": "RTM_RETIRED.ABORTED",
535        "PEBScounters": "0,1,2,3,4,5,6,7",
536        "PublicDescription": "Counts the number of times RTM abort was triggered.",
537        "SampleAfterValue": "100003",
538        "UMask": "0x4"
539    },
540    {
541        "BriefDescription": "Number of times an RTM execution started.",
542        "CollectPEBSRecord": "2",
543        "Counter": "0,1,2,3,4,5,6,7",
544        "EventCode": "0xc9",
545        "EventName": "RTM_RETIRED.START",
546        "PEBScounters": "0,1,2,3,4,5,6,7",
547        "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
548        "SampleAfterValue": "100003",
549        "UMask": "0x1"
550    },
551    {
552        "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
553        "CollectPEBSRecord": "2",
554        "Counter": "0,1,2,3,4,5,6,7",
555        "EventCode": "0xc8",
556        "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
557        "PEBScounters": "0,1,2,3,4,5,6,7",
558        "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
559        "SampleAfterValue": "100003",
560        "UMask": "0x20"
561    },
562    {
563        "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
564        "CollectPEBSRecord": "2",
565        "Counter": "0,1,2,3",
566        "EventCode": "0x54",
567        "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
568        "PEBScounters": "0,1,2,3",
569        "PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
570        "SampleAfterValue": "100003",
571        "Speculative": "1",
572        "UMask": "0x4"
573    }
574]