1[
2    {
3        "BriefDescription": "ARITH.FPDIV_ACTIVE",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5,6,7",
6        "CounterMask": "1",
7        "EventCode": "0xb0",
8        "EventName": "ARITH.FPDIV_ACTIVE",
9        "PEBScounters": "0,1,2,3,4,5,6,7",
10        "SampleAfterValue": "1000003",
11        "UMask": "0x1"
12    },
13    {
14        "BriefDescription": "Counts all microcode FP assists.",
15        "CollectPEBSRecord": "2",
16        "Counter": "0,1,2,3,4,5,6,7",
17        "EventCode": "0xc1",
18        "EventName": "ASSISTS.FP",
19        "PEBScounters": "0,1,2,3,4,5,6,7",
20        "PublicDescription": "Counts all microcode Floating Point assists.",
21        "SampleAfterValue": "100003",
22        "UMask": "0x2"
23    },
24    {
25        "BriefDescription": "ASSISTS.SSE_AVX_MIX",
26        "CollectPEBSRecord": "2",
27        "Counter": "0,1,2,3,4,5,6,7",
28        "EventCode": "0xc1",
29        "EventName": "ASSISTS.SSE_AVX_MIX",
30        "PEBScounters": "0,1,2,3,4,5,6,7",
31        "SampleAfterValue": "1000003",
32        "UMask": "0x10"
33    },
34    {
35        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
36        "CollectPEBSRecord": "2",
37        "Counter": "0,1,2,3,4,5,6,7",
38        "EventCode": "0xb3",
39        "EventName": "FP_ARITH_DISPATCHED.PORT_0",
40        "PEBScounters": "0,1,2,3,4,5,6,7",
41        "SampleAfterValue": "2000003",
42        "UMask": "0x1"
43    },
44    {
45        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
46        "CollectPEBSRecord": "2",
47        "Counter": "0,1,2,3,4,5,6,7",
48        "EventCode": "0xb3",
49        "EventName": "FP_ARITH_DISPATCHED.PORT_1",
50        "PEBScounters": "0,1,2,3,4,5,6,7",
51        "SampleAfterValue": "2000003",
52        "UMask": "0x2"
53    },
54    {
55        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
56        "CollectPEBSRecord": "2",
57        "Counter": "0,1,2,3,4,5,6,7",
58        "EventCode": "0xb3",
59        "EventName": "FP_ARITH_DISPATCHED.PORT_5",
60        "PEBScounters": "0,1,2,3,4,5,6,7",
61        "SampleAfterValue": "2000003",
62        "UMask": "0x4"
63    },
64    {
65        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
66        "CollectPEBSRecord": "2",
67        "Counter": "0,1,2,3,4,5,6,7",
68        "EventCode": "0xc7",
69        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
70        "PEBScounters": "0,1,2,3,4,5,6,7",
71        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
72        "SampleAfterValue": "100003",
73        "UMask": "0x4"
74    },
75    {
76        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
77        "CollectPEBSRecord": "2",
78        "Counter": "0,1,2,3,4,5,6,7",
79        "EventCode": "0xc7",
80        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
81        "PEBScounters": "0,1,2,3,4,5,6,7",
82        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
83        "SampleAfterValue": "100003",
84        "UMask": "0x8"
85    },
86    {
87        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
88        "CollectPEBSRecord": "2",
89        "Counter": "0,1,2,3,4,5,6,7",
90        "EventCode": "0xc7",
91        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
92        "PEBScounters": "0,1,2,3,4,5,6,7",
93        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
94        "SampleAfterValue": "100003",
95        "UMask": "0x10"
96    },
97    {
98        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
99        "CollectPEBSRecord": "2",
100        "Counter": "0,1,2,3,4,5,6,7",
101        "EventCode": "0xc7",
102        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
103        "PEBScounters": "0,1,2,3,4,5,6,7",
104        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
105        "SampleAfterValue": "100003",
106        "UMask": "0x20"
107    },
108    {
109        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
110        "CollectPEBSRecord": "2",
111        "Counter": "0,1,2,3,4,5,6,7",
112        "EventCode": "0xc7",
113        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
114        "PEBScounters": "0,1,2,3,4,5,6,7",
115        "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
116        "SampleAfterValue": "100003",
117        "UMask": "0x40"
118    },
119    {
120        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
121        "CollectPEBSRecord": "2",
122        "Counter": "0,1,2,3,4,5,6,7",
123        "EventCode": "0xc7",
124        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
125        "PEBScounters": "0,1,2,3,4,5,6,7",
126        "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
127        "SampleAfterValue": "100003",
128        "UMask": "0x80"
129    },
130    {
131        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
132        "CollectPEBSRecord": "2",
133        "Counter": "0,1,2,3,4,5,6,7",
134        "EventCode": "0xc7",
135        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
136        "PEBScounters": "0,1,2,3,4,5,6,7",
137        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
138        "SampleAfterValue": "100003",
139        "UMask": "0x1"
140    },
141    {
142        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
143        "CollectPEBSRecord": "2",
144        "Counter": "0,1,2,3,4,5,6,7",
145        "EventCode": "0xc7",
146        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
147        "PEBScounters": "0,1,2,3,4,5,6,7",
148        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
149        "SampleAfterValue": "100003",
150        "UMask": "0x2"
151    },
152    {
153        "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
154        "Counter": "0,1,2,3,4,5,6,7",
155        "EventCode": "0xcf",
156        "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
157        "PEBScounters": "0,1,2,3,4,5,6,7",
158        "SampleAfterValue": "100003",
159        "UMask": "0x4"
160    },
161    {
162        "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
163        "Counter": "0,1,2,3,4,5,6,7",
164        "EventCode": "0xcf",
165        "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
166        "PEBScounters": "0,1,2,3,4,5,6,7",
167        "SampleAfterValue": "100003",
168        "UMask": "0x8"
169    },
170    {
171        "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
172        "CollectPEBSRecord": "2",
173        "Counter": "0,1,2,3,4,5,6,7",
174        "EventCode": "0xcf",
175        "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
176        "PEBScounters": "0,1,2,3,4,5,6,7",
177        "SampleAfterValue": "100003",
178        "UMask": "0x10"
179    },
180    {
181        "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
182        "Counter": "0,1,2,3,4,5,6,7",
183        "EventCode": "0xcf",
184        "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
185        "PEBScounters": "0,1,2,3,4,5,6,7",
186        "SampleAfterValue": "100003",
187        "UMask": "0x2"
188    },
189    {
190        "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.",
191        "Counter": "0,1,2,3,4,5,6,7",
192        "EventCode": "0xcf",
193        "EventName": "FP_ARITH_INST_RETIRED2.SCALAR",
194        "PEBScounters": "0,1,2,3,4,5,6,7",
195        "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR",
196        "SampleAfterValue": "100003",
197        "UMask": "0x3"
198    },
199    {
200        "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
201        "Counter": "0,1,2,3,4,5,6,7",
202        "EventCode": "0xcf",
203        "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
204        "PEBScounters": "0,1,2,3,4,5,6,7",
205        "SampleAfterValue": "100003",
206        "UMask": "0x1"
207    },
208    {
209        "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.",
210        "Counter": "0,1,2,3,4,5,6,7",
211        "EventCode": "0xcf",
212        "EventName": "FP_ARITH_INST_RETIRED2.VECTOR",
213        "PEBScounters": "0,1,2,3,4,5,6,7",
214        "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR",
215        "SampleAfterValue": "100003",
216        "UMask": "0x1c"
217    }
218]
219