1[
2    {
3        "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
4        "EventCode": "0x08",
5        "Counter": "0,1,2,3",
6        "UMask": "0x1",
7        "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
8        "SampleAfterValue": "100003",
9        "BriefDescription": "Load misses in all DTLB levels that cause page walks",
10        "CounterHTOff": "0,1,2,3,4,5,6,7"
11    },
12    {
13        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
14        "EventCode": "0x08",
15        "Counter": "0,1,2,3",
16        "UMask": "0x2",
17        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
18        "SampleAfterValue": "2000003",
19        "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
20        "CounterHTOff": "0,1,2,3,4,5,6,7"
21    },
22    {
23        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
24        "EventCode": "0x08",
25        "Counter": "0,1,2,3",
26        "UMask": "0x4",
27        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
28        "SampleAfterValue": "2000003",
29        "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
30        "CounterHTOff": "0,1,2,3,4,5,6,7"
31    },
32    {
33        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
34        "EventCode": "0x08",
35        "Counter": "0,1,2,3",
36        "UMask": "0x8",
37        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
38        "SampleAfterValue": "2000003",
39        "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
40        "CounterHTOff": "0,1,2,3,4,5,6,7"
41    },
42    {
43        "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
44        "EventCode": "0x08",
45        "Counter": "0,1,2,3",
46        "UMask": "0xe",
47        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
48        "SampleAfterValue": "100003",
49        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
50        "CounterHTOff": "0,1,2,3,4,5,6,7"
51    },
52    {
53        "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
54        "EventCode": "0x08",
55        "Counter": "0,1,2,3",
56        "UMask": "0x10",
57        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
58        "SampleAfterValue": "2000003",
59        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
60        "CounterHTOff": "0,1,2,3,4,5,6,7"
61    },
62    {
63        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
64        "EventCode": "0x08",
65        "Counter": "0,1,2,3",
66        "UMask": "0x10",
67        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
68        "SampleAfterValue": "100003",
69        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
70        "CounterMask": "1",
71        "CounterHTOff": "0,1,2,3,4,5,6,7"
72    },
73    {
74        "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
75        "EventCode": "0x08",
76        "Counter": "0,1,2,3",
77        "UMask": "0x20",
78        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
79        "SampleAfterValue": "2000003",
80        "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
81        "CounterHTOff": "0,1,2,3,4,5,6,7"
82    },
83    {
84        "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
85        "EventCode": "0x49",
86        "Counter": "0,1,2,3",
87        "UMask": "0x1",
88        "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
89        "SampleAfterValue": "100003",
90        "BriefDescription": "Store misses in all DTLB levels that cause page walks",
91        "CounterHTOff": "0,1,2,3,4,5,6,7"
92    },
93    {
94        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
95        "EventCode": "0x49",
96        "Counter": "0,1,2,3",
97        "UMask": "0x2",
98        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
99        "SampleAfterValue": "100003",
100        "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
101        "CounterHTOff": "0,1,2,3,4,5,6,7"
102    },
103    {
104        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
105        "EventCode": "0x49",
106        "Counter": "0,1,2,3",
107        "UMask": "0x4",
108        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
109        "SampleAfterValue": "100003",
110        "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
111        "CounterHTOff": "0,1,2,3,4,5,6,7"
112    },
113    {
114        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages.  The page walks can end with or without a page fault.",
115        "EventCode": "0x49",
116        "Counter": "0,1,2,3",
117        "UMask": "0x8",
118        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
119        "SampleAfterValue": "100003",
120        "BriefDescription": "Page walk completed due to a demand data store to a 1G page",
121        "CounterHTOff": "0,1,2,3,4,5,6,7"
122    },
123    {
124        "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
125        "EventCode": "0x49",
126        "Counter": "0,1,2,3",
127        "UMask": "0xe",
128        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
129        "SampleAfterValue": "100003",
130        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
131        "CounterHTOff": "0,1,2,3,4,5,6,7"
132    },
133    {
134        "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
135        "EventCode": "0x49",
136        "Counter": "0,1,2,3",
137        "UMask": "0x10",
138        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
139        "SampleAfterValue": "2000003",
140        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
141        "CounterHTOff": "0,1,2,3,4,5,6,7"
142    },
143    {
144        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
145        "EventCode": "0x49",
146        "Counter": "0,1,2,3",
147        "UMask": "0x10",
148        "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
149        "SampleAfterValue": "100003",
150        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
151        "CounterMask": "1",
152        "CounterHTOff": "0,1,2,3,4,5,6,7"
153    },
154    {
155        "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
156        "EventCode": "0x49",
157        "Counter": "0,1,2,3",
158        "UMask": "0x20",
159        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
160        "SampleAfterValue": "100003",
161        "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
162        "CounterHTOff": "0,1,2,3,4,5,6,7"
163    },
164    {
165        "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
166        "EventCode": "0x4F",
167        "Counter": "0,1,2,3",
168        "UMask": "0x10",
169        "EventName": "EPT.WALK_PENDING",
170        "SampleAfterValue": "2000003",
171        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
172        "CounterHTOff": "0,1,2,3,4,5,6,7"
173    },
174    {
175        "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
176        "EventCode": "0x85",
177        "Counter": "0,1,2,3",
178        "UMask": "0x1",
179        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
180        "SampleAfterValue": "100003",
181        "BriefDescription": "Misses at all ITLB levels that cause page walks",
182        "CounterHTOff": "0,1,2,3,4,5,6,7"
183    },
184    {
185        "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
186        "EventCode": "0x85",
187        "Counter": "0,1,2,3",
188        "UMask": "0x2",
189        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
190        "SampleAfterValue": "100003",
191        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
192        "CounterHTOff": "0,1,2,3,4,5,6,7"
193    },
194    {
195        "PublicDescription": "Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
196        "EventCode": "0x85",
197        "Counter": "0,1,2,3",
198        "UMask": "0x4",
199        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
200        "SampleAfterValue": "100003",
201        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
202        "CounterHTOff": "0,1,2,3,4,5,6,7"
203    },
204    {
205        "PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
206        "EventCode": "0x85",
207        "Counter": "0,1,2,3",
208        "UMask": "0x8",
209        "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
210        "SampleAfterValue": "100003",
211        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
212        "CounterHTOff": "0,1,2,3,4,5,6,7"
213    },
214    {
215        "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
216        "EventCode": "0x85",
217        "Counter": "0,1,2,3",
218        "UMask": "0xe",
219        "EventName": "ITLB_MISSES.WALK_COMPLETED",
220        "SampleAfterValue": "100003",
221        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
222        "CounterHTOff": "0,1,2,3,4,5,6,7"
223    },
224    {
225        "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
226        "EventCode": "0x85",
227        "Counter": "0,1,2,3",
228        "UMask": "0x10",
229        "EventName": "ITLB_MISSES.WALK_PENDING",
230        "SampleAfterValue": "100003",
231        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
232        "CounterHTOff": "0,1,2,3,4,5,6,7"
233    },
234    {
235        "PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.",
236        "EventCode": "0x85",
237        "Counter": "0,1,2,3",
238        "UMask": "0x10",
239        "EventName": "ITLB_MISSES.WALK_ACTIVE",
240        "SampleAfterValue": "100003",
241        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
242        "CounterMask": "1",
243        "CounterHTOff": "0,1,2,3,4,5,6,7"
244    },
245    {
246        "EventCode": "0x85",
247        "Counter": "0,1,2,3",
248        "UMask": "0x20",
249        "EventName": "ITLB_MISSES.STLB_HIT",
250        "SampleAfterValue": "100003",
251        "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
252        "CounterHTOff": "0,1,2,3,4,5,6,7"
253    },
254    {
255        "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
256        "EventCode": "0xAE",
257        "Counter": "0,1,2,3",
258        "UMask": "0x1",
259        "EventName": "ITLB.ITLB_FLUSH",
260        "SampleAfterValue": "100007",
261        "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
262        "CounterHTOff": "0,1,2,3,4,5,6,7"
263    },
264    {
265        "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
266        "EventCode": "0xBD",
267        "Counter": "0,1,2,3",
268        "UMask": "0x1",
269        "EventName": "TLB_FLUSH.DTLB_THREAD",
270        "SampleAfterValue": "100007",
271        "BriefDescription": "DTLB flush attempts of the thread-specific entries",
272        "CounterHTOff": "0,1,2,3,4,5,6,7"
273    },
274    {
275        "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
276        "EventCode": "0xBD",
277        "Counter": "0,1,2,3",
278        "UMask": "0x20",
279        "EventName": "TLB_FLUSH.STLB_ANY",
280        "SampleAfterValue": "100007",
281        "BriefDescription": "STLB flush attempts",
282        "CounterHTOff": "0,1,2,3,4,5,6,7"
283    }
284]