1cda07865SPeter Wemm /*- 2c49761ddSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3c49761ddSPedro F. Giffuni * 44536af6aSKATO Takenori * Copyright (c) KATO Takenori, 1997, 1998. 5a8e282d6SKATO Takenori * 6a8e282d6SKATO Takenori * All rights reserved. Unpublished rights reserved under the copyright 7a8e282d6SKATO Takenori * laws of Japan. 8a8e282d6SKATO Takenori * 9a8e282d6SKATO Takenori * Redistribution and use in source and binary forms, with or without 10a8e282d6SKATO Takenori * modification, are permitted provided that the following conditions 11a8e282d6SKATO Takenori * are met: 12a8e282d6SKATO Takenori * 13a8e282d6SKATO Takenori * 1. Redistributions of source code must retain the above copyright 14a8e282d6SKATO Takenori * notice, this list of conditions and the following disclaimer as 15a8e282d6SKATO Takenori * the first lines of this file unmodified. 16a8e282d6SKATO Takenori * 2. Redistributions in binary form must reproduce the above copyright 17a8e282d6SKATO Takenori * notice, this list of conditions and the following disclaimer in the 18a8e282d6SKATO Takenori * documentation and/or other materials provided with the distribution. 19a8e282d6SKATO Takenori * 20a8e282d6SKATO Takenori * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21a8e282d6SKATO Takenori * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22a8e282d6SKATO Takenori * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23a8e282d6SKATO Takenori * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24a8e282d6SKATO Takenori * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25a8e282d6SKATO Takenori * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26a8e282d6SKATO Takenori * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27a8e282d6SKATO Takenori * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28a8e282d6SKATO Takenori * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29a8e282d6SKATO Takenori * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30a8e282d6SKATO Takenori */ 31a8e282d6SKATO Takenori 3256ae44c5SDavid E. O'Brien #include <sys/cdefs.h> 3356ae44c5SDavid E. O'Brien __FBSDID("$FreeBSD$"); 3456ae44c5SDavid E. O'Brien 35a8e282d6SKATO Takenori #include "opt_cpu.h" 36a8e282d6SKATO Takenori 37a8e282d6SKATO Takenori #include <sys/param.h> 38a8e282d6SKATO Takenori #include <sys/kernel.h> 39cd9e9d1bSKonstantin Belousov #include <sys/pcpu.h> 40a8e282d6SKATO Takenori #include <sys/systm.h> 419d146ac5SPeter Wemm #include <sys/sysctl.h> 42a8e282d6SKATO Takenori 43a8e282d6SKATO Takenori #include <machine/cputypes.h> 44a8e282d6SKATO Takenori #include <machine/md_var.h> 45a8e282d6SKATO Takenori #include <machine/specialreg.h> 46a8e282d6SKATO Takenori 47430e272cSPeter Wemm #include <vm/vm.h> 48430e272cSPeter Wemm #include <vm/pmap.h> 4920916c1fSKATO Takenori 5010deca7eSJohn Baldwin static int hw_instruction_sse; 519d146ac5SPeter Wemm SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 5210deca7eSJohn Baldwin &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 53cd155b56SDon Lewis static int lower_sharedpage_init; 54cd155b56SDon Lewis int hw_lower_amd64_sharedpage; 55cd155b56SDon Lewis SYSCTL_INT(_hw, OID_AUTO, lower_amd64_sharedpage, CTLFLAG_RDTUN, 56cd155b56SDon Lewis &hw_lower_amd64_sharedpage, 0, 57cd155b56SDon Lewis "Lower sharedpage to work around Ryzen issue with executing code near the top of user memory"); 586f5c96c4SJun Kuriyama /* 596f5c96c4SJun Kuriyama * -1: automatic (default) 606f5c96c4SJun Kuriyama * 0: keep enable CLFLUSH 616f5c96c4SJun Kuriyama * 1: force disable CLFLUSH 626f5c96c4SJun Kuriyama */ 636f5c96c4SJun Kuriyama static int hw_clflush_disable = -1; 649d146ac5SPeter Wemm 653ce5dbccSJung-uk Kim static void 663ce5dbccSJung-uk Kim init_amd(void) 673ce5dbccSJung-uk Kim { 68f9ac50acSAndriy Gapon uint64_t msr; 693ce5dbccSJung-uk Kim 703ce5dbccSJung-uk Kim /* 713ce5dbccSJung-uk Kim * Work around Erratum 721 for Family 10h and 12h processors. 723ce5dbccSJung-uk Kim * These processors may incorrectly update the stack pointer 733ce5dbccSJung-uk Kim * after a long series of push and/or near-call instructions, 743ce5dbccSJung-uk Kim * or a long series of pop and/or near-return instructions. 753ce5dbccSJung-uk Kim * 763ce5dbccSJung-uk Kim * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf 773ce5dbccSJung-uk Kim * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf 7865211d02SKonstantin Belousov * 7965211d02SKonstantin Belousov * Hypervisors do not provide access to the errata MSR, 8065211d02SKonstantin Belousov * causing #GP exception on attempt to apply the errata. The 8165211d02SKonstantin Belousov * MSR write shall be done on host and persist globally 8265211d02SKonstantin Belousov * anyway, so do not try to do it when under virtualization. 833ce5dbccSJung-uk Kim */ 843ce5dbccSJung-uk Kim switch (CPUID_TO_FAMILY(cpu_id)) { 853ce5dbccSJung-uk Kim case 0x10: 863ce5dbccSJung-uk Kim case 0x12: 8765211d02SKonstantin Belousov if ((cpu_feature2 & CPUID2_HV) == 0) 883ce5dbccSJung-uk Kim wrmsr(0xc0011029, rdmsr(0xc0011029) | 1); 893ce5dbccSJung-uk Kim break; 903ce5dbccSJung-uk Kim } 91e5e44520SAndriy Gapon 92e5e44520SAndriy Gapon /* 93e5e44520SAndriy Gapon * BIOS may fail to set InitApicIdCpuIdLo to 1 as it should per BKDG. 94e5e44520SAndriy Gapon * So, do it here or otherwise some tools could be confused by 95e5e44520SAndriy Gapon * Initial Local APIC ID reported with CPUID Function 1 in EBX. 96e5e44520SAndriy Gapon */ 97e5e44520SAndriy Gapon if (CPUID_TO_FAMILY(cpu_id) == 0x10) { 98e5e44520SAndriy Gapon if ((cpu_feature2 & CPUID2_HV) == 0) { 99e5e44520SAndriy Gapon msr = rdmsr(MSR_NB_CFG1); 100e5e44520SAndriy Gapon msr |= (uint64_t)1 << 54; 101e5e44520SAndriy Gapon wrmsr(MSR_NB_CFG1, msr); 102e5e44520SAndriy Gapon } 103e5e44520SAndriy Gapon } 104a2d87b79SAndriy Gapon 105a2d87b79SAndriy Gapon /* 106a2d87b79SAndriy Gapon * BIOS may configure Family 10h processors to convert WC+ cache type 107a2d87b79SAndriy Gapon * to CD. That can hurt performance of guest VMs using nested paging. 108a2d87b79SAndriy Gapon * The relevant MSR bit is not documented in the BKDG, 109a2d87b79SAndriy Gapon * the fix is borrowed from Linux. 110a2d87b79SAndriy Gapon */ 111a2d87b79SAndriy Gapon if (CPUID_TO_FAMILY(cpu_id) == 0x10) { 112a2d87b79SAndriy Gapon if ((cpu_feature2 & CPUID2_HV) == 0) { 113a2d87b79SAndriy Gapon msr = rdmsr(0xc001102a); 114a2d87b79SAndriy Gapon msr &= ~((uint64_t)1 << 24); 115a2d87b79SAndriy Gapon wrmsr(0xc001102a, msr); 116a2d87b79SAndriy Gapon } 117a2d87b79SAndriy Gapon } 118f1382605SAndriy Gapon 119f1382605SAndriy Gapon /* 120f1382605SAndriy Gapon * Work around Erratum 793: Specific Combination of Writes to Write 121f1382605SAndriy Gapon * Combined Memory Types and Locked Instructions May Cause Core Hang. 122f1382605SAndriy Gapon * See Revision Guide for AMD Family 16h Models 00h-0Fh Processors, 123f1382605SAndriy Gapon * revision 3.04 or later, publication 51810. 124f1382605SAndriy Gapon */ 125f1382605SAndriy Gapon if (CPUID_TO_FAMILY(cpu_id) == 0x16 && CPUID_TO_MODEL(cpu_id) <= 0xf) { 126f1382605SAndriy Gapon if ((cpu_feature2 & CPUID2_HV) == 0) { 127bebcdc00SJohn Baldwin msr = rdmsr(MSR_LS_CFG); 128f1382605SAndriy Gapon msr |= (uint64_t)1 << 15; 129bebcdc00SJohn Baldwin wrmsr(MSR_LS_CFG, msr); 130f1382605SAndriy Gapon } 131f1382605SAndriy Gapon } 132cd155b56SDon Lewis 13345ed991dSKonstantin Belousov /* Ryzen erratas. */ 13445ed991dSKonstantin Belousov if (CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1 && 13545ed991dSKonstantin Belousov (cpu_feature2 & CPUID2_HV) == 0) { 13645ed991dSKonstantin Belousov /* 1021 */ 13745ed991dSKonstantin Belousov msr = rdmsr(0xc0011029); 13845ed991dSKonstantin Belousov msr |= 0x2000; 13945ed991dSKonstantin Belousov wrmsr(0xc0011029, msr); 14045ed991dSKonstantin Belousov 14145ed991dSKonstantin Belousov /* 1033 */ 142bebcdc00SJohn Baldwin msr = rdmsr(MSR_LS_CFG); 14345ed991dSKonstantin Belousov msr |= 0x10; 144bebcdc00SJohn Baldwin wrmsr(MSR_LS_CFG, msr); 14545ed991dSKonstantin Belousov 14645ed991dSKonstantin Belousov /* 1049 */ 14745ed991dSKonstantin Belousov msr = rdmsr(0xc0011028); 14845ed991dSKonstantin Belousov msr |= 0x10; 14945ed991dSKonstantin Belousov wrmsr(0xc0011028, msr); 15045ed991dSKonstantin Belousov 15145ed991dSKonstantin Belousov /* 1095 */ 152bebcdc00SJohn Baldwin msr = rdmsr(MSR_LS_CFG); 15345ed991dSKonstantin Belousov msr |= 0x200000000000000; 154bebcdc00SJohn Baldwin wrmsr(MSR_LS_CFG, msr); 15545ed991dSKonstantin Belousov } 15645ed991dSKonstantin Belousov 157cd155b56SDon Lewis /* 158cd155b56SDon Lewis * Work around a problem on Ryzen that is triggered by executing 159cd155b56SDon Lewis * code near the top of user memory, in our case the signal 160cd155b56SDon Lewis * trampoline code in the shared page on amd64. 161cd155b56SDon Lewis * 162cd155b56SDon Lewis * This function is executed once for the BSP before tunables take 163cd155b56SDon Lewis * effect so the value determined here can be overridden by the 164cd155b56SDon Lewis * tunable. This function is then executed again for each AP and 165cd155b56SDon Lewis * also on resume. Set a flag the first time so that value set by 166cd155b56SDon Lewis * the tunable is not overwritten. 167cd155b56SDon Lewis * 168cd155b56SDon Lewis * The stepping and/or microcode versions should be checked after 169cd155b56SDon Lewis * this issue is fixed by AMD so that we don't use this mode if not 170cd155b56SDon Lewis * needed. 171cd155b56SDon Lewis */ 172cd155b56SDon Lewis if (lower_sharedpage_init == 0) { 173cd155b56SDon Lewis lower_sharedpage_init = 1; 1742ee49facSKonstantin Belousov if (CPUID_TO_FAMILY(cpu_id) == 0x17 || 1752ee49facSKonstantin Belousov CPUID_TO_FAMILY(cpu_id) == 0x18) { 176cd155b56SDon Lewis hw_lower_amd64_sharedpage = 1; 177cd155b56SDon Lewis } 178cd155b56SDon Lewis } 1793ce5dbccSJung-uk Kim } 1803ce5dbccSJung-uk Kim 18192df0bdaSJung-uk Kim /* 182cd45fec0SJung-uk Kim * Initialize special VIA features 18392df0bdaSJung-uk Kim */ 18492df0bdaSJung-uk Kim static void 18592df0bdaSJung-uk Kim init_via(void) 18692df0bdaSJung-uk Kim { 18792df0bdaSJung-uk Kim u_int regs[4], val; 18892df0bdaSJung-uk Kim 189cd45fec0SJung-uk Kim /* 190cd45fec0SJung-uk Kim * Check extended CPUID for PadLock features. 191cd45fec0SJung-uk Kim * 192cd45fec0SJung-uk Kim * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf 193cd45fec0SJung-uk Kim */ 19492df0bdaSJung-uk Kim do_cpuid(0xc0000000, regs); 195cd45fec0SJung-uk Kim if (regs[0] >= 0xc0000001) { 19692df0bdaSJung-uk Kim do_cpuid(0xc0000001, regs); 19792df0bdaSJung-uk Kim val = regs[3]; 19892df0bdaSJung-uk Kim } else 199cd45fec0SJung-uk Kim return; 20092df0bdaSJung-uk Kim 201cd45fec0SJung-uk Kim /* Enable RNG if present. */ 202cd45fec0SJung-uk Kim if ((val & VIA_CPUID_HAS_RNG) != 0) { 20392df0bdaSJung-uk Kim via_feature_rng = VIA_HAS_RNG; 204cd45fec0SJung-uk Kim wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); 20592df0bdaSJung-uk Kim } 206cd45fec0SJung-uk Kim 207cd45fec0SJung-uk Kim /* Enable PadLock if present. */ 208cd45fec0SJung-uk Kim if ((val & VIA_CPUID_HAS_ACE) != 0) 20992df0bdaSJung-uk Kim via_feature_xcrypt |= VIA_HAS_AES; 210cd45fec0SJung-uk Kim if ((val & VIA_CPUID_HAS_ACE2) != 0) 21192df0bdaSJung-uk Kim via_feature_xcrypt |= VIA_HAS_AESCTR; 212cd45fec0SJung-uk Kim if ((val & VIA_CPUID_HAS_PHE) != 0) 21392df0bdaSJung-uk Kim via_feature_xcrypt |= VIA_HAS_SHA; 214cd45fec0SJung-uk Kim if ((val & VIA_CPUID_HAS_PMM) != 0) 21592df0bdaSJung-uk Kim via_feature_xcrypt |= VIA_HAS_MM; 216cd45fec0SJung-uk Kim if (via_feature_xcrypt != 0) 217cd45fec0SJung-uk Kim wrmsr(0x1107, rdmsr(0x1107) | (1 << 28)); 21892df0bdaSJung-uk Kim } 21992df0bdaSJung-uk Kim 2209d146ac5SPeter Wemm /* 221430e272cSPeter Wemm * Initialize CPU control registers 2229d146ac5SPeter Wemm */ 2239d146ac5SPeter Wemm void 224430e272cSPeter Wemm initializecpu(void) 2259d146ac5SPeter Wemm { 226430e272cSPeter Wemm uint64_t msr; 227cd9e9d1bSKonstantin Belousov uint32_t cr4; 228430e272cSPeter Wemm 229cd9e9d1bSKonstantin Belousov cr4 = rcr4(); 2309d146ac5SPeter Wemm if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 231cd9e9d1bSKonstantin Belousov cr4 |= CR4_FXSR | CR4_XMM; 2329d146ac5SPeter Wemm cpu_fxsr = hw_instruction_sse = 1; 2339d146ac5SPeter Wemm } 234cd9e9d1bSKonstantin Belousov if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE) 235cd9e9d1bSKonstantin Belousov cr4 |= CR4_FSGSBASE; 236cd9e9d1bSKonstantin Belousov 237e7a9df16SKonstantin Belousov if (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) 238e7a9df16SKonstantin Belousov cr4 |= CR4_PKE; 239e7a9df16SKonstantin Belousov 240cd9e9d1bSKonstantin Belousov /* 241cd9e9d1bSKonstantin Belousov * Postpone enabling the SMEP on the boot CPU until the page 242cd9e9d1bSKonstantin Belousov * tables are switched from the boot loader identity mapping 243cd9e9d1bSKonstantin Belousov * to the kernel tables. The boot loader enables the U bit in 244cd9e9d1bSKonstantin Belousov * its tables. 245cd9e9d1bSKonstantin Belousov */ 246b3a7db3bSKonstantin Belousov if (!IS_BSP()) { 247b3a7db3bSKonstantin Belousov if (cpu_stdext_feature & CPUID_STDEXT_SMEP) 248cd9e9d1bSKonstantin Belousov cr4 |= CR4_SMEP; 249b3a7db3bSKonstantin Belousov if (cpu_stdext_feature & CPUID_STDEXT_SMAP) 250b3a7db3bSKonstantin Belousov cr4 |= CR4_SMAP; 251b3a7db3bSKonstantin Belousov } 252cd9e9d1bSKonstantin Belousov load_cr4(cr4); 253beb24065SJonathan T. Looney if (IS_BSP() && (amd_feature & AMDID_NX) != 0) { 254430e272cSPeter Wemm msr = rdmsr(MSR_EFER) | EFER_NXE; 255430e272cSPeter Wemm wrmsr(MSR_EFER, msr); 256430e272cSPeter Wemm pg_nx = PG_NX; 2579d146ac5SPeter Wemm } 258a324b7f7SKonstantin Belousov hw_ibrs_recalculate(false); 2593621ba1eSKonstantin Belousov hw_ssb_recalculate(false); 2602dec2b4aSKonstantin Belousov amd64_syscall_ret_flush_l1d_recalc(); 2613ce5dbccSJung-uk Kim switch (cpu_vendor_id) { 2623ce5dbccSJung-uk Kim case CPU_VENDOR_AMD: 2632ee49facSKonstantin Belousov case CPU_VENDOR_HYGON: 2643ce5dbccSJung-uk Kim init_amd(); 2653ce5dbccSJung-uk Kim break; 2663ce5dbccSJung-uk Kim case CPU_VENDOR_CENTAUR: 26792df0bdaSJung-uk Kim init_via(); 2683ce5dbccSJung-uk Kim break; 2693ce5dbccSJung-uk Kim } 27039d70f6bSKonstantin Belousov 27139d70f6bSKonstantin Belousov if ((amd_feature & AMDID_RDTSCP) != 0 || 27239d70f6bSKonstantin Belousov (cpu_stdext_feature2 & CPUID_STDEXT2_RDPID) != 0) 27339d70f6bSKonstantin Belousov wrmsr(MSR_TSC_AUX, PCPU_GET(cpuid)); 274ec24e8d4SKonstantin Belousov } 275ec24e8d4SKonstantin Belousov 276ec24e8d4SKonstantin Belousov void 277cd234300SBrooks Davis initializecpucache(void) 278ec24e8d4SKonstantin Belousov { 279206a3368SKonstantin Belousov 280206a3368SKonstantin Belousov /* 281206a3368SKonstantin Belousov * CPUID with %eax = 1, %ebx returns 282206a3368SKonstantin Belousov * Bits 15-8: CLFLUSH line size 283206a3368SKonstantin Belousov * (Value * 8 = cache line size in bytes) 284206a3368SKonstantin Belousov */ 285206a3368SKonstantin Belousov if ((cpu_feature & CPUID_CLFSH) != 0) 286206a3368SKonstantin Belousov cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 287b02395c6SKonstantin Belousov /* 2887134e390SJohn Baldwin * XXXKIB: (temporary) hack to work around traps generated 2897134e390SJohn Baldwin * when CLFLUSHing APIC register window under virtualization 2907134e390SJohn Baldwin * environments. These environments tend to disable the 2917134e390SJohn Baldwin * CPUID_SS feature even though the native CPU supports it. 292b02395c6SKonstantin Belousov */ 2936f5c96c4SJun Kuriyama TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 294af95bbf5SKonstantin Belousov if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) { 295b02395c6SKonstantin Belousov cpu_feature &= ~CPUID_CLFSH; 296af95bbf5SKonstantin Belousov cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 297af95bbf5SKonstantin Belousov } 298af95bbf5SKonstantin Belousov 2996f5c96c4SJun Kuriyama /* 300af95bbf5SKonstantin Belousov * The kernel's use of CLFLUSH{,OPT} can be disabled manually 301af95bbf5SKonstantin Belousov * by setting the hw.clflush_disable tunable. 3026f5c96c4SJun Kuriyama */ 303af95bbf5SKonstantin Belousov if (hw_clflush_disable == 1) { 3046f5c96c4SJun Kuriyama cpu_feature &= ~CPUID_CLFSH; 305af95bbf5SKonstantin Belousov cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT; 306af95bbf5SKonstantin Belousov } 3076f5c96c4SJun Kuriyama } 308