1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 #include <sys/resource.h> 43 #include <machine/bus.h> 44 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/extres/clk/clk.h> 49 #include <dev/extres/hwreset/hwreset.h> 50 51 #include "syscon_if.h" 52 53 #include "opt_snd.h" 54 #include <dev/sound/pcm/sound.h> 55 #include <dev/sound/fdt/audio_dai.h> 56 #include "audio_dai_if.h" 57 58 #define FIFO_LEVEL 0x40 59 60 #define DA_CTL 0x00 61 #define DA_CTL_BCLK_OUT (1 << 18) /* sun8i */ 62 #define DA_CLK_LRCK_OUT (1 << 17) /* sun8i */ 63 #define DA_CTL_SDO_EN (1 << 8) 64 #define DA_CTL_MS (1 << 5) /* sun4i */ 65 #define DA_CTL_PCM (1 << 4) /* sun4i */ 66 #define DA_CTL_MODE_SEL_MASK (3 << 4) /* sun8i */ 67 #define DA_CTL_MODE_SEL_PCM (0 << 4) /* sun8i */ 68 #define DA_CTL_MODE_SEL_LJ (1 << 4) /* sun8i */ 69 #define DA_CTL_MODE_SEL_RJ (2 << 4) /* sun8i */ 70 #define DA_CTL_TXEN (1 << 2) 71 #define DA_CTL_RXEN (1 << 1) 72 #define DA_CTL_GEN (1 << 0) 73 #define DA_FAT0 0x04 74 #define DA_FAT0_LRCK_PERIOD_MASK (0x3ff << 8) /* sun8i */ 75 #define DA_FAT0_LRCK_PERIOD(n) (((n) & 0x3fff) << 8) /* sun8i */ 76 #define DA_FAT0_LRCP_MASK (1 << 7) 77 #define DA_LRCP_NORMAL (0 << 7) 78 #define DA_LRCP_INVERTED (1 << 7) 79 #define DA_FAT0_BCP_MASK (1 << 6) 80 #define DA_BCP_NORMAL (0 << 6) 81 #define DA_BCP_INVERTED (1 << 6) 82 #define DA_FAT0_SR __BITS(5,4) 83 #define DA_FAT0_WSS __BITS(3,2) 84 #define DA_FAT0_FMT_MASK (3 << 0) 85 #define DA_FMT_I2S 0 86 #define DA_FMT_LJ 1 87 #define DA_FMT_RJ 2 88 #define DA_FAT1 0x08 89 #define DA_ISTA 0x0c 90 #define DA_ISTA_TXUI_INT (1 << 6) 91 #define DA_ISTA_TXEI_INT (1 << 4) 92 #define DA_ISTA_RXAI_INT (1 << 0) 93 #define DA_RXFIFO 0x10 94 #define DA_FCTL 0x14 95 #define DA_FCTL_HUB_EN (1 << 31) 96 #define DA_FCTL_FTX (1 << 25) 97 #define DA_FCTL_FRX (1 << 24) 98 #define DA_FCTL_TXTL_MASK (0x7f << 12) 99 #define DA_FCTL_TXTL(v) (((v) & 0x7f) << 12) 100 #define DA_FCTL_TXIM (1 << 2) 101 #define DA_FSTA 0x18 102 #define DA_FSTA_TXE_CNT(v) (((v) >> 16) & 0xff) 103 #define DA_FSTA_RXA_CNT(v) ((v) & 0x3f) 104 #define DA_INT 0x1c 105 #define DA_INT_TX_DRQ (1 << 7) 106 #define DA_INT_TXUI_EN (1 << 6) 107 #define DA_INT_TXEI_EN (1 << 4) 108 #define DA_INT_RX_DRQ (1 << 3) 109 #define DA_INT_RXAI_EN (1 << 0) 110 #define DA_TXFIFO 0x20 111 #define DA_CLKD 0x24 112 #define DA_CLKD_MCLKO_EN_SUN8I (1 << 8) 113 #define DA_CLKD_MCLKO_EN_SUN4I (1 << 7) 114 #define DA_CLKD_BCLKDIV_SUN8I(n) (((n) & 0xf) << 4) 115 #define DA_CLKD_BCLKDIV_SUN8I_MASK (0xf << 4) 116 #define DA_CLKD_BCLKDIV_SUN4I(n) (((n) & 7) << 4) 117 #define DA_CLKD_BCLKDIV_SUN4I_MASK (7 << 4) 118 #define DA_CLKD_BCLKDIV_8 3 119 #define DA_CLKD_BCLKDIV_16 5 120 #define DA_CLKD_MCLKDIV(n) (((n) & 0xff) << 0) 121 #define DA_CLKD_MCLKDIV_MASK (0xf << 0) 122 #define DA_CLKD_MCLKDIV_1 0 123 #define DA_TXCNT 0x28 124 #define DA_RXCNT 0x2c 125 #define DA_CHCFG 0x30 /* sun8i */ 126 #define DA_CHCFG_TX_SLOT_HIZ (1 << 9) 127 #define DA_CHCFG_TXN_STATE (1 << 8) 128 #define DA_CHCFG_RX_SLOT_NUM_MASK (7 << 4) 129 #define DA_CHCFG_RX_SLOT_NUM(n) (((n) & 7) << 4) 130 #define DA_CHCFG_TX_SLOT_NUM_MASK (7 << 0) 131 #define DA_CHCFG_TX_SLOT_NUM(n) (((n) & 7) << 0) 132 133 #define DA_CHSEL_OFFSET(n) (((n) & 3) << 12) /* sun8i */ 134 #define DA_CHSEL_OFFSET_MASK (3 << 12) /* sun8i */ 135 #define DA_CHSEL_EN(n) (((n) & 0xff) << 4) 136 #define DA_CHSEL_EN_MASK (0xff << 4) 137 #define DA_CHSEL_SEL(n) (((n) & 7) << 0) 138 #define DA_CHSEL_SEL_MASK (7 << 0) 139 140 #define AUDIO_BUFFER_SIZE 48000 * 4 141 142 #define AW_I2S_SAMPLE_RATE 48000 143 #define AW_I2S_CLK_RATE 24576000 144 145 enum sunxi_i2s_type { 146 SUNXI_I2S_SUN4I, 147 SUNXI_I2S_SUN8I, 148 }; 149 150 struct sunxi_i2s_config { 151 const char *name; 152 enum sunxi_i2s_type type; 153 bus_size_t txchsel; 154 bus_size_t txchmap; 155 bus_size_t rxchsel; 156 bus_size_t rxchmap; 157 }; 158 159 static const struct sunxi_i2s_config sun50i_a64_codec_config = { 160 .name = "Audio Codec (digital part)", 161 .type = SUNXI_I2S_SUN4I, 162 .txchsel = 0x30, 163 .txchmap = 0x34, 164 .rxchsel = 0x38, 165 .rxchmap = 0x3c, 166 }; 167 168 static const struct sunxi_i2s_config sun8i_h3_config = { 169 .name = "I2S/PCM controller", 170 .type = SUNXI_I2S_SUN8I, 171 .txchsel = 0x34, 172 .txchmap = 0x44, 173 .rxchsel = 0x54, 174 .rxchmap = 0x58, 175 }; 176 177 static const u_int sun4i_i2s_bclk_divmap[] = { 178 [0] = 2, 179 [1] = 4, 180 [2] = 6, 181 [3] = 8, 182 [4] = 12, 183 [5] = 16, 184 }; 185 186 static const u_int sun4i_i2s_mclk_divmap[] = { 187 [0] = 1, 188 [1] = 2, 189 [2] = 4, 190 [3] = 6, 191 [4] = 8, 192 [5] = 12, 193 [6] = 16, 194 [7] = 24, 195 }; 196 197 static const u_int sun8i_i2s_divmap[] = { 198 [1] = 1, 199 [2] = 2, 200 [3] = 4, 201 [4] = 6, 202 [5] = 8, 203 [6] = 12, 204 [7] = 16, 205 [8] = 24, 206 [9] = 32, 207 [10] = 48, 208 [11] = 64, 209 [12] = 96, 210 [13] = 128, 211 [14] = 176, 212 [15] = 192, 213 }; 214 215 216 static struct ofw_compat_data compat_data[] = { 217 { "allwinner,sun50i-a64-codec-i2s", (uintptr_t)&sun50i_a64_codec_config }, 218 { "allwinner,sun8i-h3-i2s", (uintptr_t)&sun8i_h3_config }, 219 { NULL, 0 } 220 }; 221 222 static struct resource_spec aw_i2s_spec[] = { 223 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 224 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 225 { -1, 0 } 226 }; 227 228 struct aw_i2s_softc { 229 device_t dev; 230 struct resource *res[2]; 231 struct mtx mtx; 232 clk_t clk; 233 struct sunxi_i2s_config *cfg; 234 void * intrhand; 235 /* pointers to playback/capture buffers */ 236 uint32_t play_ptr; 237 uint32_t rec_ptr; 238 }; 239 240 #define I2S_LOCK(sc) mtx_lock(&(sc)->mtx) 241 #define I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 242 #define I2S_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) 243 #define I2S_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) 244 #define I2S_TYPE(sc) ((sc)->cfg->type) 245 246 static int aw_i2s_probe(device_t dev); 247 static int aw_i2s_attach(device_t dev); 248 static int aw_i2s_detach(device_t dev); 249 250 static u_int 251 sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div) 252 { 253 u_int n; 254 255 for (n = 0; n < divmaplen; n++) 256 if (divmap[n] == div) 257 return n; 258 259 return -1; 260 } 261 262 static uint32_t sc_fmt[] = { 263 SND_FORMAT(AFMT_S16_LE, 2, 0), 264 0 265 }; 266 static struct pcmchan_caps aw_i2s_caps = {AW_I2S_SAMPLE_RATE, AW_I2S_SAMPLE_RATE, sc_fmt, 0}; 267 268 269 static int 270 aw_i2s_init(struct aw_i2s_softc *sc) 271 { 272 uint32_t val; 273 int error; 274 275 error = clk_enable(sc->clk); 276 if (error != 0) { 277 device_printf(sc->dev, "cannot enable mod clock\n"); 278 return (ENXIO); 279 } 280 281 /* Reset */ 282 val = I2S_READ(sc, DA_CTL); 283 val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN); 284 I2S_WRITE(sc, DA_CTL, val); 285 286 val = I2S_READ(sc, DA_FCTL); 287 val &= ~(DA_FCTL_FTX|DA_FCTL_FRX); 288 val &= ~(DA_FCTL_TXTL_MASK); 289 val |= DA_FCTL_TXTL(FIFO_LEVEL); 290 I2S_WRITE(sc, DA_FCTL, val); 291 292 I2S_WRITE(sc, DA_TXCNT, 0); 293 I2S_WRITE(sc, DA_RXCNT, 0); 294 295 /* Enable */ 296 val = I2S_READ(sc, DA_CTL); 297 val |= DA_CTL_GEN; 298 I2S_WRITE(sc, DA_CTL, val); 299 val |= DA_CTL_SDO_EN; 300 I2S_WRITE(sc, DA_CTL, val); 301 302 /* Setup channels */ 303 I2S_WRITE(sc, sc->cfg->txchmap, 0x76543210); 304 val = I2S_READ(sc, sc->cfg->txchsel); 305 val &= ~DA_CHSEL_EN_MASK; 306 val |= DA_CHSEL_EN(3); 307 val &= ~DA_CHSEL_SEL_MASK; 308 val |= DA_CHSEL_SEL(1); 309 I2S_WRITE(sc, sc->cfg->txchsel, val); 310 I2S_WRITE(sc, sc->cfg->rxchmap, 0x76543210); 311 val = I2S_READ(sc, sc->cfg->rxchsel); 312 val &= ~DA_CHSEL_EN_MASK; 313 val |= DA_CHSEL_EN(3); 314 val &= ~DA_CHSEL_SEL_MASK; 315 val |= DA_CHSEL_SEL(1); 316 I2S_WRITE(sc, sc->cfg->rxchsel, val); 317 318 if (I2S_TYPE(sc) == SUNXI_I2S_SUN8I) { 319 val = I2S_READ(sc, DA_CHCFG); 320 val &= ~DA_CHCFG_TX_SLOT_NUM_MASK; 321 val |= DA_CHCFG_TX_SLOT_NUM(1); 322 val &= ~DA_CHCFG_RX_SLOT_NUM_MASK; 323 val |= DA_CHCFG_RX_SLOT_NUM(1); 324 I2S_WRITE(sc, DA_CHCFG, val); 325 } 326 327 return (0); 328 } 329 330 static int 331 aw_i2s_probe(device_t dev) 332 { 333 if (!ofw_bus_status_okay(dev)) 334 return (ENXIO); 335 336 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 337 return (ENXIO); 338 339 device_set_desc(dev, "Allwinner I2S"); 340 return (BUS_PROBE_DEFAULT); 341 } 342 343 static int 344 aw_i2s_attach(device_t dev) 345 { 346 struct aw_i2s_softc *sc; 347 int error; 348 phandle_t node; 349 hwreset_t rst; 350 clk_t clk; 351 352 sc = device_get_softc(dev); 353 sc->dev = dev; 354 355 sc->cfg = (void*)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 356 357 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 358 359 if (bus_alloc_resources(dev, aw_i2s_spec, sc->res) != 0) { 360 device_printf(dev, "cannot allocate resources for device\n"); 361 error = ENXIO; 362 goto fail; 363 } 364 365 error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk); 366 if (error != 0) { 367 device_printf(dev, "cannot get i2s_clk clock\n"); 368 goto fail; 369 } 370 371 error = clk_get_by_ofw_name(dev, 0, "apb", &clk); 372 if (error != 0) { 373 device_printf(dev, "cannot get APB clock\n"); 374 goto fail; 375 } 376 377 error = clk_enable(clk); 378 if (error != 0) { 379 device_printf(dev, "cannot enable APB clock\n"); 380 goto fail; 381 } 382 383 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { 384 error = hwreset_deassert(rst); 385 if (error != 0) { 386 device_printf(dev, "cannot de-assert reset\n"); 387 goto fail; 388 } 389 } 390 391 aw_i2s_init(sc); 392 393 node = ofw_bus_get_node(dev); 394 OF_device_register_xref(OF_xref_from_node(node), dev); 395 396 return (0); 397 398 fail: 399 aw_i2s_detach(dev); 400 return (error); 401 } 402 403 static int 404 aw_i2s_detach(device_t dev) 405 { 406 struct aw_i2s_softc *i2s; 407 408 i2s = device_get_softc(dev); 409 410 if (i2s->clk) 411 clk_release(i2s->clk); 412 413 if (i2s->intrhand != NULL) 414 bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand); 415 416 bus_release_resources(dev, aw_i2s_spec, i2s->res); 417 mtx_destroy(&i2s->mtx); 418 419 return (0); 420 } 421 422 static int 423 aw_i2s_dai_init(device_t dev, uint32_t format) 424 { 425 struct aw_i2s_softc *sc; 426 int fmt, pol; 427 uint32_t ctl, fat0, chsel; 428 u_int offset; 429 430 sc = device_get_softc(dev); 431 432 fmt = AUDIO_DAI_FORMAT_FORMAT(format); 433 pol = AUDIO_DAI_FORMAT_POLARITY(format); 434 435 ctl = I2S_READ(sc, DA_CTL); 436 fat0 = I2S_READ(sc, DA_FAT0); 437 438 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 439 fat0 &= ~DA_FAT0_FMT_MASK; 440 switch (fmt) { 441 case AUDIO_DAI_FORMAT_I2S: 442 fat0 |= DA_FMT_I2S; 443 break; 444 case AUDIO_DAI_FORMAT_RJ: 445 fat0 |= DA_FMT_RJ; 446 break; 447 case AUDIO_DAI_FORMAT_LJ: 448 fat0 |= DA_FMT_LJ; 449 break; 450 default: 451 return EINVAL; 452 } 453 ctl &= ~DA_CTL_PCM; 454 } else { 455 ctl &= ~DA_CTL_MODE_SEL_MASK; 456 switch (fmt) { 457 case AUDIO_DAI_FORMAT_I2S: 458 ctl |= DA_CTL_MODE_SEL_LJ; 459 offset = 1; 460 break; 461 case AUDIO_DAI_FORMAT_LJ: 462 ctl |= DA_CTL_MODE_SEL_LJ; 463 offset = 0; 464 break; 465 case AUDIO_DAI_FORMAT_RJ: 466 ctl |= DA_CTL_MODE_SEL_RJ; 467 offset = 0; 468 break; 469 case AUDIO_DAI_FORMAT_DSPA: 470 ctl |= DA_CTL_MODE_SEL_PCM; 471 offset = 1; 472 break; 473 case AUDIO_DAI_FORMAT_DSPB: 474 ctl |= DA_CTL_MODE_SEL_PCM; 475 offset = 0; 476 break; 477 default: 478 return EINVAL; 479 } 480 481 chsel = I2S_READ(sc, sc->cfg->txchsel); 482 chsel &= ~DA_CHSEL_OFFSET_MASK; 483 chsel |= DA_CHSEL_OFFSET(offset); 484 I2S_WRITE(sc, sc->cfg->txchsel, chsel); 485 486 chsel = I2S_READ(sc, sc->cfg->rxchsel); 487 chsel &= ~DA_CHSEL_OFFSET_MASK; 488 chsel |= DA_CHSEL_OFFSET(offset); 489 I2S_WRITE(sc, sc->cfg->rxchsel, chsel); 490 } 491 492 fat0 &= ~(DA_FAT0_LRCP_MASK|DA_FAT0_BCP_MASK); 493 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 494 if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) 495 fat0 |= DA_BCP_INVERTED; 496 if (AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) 497 fat0 |= DA_LRCP_INVERTED; 498 } else { 499 if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol)) 500 fat0 |= DA_BCP_INVERTED; 501 if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol)) 502 fat0 |= DA_LRCP_INVERTED; 503 504 fat0 &= ~DA_FAT0_LRCK_PERIOD_MASK; 505 fat0 |= DA_FAT0_LRCK_PERIOD(32 - 1); 506 } 507 508 I2S_WRITE(sc, DA_CTL, ctl); 509 I2S_WRITE(sc, DA_FAT0, fat0); 510 511 return (0); 512 } 513 514 515 static int 516 aw_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf) 517 { 518 struct aw_i2s_softc *sc; 519 int ret = 0; 520 uint32_t val, status; 521 522 sc = device_get_softc(dev); 523 524 I2S_LOCK(sc); 525 526 status = I2S_READ(sc, DA_ISTA); 527 /* Clear interrupts */ 528 // device_printf(sc->dev, "status: %08x\n", status); 529 I2S_WRITE(sc, DA_ISTA, status); 530 531 if (status & DA_ISTA_TXEI_INT) { 532 uint8_t *samples; 533 uint32_t count, size, readyptr, written, empty; 534 535 val = I2S_READ(sc, DA_FSTA); 536 empty = DA_FSTA_TXE_CNT(val); 537 count = sndbuf_getready(play_buf); 538 size = sndbuf_getsize(play_buf); 539 readyptr = sndbuf_getreadyptr(play_buf); 540 541 samples = (uint8_t*)sndbuf_getbuf(play_buf); 542 written = 0; 543 if (empty > count / 2) 544 empty = count / 2; 545 for (; empty > 0; empty--) { 546 val = (samples[readyptr++ % size] << 16); 547 val |= (samples[readyptr++ % size] << 24); 548 written += 2; 549 I2S_WRITE(sc, DA_TXFIFO, val); 550 } 551 sc->play_ptr += written; 552 sc->play_ptr %= size; 553 ret |= AUDIO_DAI_PLAY_INTR; 554 } 555 556 if (status & DA_ISTA_RXAI_INT) { 557 uint8_t *samples; 558 uint32_t count, size, freeptr, recorded, available; 559 560 val = I2S_READ(sc, DA_FSTA); 561 available = DA_FSTA_RXA_CNT(val); 562 563 count = sndbuf_getfree(rec_buf); 564 size = sndbuf_getsize(rec_buf); 565 freeptr = sndbuf_getfreeptr(rec_buf); 566 samples = (uint8_t*)sndbuf_getbuf(rec_buf); 567 recorded = 0; 568 if (available > count / 2) 569 available = count / 2; 570 571 for (; available > 0; available--) { 572 val = I2S_READ(sc, DA_RXFIFO); 573 samples[freeptr++ % size] = (val >> 16) & 0xff; 574 samples[freeptr++ % size] = (val >> 24) & 0xff; 575 recorded += 2; 576 } 577 sc->rec_ptr += recorded; 578 sc->rec_ptr %= size; 579 ret |= AUDIO_DAI_REC_INTR; 580 } 581 582 I2S_UNLOCK(sc); 583 584 return (ret); 585 } 586 587 static struct pcmchan_caps * 588 aw_i2s_dai_get_caps(device_t dev) 589 { 590 return (&aw_i2s_caps); 591 } 592 593 static int 594 aw_i2s_dai_trigger(device_t dev, int go, int pcm_dir) 595 { 596 struct aw_i2s_softc *sc = device_get_softc(dev); 597 uint32_t val; 598 599 if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC)) 600 return (EINVAL); 601 602 switch (go) { 603 case PCMTRIG_START: 604 if (pcm_dir == PCMDIR_PLAY) { 605 /* Flush FIFO */ 606 val = I2S_READ(sc, DA_FCTL); 607 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX); 608 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX); 609 610 /* Reset TX sample counter */ 611 I2S_WRITE(sc, DA_TXCNT, 0); 612 613 /* Enable TX block */ 614 val = I2S_READ(sc, DA_CTL); 615 I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN); 616 617 /* Enable TX underrun interrupt */ 618 val = I2S_READ(sc, DA_INT); 619 I2S_WRITE(sc, DA_INT, val | DA_INT_TXEI_EN); 620 } 621 622 if (pcm_dir == PCMDIR_REC) { 623 /* Flush FIFO */ 624 val = I2S_READ(sc, DA_FCTL); 625 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX); 626 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX); 627 628 /* Reset RX sample counter */ 629 I2S_WRITE(sc, DA_RXCNT, 0); 630 631 /* Enable RX block */ 632 val = I2S_READ(sc, DA_CTL); 633 I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN); 634 635 /* Enable RX data available interrupt */ 636 val = I2S_READ(sc, DA_INT); 637 I2S_WRITE(sc, DA_INT, val | DA_INT_RXAI_EN); 638 } 639 640 break; 641 642 case PCMTRIG_STOP: 643 case PCMTRIG_ABORT: 644 I2S_LOCK(sc); 645 646 if (pcm_dir == PCMDIR_PLAY) { 647 /* Disable TX block */ 648 val = I2S_READ(sc, DA_CTL); 649 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN); 650 651 /* Enable TX underrun interrupt */ 652 val = I2S_READ(sc, DA_INT); 653 I2S_WRITE(sc, DA_INT, val & ~DA_INT_TXEI_EN); 654 655 sc->play_ptr = 0; 656 } else { 657 /* Disable RX block */ 658 val = I2S_READ(sc, DA_CTL); 659 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN); 660 661 /* Disable RX data available interrupt */ 662 val = I2S_READ(sc, DA_INT); 663 I2S_WRITE(sc, DA_INT, val & ~DA_INT_RXAI_EN); 664 665 sc->rec_ptr = 0; 666 } 667 668 I2S_UNLOCK(sc); 669 break; 670 } 671 672 return (0); 673 } 674 675 static uint32_t 676 aw_i2s_dai_get_ptr(device_t dev, int pcm_dir) 677 { 678 struct aw_i2s_softc *sc; 679 uint32_t ptr; 680 681 sc = device_get_softc(dev); 682 683 I2S_LOCK(sc); 684 if (pcm_dir == PCMDIR_PLAY) 685 ptr = sc->play_ptr; 686 else 687 ptr = sc->rec_ptr; 688 I2S_UNLOCK(sc); 689 690 return ptr; 691 } 692 693 static int 694 aw_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg) 695 { 696 struct aw_i2s_softc *sc = device_get_softc(dev); 697 698 if (bus_setup_intr(dev, sc->res[1], 699 INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg, 700 &sc->intrhand)) { 701 device_printf(dev, "cannot setup interrupt handler\n"); 702 return (ENXIO); 703 } 704 705 return (0); 706 } 707 708 static uint32_t 709 aw_i2s_dai_set_chanformat(device_t dev, uint32_t format) 710 { 711 712 return (0); 713 } 714 715 static int 716 aw_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir) 717 { 718 struct aw_i2s_softc *sc; 719 int bclk_val, mclk_val; 720 uint32_t val; 721 int error; 722 723 sc = device_get_softc(dev); 724 725 error = clk_set_freq(sc->clk, AW_I2S_CLK_RATE, CLK_SET_ROUND_DOWN); 726 if (error != 0) { 727 device_printf(sc->dev, 728 "couldn't set mod clock rate to %u Hz: %d\n", AW_I2S_CLK_RATE, error); 729 return error; 730 } 731 error = clk_enable(sc->clk); 732 if (error != 0) { 733 device_printf(sc->dev, 734 "couldn't enable mod clock: %d\n", error); 735 return error; 736 } 737 738 const u_int bclk_prate = I2S_TYPE(sc) == SUNXI_I2S_SUN4I ? rate : AW_I2S_CLK_RATE; 739 740 const u_int bclk_div = bclk_prate / (2 * 32 * AW_I2S_SAMPLE_RATE); 741 const u_int mclk_div = AW_I2S_CLK_RATE / rate; 742 743 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 744 bclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_bclk_divmap, 745 nitems(sun4i_i2s_bclk_divmap), bclk_div); 746 mclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_mclk_divmap, 747 nitems(sun4i_i2s_mclk_divmap), mclk_div); 748 } else { 749 bclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, 750 nitems(sun8i_i2s_divmap), bclk_div); 751 mclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, 752 nitems(sun8i_i2s_divmap), mclk_div); 753 } 754 if (bclk_val == -1 || mclk_val == -1) { 755 device_printf(sc->dev, "couldn't configure bclk/mclk dividers\n"); 756 return EIO; 757 } 758 759 val = I2S_READ(sc, DA_CLKD); 760 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 761 val |= DA_CLKD_MCLKO_EN_SUN4I; 762 val &= ~DA_CLKD_BCLKDIV_SUN4I_MASK; 763 val |= DA_CLKD_BCLKDIV_SUN4I(bclk_val); 764 } else { 765 val |= DA_CLKD_MCLKO_EN_SUN8I; 766 val &= ~DA_CLKD_BCLKDIV_SUN8I_MASK; 767 val |= DA_CLKD_BCLKDIV_SUN8I(bclk_val); 768 } 769 val &= ~DA_CLKD_MCLKDIV_MASK; 770 val |= DA_CLKD_MCLKDIV(mclk_val); 771 I2S_WRITE(sc, DA_CLKD, val); 772 773 774 return (0); 775 } 776 777 static uint32_t 778 aw_i2s_dai_set_chanspeed(device_t dev, uint32_t speed) 779 { 780 781 return (speed); 782 } 783 784 static device_method_t aw_i2s_methods[] = { 785 /* Device interface */ 786 DEVMETHOD(device_probe, aw_i2s_probe), 787 DEVMETHOD(device_attach, aw_i2s_attach), 788 DEVMETHOD(device_detach, aw_i2s_detach), 789 790 DEVMETHOD(audio_dai_init, aw_i2s_dai_init), 791 DEVMETHOD(audio_dai_setup_intr, aw_i2s_dai_setup_intr), 792 DEVMETHOD(audio_dai_set_sysclk, aw_i2s_dai_set_sysclk), 793 DEVMETHOD(audio_dai_set_chanspeed, aw_i2s_dai_set_chanspeed), 794 DEVMETHOD(audio_dai_set_chanformat, aw_i2s_dai_set_chanformat), 795 DEVMETHOD(audio_dai_intr, aw_i2s_dai_intr), 796 DEVMETHOD(audio_dai_get_caps, aw_i2s_dai_get_caps), 797 DEVMETHOD(audio_dai_trigger, aw_i2s_dai_trigger), 798 DEVMETHOD(audio_dai_get_ptr, aw_i2s_dai_get_ptr), 799 800 DEVMETHOD_END 801 }; 802 803 static driver_t aw_i2s_driver = { 804 "i2s", 805 aw_i2s_methods, 806 sizeof(struct aw_i2s_softc), 807 }; 808 809 static devclass_t aw_i2s_devclass; 810 811 DRIVER_MODULE(aw_i2s, simplebus, aw_i2s_driver, aw_i2s_devclass, 0, 0); 812 SIMPLEBUS_PNP_INFO(compat_data); 813