1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * SOCFPGA Reset Manager. 33 * Chapter 3, Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/rman.h> 46 #include <sys/timeet.h> 47 #include <sys/timetc.h> 48 #include <sys/sysctl.h> 49 50 #include <dev/fdt/fdt_common.h> 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <machine/bus.h> 56 #include <machine/fdt.h> 57 #include <machine/cpu.h> 58 #include <machine/intr.h> 59 60 #include <arm/altera/socfpga/socfpga_common.h> 61 #include <arm/altera/socfpga/socfpga_rstmgr.h> 62 #include <arm/altera/socfpga/socfpga_l3regs.h> 63 64 struct rstmgr_softc { 65 struct resource *res[1]; 66 bus_space_tag_t bst; 67 bus_space_handle_t bsh; 68 device_t dev; 69 }; 70 71 struct rstmgr_softc *rstmgr_sc; 72 73 static struct resource_spec rstmgr_spec[] = { 74 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 75 { -1, 0 } 76 }; 77 78 enum { 79 RSTMGR_SYSCTL_FPGA2HPS, 80 RSTMGR_SYSCTL_LWHPS2FPGA, 81 RSTMGR_SYSCTL_HPS2FPGA 82 }; 83 84 static int 85 l3remap(struct rstmgr_softc *sc, int remap, int enable) 86 { 87 uint32_t addr, paddr; 88 bus_addr_t vaddr; 89 phandle_t node; 90 int reg; 91 92 /* 93 * Control whether bridge is visible to L3 masters or not. 94 * Register is write-only. 95 */ 96 97 reg = REMAP_MPUZERO; 98 if (enable) 99 reg |= (remap); 100 else 101 reg &= ~(remap); 102 103 node = OF_finddevice("l3regs"); 104 if (node == -1) { 105 device_printf(sc->dev, "Can't find l3regs node\n"); 106 return (1); 107 } 108 109 if ((OF_getprop(node, "reg", &paddr, sizeof(paddr))) > 0) { 110 addr = fdt32_to_cpu(paddr); 111 if (bus_space_map(fdtbus_bs_tag, addr, 0x4, 0, &vaddr) == 0) { 112 bus_space_write_4(fdtbus_bs_tag, vaddr, 113 L3REGS_REMAP, reg); 114 return (0); 115 } 116 } 117 118 return (1); 119 } 120 121 static int 122 rstmgr_sysctl(SYSCTL_HANDLER_ARGS) 123 { 124 struct rstmgr_softc *sc; 125 int enable; 126 int remap; 127 int err; 128 int reg; 129 int bit; 130 131 sc = arg1; 132 133 switch (arg2) { 134 case RSTMGR_SYSCTL_FPGA2HPS: 135 bit = BRGMODRST_FPGA2HPS; 136 remap = 0; 137 break; 138 case RSTMGR_SYSCTL_LWHPS2FPGA: 139 bit = BRGMODRST_LWHPS2FPGA; 140 remap = REMAP_LWHPS2FPGA; 141 break; 142 case RSTMGR_SYSCTL_HPS2FPGA: 143 bit = BRGMODRST_HPS2FPGA; 144 remap = REMAP_HPS2FPGA; 145 break; 146 default: 147 return (1); 148 }; 149 150 reg = READ4(sc, RSTMGR_BRGMODRST); 151 enable = reg & bit ? 0 : 1; 152 153 err = sysctl_handle_int(oidp, &enable, 0, req); 154 if (err || !req->newptr) 155 return (err); 156 157 if (enable == 1) 158 reg &= ~(bit); 159 else if (enable == 0) 160 reg |= (bit); 161 else 162 return (EINVAL); 163 164 WRITE4(sc, RSTMGR_BRGMODRST, reg); 165 l3remap(sc, remap, enable); 166 167 return (0); 168 } 169 170 int 171 rstmgr_warmreset(void) 172 { 173 struct rstmgr_softc *sc; 174 175 sc = rstmgr_sc; 176 if (sc == NULL) 177 return (1); 178 179 /* Request warm reset */ 180 WRITE4(sc, RSTMGR_CTRL, 181 CTRL_SWWARMRSTREQ); 182 183 return (0); 184 } 185 186 static int 187 rstmgr_add_sysctl(struct rstmgr_softc *sc) 188 { 189 struct sysctl_oid_list *children; 190 struct sysctl_ctx_list *ctx; 191 192 ctx = device_get_sysctl_ctx(sc->dev); 193 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 194 195 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fpga2hps", 196 CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_FPGA2HPS, 197 rstmgr_sysctl, "I", "Enable fpga2hps bridge"); 198 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lwhps2fpga", 199 CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_LWHPS2FPGA, 200 rstmgr_sysctl, "I", "Enable lwhps2fpga bridge"); 201 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hps2fpga", 202 CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_HPS2FPGA, 203 rstmgr_sysctl, "I", "Enable hps2fpga bridge"); 204 205 return (0); 206 } 207 208 static int 209 rstmgr_probe(device_t dev) 210 { 211 212 if (!ofw_bus_status_okay(dev)) 213 return (ENXIO); 214 215 if (!ofw_bus_is_compatible(dev, "altr,rst-mgr")) 216 return (ENXIO); 217 218 device_set_desc(dev, "Reset Manager"); 219 return (BUS_PROBE_DEFAULT); 220 } 221 222 static int 223 rstmgr_attach(device_t dev) 224 { 225 struct rstmgr_softc *sc; 226 227 sc = device_get_softc(dev); 228 sc->dev = dev; 229 230 if (bus_alloc_resources(dev, rstmgr_spec, sc->res)) { 231 device_printf(dev, "could not allocate resources\n"); 232 return (ENXIO); 233 } 234 235 /* Memory interface */ 236 sc->bst = rman_get_bustag(sc->res[0]); 237 sc->bsh = rman_get_bushandle(sc->res[0]); 238 239 rstmgr_sc = sc; 240 rstmgr_add_sysctl(sc); 241 242 return (0); 243 } 244 245 static device_method_t rstmgr_methods[] = { 246 DEVMETHOD(device_probe, rstmgr_probe), 247 DEVMETHOD(device_attach, rstmgr_attach), 248 { 0, 0 } 249 }; 250 251 static driver_t rstmgr_driver = { 252 "rstmgr", 253 rstmgr_methods, 254 sizeof(struct rstmgr_softc), 255 }; 256 257 static devclass_t rstmgr_devclass; 258 259 DRIVER_MODULE(rstmgr, simplebus, rstmgr_driver, rstmgr_devclass, 0, 0); 260