1 /* $NetBSD: db_interface.c,v 1.33 2003/08/25 04:51:10 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 37 #include <sys/cdefs.h> 38 #include "opt_ddb.h" 39 40 #include <sys/param.h> 41 #include <sys/cons.h> 42 #include <sys/proc.h> 43 #include <sys/reboot.h> 44 #include <sys/systm.h> /* just for boothowto */ 45 #include <sys/exec.h> 46 #ifdef KDB 47 #include <sys/kdb.h> 48 #endif 49 50 #include <vm/vm.h> 51 #include <vm/pmap.h> 52 #include <vm/vm_map.h> 53 #include <vm/vm_extern.h> 54 55 #include <machine/db_machdep.h> 56 #include <machine/cpu.h> 57 #include <machine/machdep.h> 58 #include <machine/vmparam.h> 59 60 #include <ddb/ddb.h> 61 #include <ddb/db_access.h> 62 #include <ddb/db_command.h> 63 #include <ddb/db_output.h> 64 #include <ddb/db_variables.h> 65 #include <ddb/db_sym.h> 66 67 static int nil = 0; 68 69 int db_access_und_sp (struct db_variable *, db_expr_t *, int); 70 int db_access_abt_sp (struct db_variable *, db_expr_t *, int); 71 int db_access_irq_sp (struct db_variable *, db_expr_t *, int); 72 73 static db_varfcn_t db_frame; 74 75 #define DB_OFFSET(x) (db_expr_t *)offsetof(struct trapframe, x) 76 struct db_variable db_regs[] = { 77 { "spsr", DB_OFFSET(tf_spsr), db_frame }, 78 { "r0", DB_OFFSET(tf_r0), db_frame }, 79 { "r1", DB_OFFSET(tf_r1), db_frame }, 80 { "r2", DB_OFFSET(tf_r2), db_frame }, 81 { "r3", DB_OFFSET(tf_r3), db_frame }, 82 { "r4", DB_OFFSET(tf_r4), db_frame }, 83 { "r5", DB_OFFSET(tf_r5), db_frame }, 84 { "r6", DB_OFFSET(tf_r6), db_frame }, 85 { "r7", DB_OFFSET(tf_r7), db_frame }, 86 { "r8", DB_OFFSET(tf_r8), db_frame }, 87 { "r9", DB_OFFSET(tf_r9), db_frame }, 88 { "r10", DB_OFFSET(tf_r10), db_frame }, 89 { "r11", DB_OFFSET(tf_r11), db_frame }, 90 { "r12", DB_OFFSET(tf_r12), db_frame }, 91 { "usr_sp", DB_OFFSET(tf_usr_sp), db_frame }, 92 { "usr_lr", DB_OFFSET(tf_usr_lr), db_frame }, 93 { "svc_sp", DB_OFFSET(tf_svc_sp), db_frame }, 94 { "svc_lr", DB_OFFSET(tf_svc_lr), db_frame }, 95 { "pc", DB_OFFSET(tf_pc), db_frame }, 96 { "und_sp", &nil, db_access_und_sp, }, 97 { "abt_sp", &nil, db_access_abt_sp, }, 98 { "irq_sp", &nil, db_access_irq_sp, }, 99 }; 100 101 struct db_variable *db_eregs = db_regs + nitems(db_regs); 102 103 int 104 db_access_und_sp(struct db_variable *vp, db_expr_t *valp, int rw) 105 { 106 107 if (rw == DB_VAR_GET) { 108 *valp = get_stackptr(PSR_UND32_MODE); 109 return (1); 110 } 111 return (0); 112 } 113 114 int 115 db_access_abt_sp(struct db_variable *vp, db_expr_t *valp, int rw) 116 { 117 118 if (rw == DB_VAR_GET) { 119 *valp = get_stackptr(PSR_ABT32_MODE); 120 return (1); 121 } 122 return (0); 123 } 124 125 int 126 db_access_irq_sp(struct db_variable *vp, db_expr_t *valp, int rw) 127 { 128 129 if (rw == DB_VAR_GET) { 130 *valp = get_stackptr(PSR_IRQ32_MODE); 131 return (1); 132 } 133 return (0); 134 } 135 136 int db_frame(struct db_variable *vp, db_expr_t *valp, int rw) 137 { 138 int *reg; 139 140 if (kdb_frame == NULL) 141 return (0); 142 143 reg = (int *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep); 144 if (rw == DB_VAR_GET) 145 *valp = *reg; 146 else 147 *reg = *valp; 148 return (1); 149 } 150 151 void 152 db_show_mdpcpu(struct pcpu *pc) 153 { 154 155 db_printf("curpmap = %p\n", pc->pc_curpmap); 156 } 157 158 int 159 db_validate_address(vm_offset_t addr) 160 { 161 struct proc *p = curproc; 162 struct pmap *pmap; 163 164 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 165 #ifndef ARM32_NEW_VM_LAYOUT 166 addr >= VM_MAXUSER_ADDRESS 167 #else 168 addr >= VM_MIN_KERNEL_ADDRESS 169 #endif 170 ) 171 pmap = kernel_pmap; 172 else 173 pmap = p->p_vmspace->vm_map.pmap; 174 175 return (pmap_extract(pmap, addr) == FALSE); 176 } 177 178 /* 179 * Read bytes from kernel address space for debugger. 180 */ 181 int 182 db_read_bytes(vm_offset_t addr, size_t size, char *data) 183 { 184 char *src = (char *)addr; 185 186 if (db_validate_address((u_int)src)) { 187 db_printf("address %p is invalid\n", src); 188 return (-1); 189 } 190 191 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) { 192 *((int*)data) = *((int*)src); 193 return (0); 194 } 195 196 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) { 197 *((short*)data) = *((short*)src); 198 return (0); 199 } 200 201 while (size-- > 0) { 202 if (db_validate_address((u_int)src)) { 203 db_printf("address %p is invalid\n", src); 204 return (-1); 205 } 206 *data++ = *src++; 207 } 208 return (0); 209 } 210 211 /* 212 * Write bytes to kernel address space for debugger. 213 */ 214 int 215 db_write_bytes(vm_offset_t addr, size_t size, char *data) 216 { 217 char *dst; 218 size_t loop; 219 220 dst = (char *)addr; 221 if (db_validate_address((u_int)dst)) { 222 db_printf("address %p is invalid\n", dst); 223 return (0); 224 } 225 226 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) 227 *((int*)dst) = *((int*)data); 228 else 229 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) 230 *((short*)dst) = *((short*)data); 231 else { 232 loop = size; 233 while (loop-- > 0) { 234 if (db_validate_address((u_int)dst)) { 235 db_printf("address %p is invalid\n", dst); 236 return (-1); 237 } 238 *dst++ = *data++; 239 } 240 } 241 242 /* make sure the caches and memory are in sync */ 243 icache_sync(addr, size); 244 245 /* In case the current page tables have been modified ... */ 246 tlb_flush_all(); 247 return (0); 248 } 249 250 static u_int 251 db_fetch_reg(int reg) 252 { 253 254 switch (reg) { 255 case 0: 256 return (kdb_frame->tf_r0); 257 case 1: 258 return (kdb_frame->tf_r1); 259 case 2: 260 return (kdb_frame->tf_r2); 261 case 3: 262 return (kdb_frame->tf_r3); 263 case 4: 264 return (kdb_frame->tf_r4); 265 case 5: 266 return (kdb_frame->tf_r5); 267 case 6: 268 return (kdb_frame->tf_r6); 269 case 7: 270 return (kdb_frame->tf_r7); 271 case 8: 272 return (kdb_frame->tf_r8); 273 case 9: 274 return (kdb_frame->tf_r9); 275 case 10: 276 return (kdb_frame->tf_r10); 277 case 11: 278 return (kdb_frame->tf_r11); 279 case 12: 280 return (kdb_frame->tf_r12); 281 case 13: 282 return (kdb_frame->tf_svc_sp); 283 case 14: 284 return (kdb_frame->tf_svc_lr); 285 case 15: 286 return (kdb_frame->tf_pc); 287 default: 288 panic("db_fetch_reg: botch"); 289 } 290 } 291 292 static u_int 293 db_branch_taken_read_int(void *cookie __unused, vm_offset_t offset, u_int *val) 294 { 295 u_int ret; 296 297 db_read_bytes(offset, 4, (char *)&ret); 298 *val = ret; 299 300 return (0); 301 } 302 303 static u_int 304 db_branch_taken_fetch_reg(void *cookie __unused, int reg) 305 { 306 307 return (db_fetch_reg(reg)); 308 } 309 310 u_int 311 branch_taken(u_int insn, db_addr_t pc) 312 { 313 register_t new_pc; 314 int ret; 315 316 ret = arm_predict_branch(NULL, insn, (register_t)pc, &new_pc, 317 db_branch_taken_fetch_reg, db_branch_taken_read_int); 318 319 if (ret != 0) 320 kdb_reenter(); 321 322 return (new_pc); 323 } 324