1 /* $NetBSD: db_interface.c,v 1.33 2003/08/25 04:51:10 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 Scott K. Stevens 5 * 6 * Mach Operating System 7 * Copyright (c) 1991,1990 Carnegie Mellon University 8 * All Rights Reserved. 9 * 10 * Permission to use, copy, modify and distribute this software and its 11 * documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 * 30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU) 31 */ 32 33 /* 34 * Interface to new debugger. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 #include "opt_ddb.h" 40 41 #include <sys/param.h> 42 #include <sys/cons.h> 43 #include <sys/proc.h> 44 #include <sys/reboot.h> 45 #include <sys/systm.h> /* just for boothowto */ 46 #include <sys/exec.h> 47 #ifdef KDB 48 #include <sys/kdb.h> 49 #endif 50 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 #include <vm/vm_map.h> 54 #include <vm/vm_extern.h> 55 56 #include <machine/db_machdep.h> 57 #include <machine/cpu.h> 58 #include <machine/machdep.h> 59 #include <machine/vmparam.h> 60 61 #include <ddb/ddb.h> 62 #include <ddb/db_access.h> 63 #include <ddb/db_command.h> 64 #include <ddb/db_output.h> 65 #include <ddb/db_variables.h> 66 #include <ddb/db_sym.h> 67 68 static int nil = 0; 69 70 int db_access_und_sp (struct db_variable *, db_expr_t *, int); 71 int db_access_abt_sp (struct db_variable *, db_expr_t *, int); 72 int db_access_irq_sp (struct db_variable *, db_expr_t *, int); 73 74 static db_varfcn_t db_frame; 75 76 #define DB_OFFSET(x) (db_expr_t *)offsetof(struct trapframe, x) 77 struct db_variable db_regs[] = { 78 { "spsr", DB_OFFSET(tf_spsr), db_frame }, 79 { "r0", DB_OFFSET(tf_r0), db_frame }, 80 { "r1", DB_OFFSET(tf_r1), db_frame }, 81 { "r2", DB_OFFSET(tf_r2), db_frame }, 82 { "r3", DB_OFFSET(tf_r3), db_frame }, 83 { "r4", DB_OFFSET(tf_r4), db_frame }, 84 { "r5", DB_OFFSET(tf_r5), db_frame }, 85 { "r6", DB_OFFSET(tf_r6), db_frame }, 86 { "r7", DB_OFFSET(tf_r7), db_frame }, 87 { "r8", DB_OFFSET(tf_r8), db_frame }, 88 { "r9", DB_OFFSET(tf_r9), db_frame }, 89 { "r10", DB_OFFSET(tf_r10), db_frame }, 90 { "r11", DB_OFFSET(tf_r11), db_frame }, 91 { "r12", DB_OFFSET(tf_r12), db_frame }, 92 { "usr_sp", DB_OFFSET(tf_usr_sp), db_frame }, 93 { "usr_lr", DB_OFFSET(tf_usr_lr), db_frame }, 94 { "svc_sp", DB_OFFSET(tf_svc_sp), db_frame }, 95 { "svc_lr", DB_OFFSET(tf_svc_lr), db_frame }, 96 { "pc", DB_OFFSET(tf_pc), db_frame }, 97 { "und_sp", &nil, db_access_und_sp, }, 98 { "abt_sp", &nil, db_access_abt_sp, }, 99 { "irq_sp", &nil, db_access_irq_sp, }, 100 }; 101 102 struct db_variable *db_eregs = db_regs + nitems(db_regs); 103 104 int 105 db_access_und_sp(struct db_variable *vp, db_expr_t *valp, int rw) 106 { 107 108 if (rw == DB_VAR_GET) { 109 *valp = get_stackptr(PSR_UND32_MODE); 110 return (1); 111 } 112 return (0); 113 } 114 115 int 116 db_access_abt_sp(struct db_variable *vp, db_expr_t *valp, int rw) 117 { 118 119 if (rw == DB_VAR_GET) { 120 *valp = get_stackptr(PSR_ABT32_MODE); 121 return (1); 122 } 123 return (0); 124 } 125 126 int 127 db_access_irq_sp(struct db_variable *vp, db_expr_t *valp, int rw) 128 { 129 130 if (rw == DB_VAR_GET) { 131 *valp = get_stackptr(PSR_IRQ32_MODE); 132 return (1); 133 } 134 return (0); 135 } 136 137 int db_frame(struct db_variable *vp, db_expr_t *valp, int rw) 138 { 139 int *reg; 140 141 if (kdb_frame == NULL) 142 return (0); 143 144 reg = (int *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep); 145 if (rw == DB_VAR_GET) 146 *valp = *reg; 147 else 148 *reg = *valp; 149 return (1); 150 } 151 152 void 153 db_show_mdpcpu(struct pcpu *pc) 154 { 155 156 #if __ARM_ARCH >= 6 157 db_printf("curpmap = %p\n", pc->pc_curpmap); 158 #endif 159 } 160 int 161 db_validate_address(vm_offset_t addr) 162 { 163 struct proc *p = curproc; 164 struct pmap *pmap; 165 166 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap || 167 #ifndef ARM32_NEW_VM_LAYOUT 168 addr >= VM_MAXUSER_ADDRESS 169 #else 170 addr >= VM_MIN_KERNEL_ADDRESS 171 #endif 172 ) 173 pmap = kernel_pmap; 174 else 175 pmap = p->p_vmspace->vm_map.pmap; 176 177 return (pmap_extract(pmap, addr) == FALSE); 178 } 179 180 /* 181 * Read bytes from kernel address space for debugger. 182 */ 183 int 184 db_read_bytes(addr, size, data) 185 vm_offset_t addr; 186 size_t size; 187 char *data; 188 { 189 char *src = (char *)addr; 190 191 if (db_validate_address((u_int)src)) { 192 db_printf("address %p is invalid\n", src); 193 return (-1); 194 } 195 196 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) { 197 *((int*)data) = *((int*)src); 198 return (0); 199 } 200 201 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) { 202 *((short*)data) = *((short*)src); 203 return (0); 204 } 205 206 while (size-- > 0) { 207 if (db_validate_address((u_int)src)) { 208 db_printf("address %p is invalid\n", src); 209 return (-1); 210 } 211 *data++ = *src++; 212 } 213 return (0); 214 } 215 216 /* 217 * Write bytes to kernel address space for debugger. 218 */ 219 int 220 db_write_bytes(vm_offset_t addr, size_t size, char *data) 221 { 222 char *dst; 223 size_t loop; 224 225 dst = (char *)addr; 226 if (db_validate_address((u_int)dst)) { 227 db_printf("address %p is invalid\n", dst); 228 return (0); 229 } 230 231 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) 232 *((int*)dst) = *((int*)data); 233 else 234 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) 235 *((short*)dst) = *((short*)data); 236 else { 237 loop = size; 238 while (loop-- > 0) { 239 if (db_validate_address((u_int)dst)) { 240 db_printf("address %p is invalid\n", dst); 241 return (-1); 242 } 243 *dst++ = *data++; 244 } 245 } 246 247 /* make sure the caches and memory are in sync */ 248 icache_sync(addr, size); 249 250 /* In case the current page tables have been modified ... */ 251 tlb_flush_all(); 252 return (0); 253 } 254 255 static u_int 256 db_fetch_reg(int reg) 257 { 258 259 switch (reg) { 260 case 0: 261 return (kdb_frame->tf_r0); 262 case 1: 263 return (kdb_frame->tf_r1); 264 case 2: 265 return (kdb_frame->tf_r2); 266 case 3: 267 return (kdb_frame->tf_r3); 268 case 4: 269 return (kdb_frame->tf_r4); 270 case 5: 271 return (kdb_frame->tf_r5); 272 case 6: 273 return (kdb_frame->tf_r6); 274 case 7: 275 return (kdb_frame->tf_r7); 276 case 8: 277 return (kdb_frame->tf_r8); 278 case 9: 279 return (kdb_frame->tf_r9); 280 case 10: 281 return (kdb_frame->tf_r10); 282 case 11: 283 return (kdb_frame->tf_r11); 284 case 12: 285 return (kdb_frame->tf_r12); 286 case 13: 287 return (kdb_frame->tf_svc_sp); 288 case 14: 289 return (kdb_frame->tf_svc_lr); 290 case 15: 291 return (kdb_frame->tf_pc); 292 default: 293 panic("db_fetch_reg: botch"); 294 } 295 } 296 297 static u_int 298 db_branch_taken_read_int(void *cookie __unused, vm_offset_t offset, u_int *val) 299 { 300 u_int ret; 301 302 db_read_bytes(offset, 4, (char *)&ret); 303 *val = ret; 304 305 return (0); 306 } 307 308 static u_int 309 db_branch_taken_fetch_reg(void *cookie __unused, int reg) 310 { 311 312 return (db_fetch_reg(reg)); 313 } 314 315 u_int 316 branch_taken(u_int insn, db_addr_t pc) 317 { 318 register_t new_pc; 319 int ret; 320 321 ret = arm_predict_branch(NULL, insn, (register_t)pc, &new_pc, 322 db_branch_taken_fetch_reg, db_branch_taken_read_int); 323 324 if (ret != 0) 325 kdb_reenter(); 326 327 return (new_pc); 328 } 329