1 /*- 2 * Copyright (c) 2011 The FreeBSD Foundation 3 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com> 4 * All rights reserved. 5 * 6 * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the company nor the name of the author may be used to 17 * endorse or promote products derived from this software without specific 18 * prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 /** 34 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer 35 */ 36 37 #include "opt_acpi.h" 38 #include "opt_platform.h" 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/bus.h> 46 #include <sys/kernel.h> 47 #include <sys/module.h> 48 #include <sys/malloc.h> 49 #include <sys/rman.h> 50 #include <sys/timeet.h> 51 #include <sys/timetc.h> 52 #include <sys/smp.h> 53 #include <sys/vdso.h> 54 #include <sys/watchdog.h> 55 #include <machine/bus.h> 56 #include <machine/cpu.h> 57 #include <machine/intr.h> 58 #include <machine/md_var.h> 59 60 #if defined(__arm__) 61 #include <machine/machdep.h> /* For arm_set_delay */ 62 #endif 63 64 #ifdef FDT 65 #include <dev/ofw/openfirm.h> 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 #endif 69 70 #ifdef DEV_ACPI 71 #include <contrib/dev/acpica/include/acpi.h> 72 #include <dev/acpica/acpivar.h> 73 #endif 74 75 #define GT_CTRL_ENABLE (1 << 0) 76 #define GT_CTRL_INT_MASK (1 << 1) 77 #define GT_CTRL_INT_STAT (1 << 2) 78 #define GT_REG_CTRL 0 79 #define GT_REG_TVAL 1 80 81 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */ 82 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */ 83 #define GT_CNTKCTL_EVNTI (0xf << 4) /* Virtual counter event bits */ 84 #define GT_CNTKCTL_EVNTDIR (1 << 3) /* Virtual counter event transition */ 85 #define GT_CNTKCTL_EVNTEN (1 << 2) /* Enables virtual counter events */ 86 #define GT_CNTKCTL_PL0VCTEN (1 << 1) /* PL0 CNTVCT and CNTFRQ access */ 87 #define GT_CNTKCTL_PL0PCTEN (1 << 0) /* PL0 CNTPCT and CNTFRQ access */ 88 89 struct arm_tmr_softc { 90 struct resource *res[4]; 91 void *ihl[4]; 92 uint32_t clkfreq; 93 struct eventtimer et; 94 bool physical; 95 }; 96 97 static struct arm_tmr_softc *arm_tmr_sc = NULL; 98 99 static struct resource_spec timer_spec[] = { 100 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Secure */ 101 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Non-secure */ 102 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, /* Virt */ 103 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, /* Hyp */ 104 { -1, 0 } 105 }; 106 107 static uint32_t arm_tmr_fill_vdso_timehands(struct vdso_timehands *vdso_th, 108 struct timecounter *tc); 109 static void arm_tmr_do_delay(int usec, void *); 110 111 static timecounter_get_t arm_tmr_get_timecount; 112 113 static struct timecounter arm_tmr_timecount = { 114 .tc_name = "ARM MPCore Timecounter", 115 .tc_get_timecount = arm_tmr_get_timecount, 116 .tc_poll_pps = NULL, 117 .tc_counter_mask = ~0u, 118 .tc_frequency = 0, 119 .tc_quality = 1000, 120 .tc_fill_vdso_timehands = arm_tmr_fill_vdso_timehands, 121 }; 122 123 #ifdef __arm__ 124 #define get_el0(x) cp15_## x ##_get() 125 #define get_el1(x) cp15_## x ##_get() 126 #define set_el0(x, val) cp15_## x ##_set(val) 127 #define set_el1(x, val) cp15_## x ##_set(val) 128 #else /* __aarch64__ */ 129 #define get_el0(x) READ_SPECIALREG(x ##_el0) 130 #define get_el1(x) READ_SPECIALREG(x ##_el1) 131 #define set_el0(x, val) WRITE_SPECIALREG(x ##_el0, val) 132 #define set_el1(x, val) WRITE_SPECIALREG(x ##_el1, val) 133 #endif 134 135 static int 136 get_freq(void) 137 { 138 return (get_el0(cntfrq)); 139 } 140 141 static uint64_t 142 get_cntxct(bool physical) 143 { 144 uint64_t val; 145 146 isb(); 147 if (physical) 148 val = get_el0(cntpct); 149 else 150 val = get_el0(cntvct); 151 152 return (val); 153 } 154 155 static int 156 set_ctrl(uint32_t val, bool physical) 157 { 158 159 if (physical) 160 set_el0(cntp_ctl, val); 161 else 162 set_el0(cntv_ctl, val); 163 isb(); 164 165 return (0); 166 } 167 168 static int 169 set_tval(uint32_t val, bool physical) 170 { 171 172 if (physical) 173 set_el0(cntp_tval, val); 174 else 175 set_el0(cntv_tval, val); 176 isb(); 177 178 return (0); 179 } 180 181 static int 182 get_ctrl(bool physical) 183 { 184 uint32_t val; 185 186 if (physical) 187 val = get_el0(cntp_ctl); 188 else 189 val = get_el0(cntv_ctl); 190 191 return (val); 192 } 193 194 static void 195 setup_user_access(void *arg __unused) 196 { 197 uint32_t cntkctl; 198 199 cntkctl = get_el1(cntkctl); 200 cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN | 201 GT_CNTKCTL_EVNTEN); 202 if (arm_tmr_sc->physical) { 203 cntkctl |= GT_CNTKCTL_PL0PCTEN; 204 cntkctl &= ~GT_CNTKCTL_PL0VCTEN; 205 } else { 206 cntkctl |= GT_CNTKCTL_PL0VCTEN; 207 cntkctl &= ~GT_CNTKCTL_PL0PCTEN; 208 } 209 set_el1(cntkctl, cntkctl); 210 isb(); 211 } 212 213 static void 214 tmr_setup_user_access(void *arg __unused) 215 { 216 217 if (arm_tmr_sc != NULL) 218 smp_rendezvous(NULL, setup_user_access, NULL, NULL); 219 } 220 SYSINIT(tmr_ua, SI_SUB_SMP, SI_ORDER_SECOND, tmr_setup_user_access, NULL); 221 222 static unsigned 223 arm_tmr_get_timecount(struct timecounter *tc) 224 { 225 226 return (get_cntxct(arm_tmr_sc->physical)); 227 } 228 229 static int 230 arm_tmr_start(struct eventtimer *et, sbintime_t first, 231 sbintime_t period __unused) 232 { 233 struct arm_tmr_softc *sc; 234 int counts, ctrl; 235 236 sc = (struct arm_tmr_softc *)et->et_priv; 237 238 if (first != 0) { 239 counts = ((uint32_t)et->et_frequency * first) >> 32; 240 ctrl = get_ctrl(sc->physical); 241 ctrl &= ~GT_CTRL_INT_MASK; 242 ctrl |= GT_CTRL_ENABLE; 243 set_tval(counts, sc->physical); 244 set_ctrl(ctrl, sc->physical); 245 return (0); 246 } 247 248 return (EINVAL); 249 250 } 251 252 static int 253 arm_tmr_stop(struct eventtimer *et) 254 { 255 struct arm_tmr_softc *sc; 256 int ctrl; 257 258 sc = (struct arm_tmr_softc *)et->et_priv; 259 260 ctrl = get_ctrl(sc->physical); 261 ctrl &= ~GT_CTRL_ENABLE; 262 set_ctrl(ctrl, sc->physical); 263 264 return (0); 265 } 266 267 static int 268 arm_tmr_intr(void *arg) 269 { 270 struct arm_tmr_softc *sc; 271 int ctrl; 272 273 sc = (struct arm_tmr_softc *)arg; 274 ctrl = get_ctrl(sc->physical); 275 if (ctrl & GT_CTRL_INT_STAT) { 276 ctrl |= GT_CTRL_INT_MASK; 277 set_ctrl(ctrl, sc->physical); 278 } 279 280 if (sc->et.et_active) 281 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 282 283 return (FILTER_HANDLED); 284 } 285 286 #ifdef FDT 287 static int 288 arm_tmr_fdt_probe(device_t dev) 289 { 290 291 if (!ofw_bus_status_okay(dev)) 292 return (ENXIO); 293 294 if (ofw_bus_is_compatible(dev, "arm,armv7-timer")) { 295 device_set_desc(dev, "ARMv7 Generic Timer"); 296 return (BUS_PROBE_DEFAULT); 297 } else if (ofw_bus_is_compatible(dev, "arm,armv8-timer")) { 298 device_set_desc(dev, "ARMv8 Generic Timer"); 299 return (BUS_PROBE_DEFAULT); 300 } 301 302 return (ENXIO); 303 } 304 #endif 305 306 #ifdef DEV_ACPI 307 static void 308 arm_tmr_acpi_identify(driver_t *driver, device_t parent) 309 { 310 ACPI_TABLE_GTDT *gtdt; 311 vm_paddr_t physaddr; 312 device_t dev; 313 314 physaddr = acpi_find_table(ACPI_SIG_GTDT); 315 if (physaddr == 0) 316 return; 317 318 gtdt = acpi_map_table(physaddr, ACPI_SIG_GTDT); 319 if (gtdt == NULL) { 320 device_printf(parent, "gic: Unable to map the GTDT\n"); 321 return; 322 } 323 324 dev = BUS_ADD_CHILD(parent, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE, 325 "generic_timer", -1); 326 if (dev == NULL) { 327 device_printf(parent, "add gic child failed\n"); 328 goto out; 329 } 330 331 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 0, 332 gtdt->SecureEl1Interrupt, 1); 333 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 1, 334 gtdt->NonSecureEl1Interrupt, 1); 335 BUS_SET_RESOURCE(parent, dev, SYS_RES_IRQ, 2, 336 gtdt->VirtualTimerInterrupt, 1); 337 338 out: 339 acpi_unmap_table(gtdt); 340 } 341 342 static int 343 arm_tmr_acpi_probe(device_t dev) 344 { 345 346 device_set_desc(dev, "ARM Generic Timer"); 347 return (BUS_PROBE_NOWILDCARD); 348 } 349 #endif 350 351 352 static int 353 arm_tmr_attach(device_t dev) 354 { 355 struct arm_tmr_softc *sc; 356 #ifdef FDT 357 phandle_t node; 358 pcell_t clock; 359 #endif 360 int error; 361 int i; 362 363 sc = device_get_softc(dev); 364 if (arm_tmr_sc) 365 return (ENXIO); 366 367 #ifdef FDT 368 /* Get the base clock frequency */ 369 node = ofw_bus_get_node(dev); 370 if (node > 0) { 371 error = OF_getencprop(node, "clock-frequency", &clock, 372 sizeof(clock)); 373 if (error > 0) 374 sc->clkfreq = clock; 375 } 376 #endif 377 378 if (sc->clkfreq == 0) { 379 /* Try to get clock frequency from timer */ 380 sc->clkfreq = get_freq(); 381 } 382 383 if (sc->clkfreq == 0) { 384 device_printf(dev, "No clock frequency specified\n"); 385 return (ENXIO); 386 } 387 388 if (bus_alloc_resources(dev, timer_spec, sc->res)) { 389 device_printf(dev, "could not allocate resources\n"); 390 return (ENXIO); 391 } 392 393 #ifdef __arm__ 394 sc->physical = true; 395 #else /* __aarch64__ */ 396 /* If we do not have a virtual timer use the physical. */ 397 sc->physical = (sc->res[2] == NULL) ? true : false; 398 #endif 399 400 arm_tmr_sc = sc; 401 402 /* Setup secure, non-secure and virtual IRQs handler */ 403 for (i = 0; i < 3; i++) { 404 /* If we do not have the interrupt, skip it. */ 405 if (sc->res[i] == NULL) 406 continue; 407 error = bus_setup_intr(dev, sc->res[i], INTR_TYPE_CLK, 408 arm_tmr_intr, NULL, sc, &sc->ihl[i]); 409 if (error) { 410 device_printf(dev, "Unable to alloc int resource.\n"); 411 return (ENXIO); 412 } 413 } 414 415 arm_tmr_timecount.tc_frequency = sc->clkfreq; 416 tc_init(&arm_tmr_timecount); 417 418 sc->et.et_name = "ARM MPCore Eventtimer"; 419 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 420 sc->et.et_quality = 1000; 421 422 sc->et.et_frequency = sc->clkfreq; 423 sc->et.et_min_period = (0x00000010LLU << 32) / sc->et.et_frequency; 424 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 425 sc->et.et_start = arm_tmr_start; 426 sc->et.et_stop = arm_tmr_stop; 427 sc->et.et_priv = sc; 428 et_register(&sc->et); 429 430 #if defined(__arm__) 431 arm_set_delay(arm_tmr_do_delay, sc); 432 #endif 433 434 return (0); 435 } 436 437 #ifdef FDT 438 static device_method_t arm_tmr_fdt_methods[] = { 439 DEVMETHOD(device_probe, arm_tmr_fdt_probe), 440 DEVMETHOD(device_attach, arm_tmr_attach), 441 { 0, 0 } 442 }; 443 444 static driver_t arm_tmr_fdt_driver = { 445 "generic_timer", 446 arm_tmr_fdt_methods, 447 sizeof(struct arm_tmr_softc), 448 }; 449 450 static devclass_t arm_tmr_fdt_devclass; 451 452 EARLY_DRIVER_MODULE(timer, simplebus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass, 453 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 454 EARLY_DRIVER_MODULE(timer, ofwbus, arm_tmr_fdt_driver, arm_tmr_fdt_devclass, 455 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 456 #endif 457 458 #ifdef DEV_ACPI 459 static device_method_t arm_tmr_acpi_methods[] = { 460 DEVMETHOD(device_identify, arm_tmr_acpi_identify), 461 DEVMETHOD(device_probe, arm_tmr_acpi_probe), 462 DEVMETHOD(device_attach, arm_tmr_attach), 463 { 0, 0 } 464 }; 465 466 static driver_t arm_tmr_acpi_driver = { 467 "generic_timer", 468 arm_tmr_acpi_methods, 469 sizeof(struct arm_tmr_softc), 470 }; 471 472 static devclass_t arm_tmr_acpi_devclass; 473 474 EARLY_DRIVER_MODULE(timer, acpi, arm_tmr_acpi_driver, arm_tmr_acpi_devclass, 475 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 476 #endif 477 478 static void 479 arm_tmr_do_delay(int usec, void *arg) 480 { 481 struct arm_tmr_softc *sc = arg; 482 int32_t counts, counts_per_usec; 483 uint32_t first, last; 484 485 /* Get the number of times to count */ 486 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1); 487 488 /* 489 * Clamp the timeout at a maximum value (about 32 seconds with 490 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 491 * near that length of time and if they are, they should be hung 492 * out to dry. 493 */ 494 if (usec >= (0x80000000U / counts_per_usec)) 495 counts = (0x80000000U / counts_per_usec) - 1; 496 else 497 counts = usec * counts_per_usec; 498 499 first = get_cntxct(sc->physical); 500 501 while (counts > 0) { 502 last = get_cntxct(sc->physical); 503 counts -= (int32_t)(last - first); 504 first = last; 505 } 506 } 507 508 #if defined(__aarch64__) 509 void 510 DELAY(int usec) 511 { 512 int32_t counts; 513 514 /* 515 * Check the timers are setup, if not just 516 * use a for loop for the meantime 517 */ 518 if (arm_tmr_sc == NULL) { 519 for (; usec > 0; usec--) 520 for (counts = 200; counts > 0; counts--) 521 /* 522 * Prevent the compiler from optimizing 523 * out the loop 524 */ 525 cpufunc_nullop(); 526 } else 527 arm_tmr_do_delay(usec, arm_tmr_sc); 528 } 529 #endif 530 531 static uint32_t 532 arm_tmr_fill_vdso_timehands(struct vdso_timehands *vdso_th, 533 struct timecounter *tc) 534 { 535 536 vdso_th->th_algo = VDSO_TH_ALGO_ARM_GENTIM; 537 vdso_th->th_physical = arm_tmr_sc->physical; 538 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 539 return (1); 540 } 541