1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 #include "opt_ddb.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/proc.h> 37 #include <sys/pcpu.h> 38 #include <sys/sched.h> 39 #include <sys/smp.h> 40 #include <sys/ktr.h> 41 #include <sys/malloc.h> 42 43 #include <vm/vm.h> 44 #include <vm/vm_extern.h> 45 #include <vm/vm_kern.h> 46 #include <vm/pmap.h> 47 48 #include <machine/armreg.h> 49 #include <machine/cpu.h> 50 #include <machine/cpufunc.h> 51 #include <machine/debug_monitor.h> 52 #include <machine/smp.h> 53 #include <machine/pcb.h> 54 #include <machine/intr.h> 55 #include <machine/vmparam.h> 56 #ifdef VFP 57 #include <machine/vfp.h> 58 #endif 59 #ifdef CPU_MV_PJ4B 60 #include <arm/mv/mvwin.h> 61 #endif 62 63 /* used to hold the AP's until we are ready to release them */ 64 struct mtx ap_boot_mtx; 65 66 /* # of Applications processors */ 67 volatile int mp_naps; 68 69 /* Set to 1 once we're ready to let the APs out of the pen. */ 70 volatile int aps_ready = 0; 71 72 void set_stackptrs(int cpu); 73 74 /* Temporary variables for init_secondary() */ 75 void *dpcpu[MAXCPU - 1]; 76 77 /* Determine if we running MP machine */ 78 int 79 cpu_mp_probe(void) 80 { 81 82 KASSERT(mp_ncpus != 0, ("cpu_mp_probe: mp_ncpus is unset")); 83 84 CPU_SETOF(0, &all_cpus); 85 86 return (mp_ncpus > 1); 87 } 88 89 /* Start Application Processor via platform specific function */ 90 static int 91 check_ap(void) 92 { 93 uint32_t ms; 94 95 for (ms = 0; ms < 2000; ++ms) { 96 if ((mp_naps + 1) == mp_ncpus) 97 return (0); /* success */ 98 else 99 DELAY(1000); 100 } 101 102 return (-2); 103 } 104 105 /* Initialize and fire up non-boot processors */ 106 void 107 cpu_mp_start(void) 108 { 109 int error, i; 110 111 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 112 113 /* Reserve memory for application processors */ 114 for(i = 0; i < (mp_ncpus - 1); i++) 115 dpcpu[i] = kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO); 116 117 dcache_wbinv_poc_all(); 118 119 /* Initialize boot code and start up processors */ 120 platform_mp_start_ap(); 121 122 /* Check if ap's started properly */ 123 error = check_ap(); 124 if (error) 125 printf("WARNING: Some AP's failed to start\n"); 126 else 127 for (i = 1; i < mp_ncpus; i++) 128 CPU_SET(i, &all_cpus); 129 } 130 131 /* Introduce rest of cores to the world */ 132 void 133 cpu_mp_announce(void) 134 { 135 136 } 137 138 void 139 init_secondary(int cpu) 140 { 141 struct pcpu *pc; 142 uint32_t loop_counter; 143 144 pmap_set_tex(); 145 cpuinfo_reinit_mmu(pmap_kern_ttb); 146 cpu_setup(); 147 148 /* Provide stack pointers for other processor modes. */ 149 set_stackptrs(cpu); 150 151 enable_interrupts(PSR_A); 152 pc = &__pcpu[cpu]; 153 154 /* 155 * pcpu_init() updates queue, so it should not be executed in parallel 156 * on several cores 157 */ 158 while(mp_naps < (cpu - 1)) 159 ; 160 161 pcpu_init(pc, cpu, sizeof(struct pcpu)); 162 pc->pc_mpidr = cp15_mpidr_get() & 0xFFFFFF; 163 dpcpu_init(dpcpu[cpu - 1], cpu); 164 #if defined(DDB) 165 dbg_monitor_init_secondary(); 166 #endif 167 /* Signal our startup to BSP */ 168 atomic_add_rel_32(&mp_naps, 1); 169 170 /* Spin until the BSP releases the APs */ 171 while (!atomic_load_acq_int(&aps_ready)) { 172 #if __ARM_ARCH >= 7 173 __asm __volatile("wfe"); 174 #endif 175 } 176 177 /* Initialize curthread */ 178 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 179 pc->pc_curthread = pc->pc_idlethread; 180 pc->pc_curpcb = pc->pc_idlethread->td_pcb; 181 set_curthread(pc->pc_idlethread); 182 schedinit_ap(); 183 #ifdef VFP 184 vfp_init(); 185 #endif 186 187 /* Configure the interrupt controller */ 188 intr_pic_init_secondary(); 189 190 /* Apply possible BP hardening */ 191 cpuinfo_init_bp_hardening(); 192 193 mtx_lock_spin(&ap_boot_mtx); 194 195 atomic_add_rel_32(&smp_cpus, 1); 196 197 if (smp_cpus == mp_ncpus) { 198 /* enable IPI's, tlb shootdown, freezes etc */ 199 atomic_store_rel_int(&smp_started, 1); 200 } 201 202 mtx_unlock_spin(&ap_boot_mtx); 203 204 loop_counter = 0; 205 while (smp_started == 0) { 206 DELAY(100); 207 loop_counter++; 208 if (loop_counter == 1000) 209 CTR0(KTR_SMP, "AP still wait for smp_started"); 210 } 211 /* Start per-CPU event timers. */ 212 cpu_initclocks_ap(); 213 214 CTR0(KTR_SMP, "go into scheduler"); 215 216 /* Enter the scheduler */ 217 sched_ap_entry(); 218 219 panic("scheduler returned us to %s", __func__); 220 /* NOTREACHED */ 221 } 222 223 static void 224 ipi_rendezvous(void *dummy __unused) 225 { 226 227 CTR0(KTR_SMP, "IPI_RENDEZVOUS"); 228 smp_rendezvous_action(); 229 } 230 231 static void 232 ipi_ast(void *dummy __unused) 233 { 234 235 CTR0(KTR_SMP, "IPI_AST"); 236 } 237 238 static void 239 ipi_stop(void *dummy __unused) 240 { 241 u_int cpu; 242 243 /* 244 * IPI_STOP_HARD is mapped to IPI_STOP. 245 */ 246 CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); 247 248 cpu = PCPU_GET(cpuid); 249 savectx(&stoppcbs[cpu]); 250 251 /* 252 * CPUs are stopped when entering the debugger and at 253 * system shutdown, both events which can precede a 254 * panic dump. For the dump to be correct, all caches 255 * must be flushed and invalidated, but on ARM there's 256 * no way to broadcast a wbinv_all to other cores. 257 * Instead, we have each core do the local wbinv_all as 258 * part of stopping the core. The core requesting the 259 * stop will do the l2 cache flush after all other cores 260 * have done their l1 flushes and stopped. 261 */ 262 dcache_wbinv_poc_all(); 263 264 /* Indicate we are stopped */ 265 CPU_SET_ATOMIC(cpu, &stopped_cpus); 266 267 /* Wait for restart */ 268 while (!CPU_ISSET(cpu, &started_cpus)) 269 cpu_spinwait(); 270 271 CPU_CLR_ATOMIC(cpu, &started_cpus); 272 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 273 #ifdef DDB 274 dbg_resume_dbreg(); 275 #endif 276 CTR0(KTR_SMP, "IPI_STOP (restart)"); 277 } 278 279 static void 280 ipi_preempt(void *arg) 281 { 282 283 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); 284 sched_preempt(curthread); 285 } 286 287 static void 288 ipi_hardclock(void *arg) 289 { 290 291 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); 292 hardclockintr(); 293 } 294 295 static void 296 release_aps(void *dummy __unused) 297 { 298 uint32_t loop_counter; 299 300 if (mp_ncpus == 1) 301 return; 302 303 intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL); 304 intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL); 305 intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL); 306 intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL); 307 intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL); 308 309 atomic_store_rel_int(&aps_ready, 1); 310 /* Wake the other threads up */ 311 dsb(); 312 sev(); 313 314 printf("Release APs\n"); 315 316 for (loop_counter = 0; loop_counter < 2000; loop_counter++) { 317 if (smp_started) 318 return; 319 DELAY(1000); 320 } 321 printf("AP's not started\n"); 322 } 323 324 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 325 326 struct cpu_group * 327 cpu_topo(void) 328 { 329 330 return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0)); 331 } 332 333 void 334 cpu_mp_setmaxid(void) 335 { 336 337 platform_mp_setmaxid(); 338 } 339 340 /* Sending IPI */ 341 void 342 ipi_all_but_self(u_int ipi) 343 { 344 cpuset_t other_cpus; 345 346 other_cpus = all_cpus; 347 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 348 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 349 intr_ipi_send(other_cpus, ipi); 350 } 351 352 void 353 ipi_cpu(int cpu, u_int ipi) 354 { 355 cpuset_t cpus; 356 357 CPU_ZERO(&cpus); 358 CPU_SET(cpu, &cpus); 359 360 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi); 361 intr_ipi_send(cpus, ipi); 362 } 363 364 void 365 ipi_selected(cpuset_t cpus, u_int ipi) 366 { 367 368 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 369 intr_ipi_send(cpus, ipi); 370 } 371