1 /* 2 * Copyright (c) 2013 Daisuke Aoyama <aoyama@peach.ne.jp> 3 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@bluezbox.com> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/queue.h> 40 #include <sys/resource.h> 41 #include <sys/rman.h> 42 43 #include <dev/ofw/openfirm.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 #include <machine/bus.h> 50 51 #include "bcm2835_dma.h" 52 #include "bcm2835_vcbus.h" 53 54 #define MAX_REG 9 55 56 /* private flags */ 57 #define BCM_DMA_CH_USED 0x00000001 58 #define BCM_DMA_CH_FREE 0x40000000 59 #define BCM_DMA_CH_UNMAP 0x80000000 60 61 /* Register Map (4.2.1.2) */ 62 #define BCM_DMA_CS(n) (0x100*(n) + 0x00) 63 #define CS_ACTIVE (1 << 0) 64 #define CS_END (1 << 1) 65 #define CS_INT (1 << 2) 66 #define CS_DREQ (1 << 3) 67 #define CS_ISPAUSED (1 << 4) 68 #define CS_ISHELD (1 << 5) 69 #define CS_ISWAIT (1 << 6) 70 #define CS_ERR (1 << 8) 71 #define CS_WAITWRT (1 << 28) 72 #define CS_DISDBG (1 << 29) 73 #define CS_ABORT (1 << 30) 74 #define CS_RESET (1U << 31) 75 #define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04) 76 #define BCM_DMA_INFO(n) (0x100*(n) + 0x08) 77 #define INFO_INT_EN (1 << 0) 78 #define INFO_TDMODE (1 << 1) 79 #define INFO_WAIT_RESP (1 << 3) 80 #define INFO_D_INC (1 << 4) 81 #define INFO_D_WIDTH (1 << 5) 82 #define INFO_D_DREQ (1 << 6) 83 #define INFO_S_INC (1 << 8) 84 #define INFO_S_WIDTH (1 << 9) 85 #define INFO_S_DREQ (1 << 10) 86 #define INFO_WAITS_SHIFT (21) 87 #define INFO_PERMAP_SHIFT (16) 88 #define INFO_PERMAP_MASK (0x1f << INFO_PERMAP_SHIFT) 89 90 #define BCM_DMA_SRC(n) (0x100*(n) + 0x0C) 91 #define BCM_DMA_DST(n) (0x100*(n) + 0x10) 92 #define BCM_DMA_LEN(n) (0x100*(n) + 0x14) 93 #define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18) 94 #define BCM_DMA_CBNEXT(n) (0x100*(n) + 0x1C) 95 #define BCM_DMA_DEBUG(n) (0x100*(n) + 0x20) 96 #define DEBUG_ERROR_MASK (7) 97 98 #define BCM_DMA_INT_STATUS 0xfe0 99 #define BCM_DMA_ENABLE 0xff0 100 101 /* relative offset from BCM_VC_DMA0_BASE (p.39) */ 102 #define BCM_DMA_CH(n) (0x100*(n)) 103 104 /* channels used by GPU */ 105 #define BCM_DMA_CH_BULK 0 106 #define BCM_DMA_CH_FAST1 2 107 #define BCM_DMA_CH_FAST2 3 108 109 #define BCM_DMA_CH_GPU_MASK ((1 << BCM_DMA_CH_BULK) | \ 110 (1 << BCM_DMA_CH_FAST1) | \ 111 (1 << BCM_DMA_CH_FAST2)) 112 113 /* DMA Control Block - 256bit aligned (p.40) */ 114 struct bcm_dma_cb { 115 uint32_t info; /* Transfer Information */ 116 uint32_t src; /* Source Address */ 117 uint32_t dst; /* Destination Address */ 118 uint32_t len; /* Transfer Length */ 119 uint32_t stride; /* 2D Mode Stride */ 120 uint32_t next; /* Next Control Block Address */ 121 uint32_t rsvd1; /* Reserved */ 122 uint32_t rsvd2; /* Reserved */ 123 }; 124 125 #ifdef DEBUG 126 static void bcm_dma_cb_dump(struct bcm_dma_cb *cb); 127 static void bcm_dma_reg_dump(int ch); 128 #endif 129 130 /* DMA channel private info */ 131 struct bcm_dma_ch { 132 int ch; 133 uint32_t flags; 134 struct bcm_dma_cb * cb; 135 uint32_t vc_cb; 136 bus_dmamap_t dma_map; 137 void (*intr_func)(int, void *); 138 void * intr_arg; 139 }; 140 141 struct bcm_dma_softc { 142 device_t sc_dev; 143 struct mtx sc_mtx; 144 struct resource * sc_mem; 145 struct resource * sc_irq[BCM_DMA_CH_MAX]; 146 void * sc_intrhand[BCM_DMA_CH_MAX]; 147 struct bcm_dma_ch sc_dma_ch[BCM_DMA_CH_MAX]; 148 bus_dma_tag_t sc_dma_tag; 149 }; 150 151 static struct bcm_dma_softc *bcm_dma_sc = NULL; 152 static uint32_t bcm_dma_channel_mask; 153 154 static struct ofw_compat_data compat_data[] = { 155 {"broadcom,bcm2835-dma", 1}, 156 {"brcm,bcm2835-dma", 1}, 157 {NULL, 0} 158 }; 159 160 static void 161 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs, 162 int nseg, int err) 163 { 164 bus_addr_t *addr; 165 166 if (err) 167 return; 168 169 addr = (bus_addr_t*)arg; 170 *addr = PHYS_TO_VCBUS(segs[0].ds_addr); 171 } 172 173 static void 174 bcm_dma_reset(device_t dev, int ch) 175 { 176 struct bcm_dma_softc *sc = device_get_softc(dev); 177 struct bcm_dma_cb *cb; 178 uint32_t cs; 179 int count; 180 181 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 182 return; 183 184 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); 185 186 if (cs & CS_ACTIVE) { 187 /* pause current task */ 188 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0); 189 190 count = 1000; 191 do { 192 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); 193 } while (!(cs & CS_ISPAUSED) && (count-- > 0)); 194 195 if (!(cs & CS_ISPAUSED)) { 196 device_printf(dev, 197 "Can't abort DMA transfer at channel %d\n", ch); 198 } 199 200 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0); 201 202 /* Complete everything, clear interrupt */ 203 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 204 CS_ABORT | CS_INT | CS_END| CS_ACTIVE); 205 } 206 207 /* clear control blocks */ 208 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0); 209 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0); 210 211 /* Reset control block */ 212 cb = sc->sc_dma_ch[ch].cb; 213 bzero(cb, sizeof(*cb)); 214 cb->info = INFO_WAIT_RESP; 215 } 216 217 static int 218 bcm_dma_init(device_t dev) 219 { 220 struct bcm_dma_softc *sc = device_get_softc(dev); 221 uint32_t reg; 222 struct bcm_dma_ch *ch; 223 void *cb_virt; 224 vm_paddr_t cb_phys; 225 int err; 226 int i; 227 228 /* 229 * Only channels set in bcm_dma_channel_mask can be controlled by us. 230 * The others are out of our control as well as the corresponding bits 231 * in both BCM_DMA_ENABLE and BCM_DMA_INT_STATUS global registers. As 232 * these registers are RW ones, there is no safe way how to write only 233 * the bits which can be controlled by us. 234 * 235 * Fortunately, after reset, all channels are enabled in BCM_DMA_ENABLE 236 * register and all statuses are cleared in BCM_DMA_INT_STATUS one. 237 * Not touching these registers is a trade off between correct 238 * initialization which does not count on anything and not messing up 239 * something we have no control over. 240 */ 241 reg = bus_read_4(sc->sc_mem, BCM_DMA_ENABLE); 242 if ((reg & bcm_dma_channel_mask) != bcm_dma_channel_mask) 243 device_printf(dev, "channels are not enabled\n"); 244 reg = bus_read_4(sc->sc_mem, BCM_DMA_INT_STATUS); 245 if ((reg & bcm_dma_channel_mask) != 0) 246 device_printf(dev, "statuses are not cleared\n"); 247 248 /* Allocate DMA chunks control blocks */ 249 /* p.40 of spec - control block should be 32-bit aligned */ 250 err = bus_dma_tag_create(bus_get_dma_tag(dev), 251 1, 0, BUS_SPACE_MAXADDR_32BIT, 252 BUS_SPACE_MAXADDR, NULL, NULL, 253 sizeof(struct bcm_dma_cb), 1, 254 sizeof(struct bcm_dma_cb), 255 BUS_DMA_ALLOCNOW, NULL, NULL, 256 &sc->sc_dma_tag); 257 258 if (err) { 259 device_printf(dev, "failed allocate DMA tag\n"); 260 return (err); 261 } 262 263 /* setup initial settings */ 264 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 265 ch = &sc->sc_dma_ch[i]; 266 267 bzero(ch, sizeof(struct bcm_dma_ch)); 268 ch->ch = i; 269 ch->flags = BCM_DMA_CH_UNMAP; 270 271 if ((bcm_dma_channel_mask & (1 << i)) == 0) 272 continue; 273 274 err = bus_dmamem_alloc(sc->sc_dma_tag, &cb_virt, 275 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 276 &ch->dma_map); 277 if (err) { 278 device_printf(dev, "cannot allocate DMA memory\n"); 279 break; 280 } 281 282 /* 283 * Least alignment for busdma-allocated stuff is cache 284 * line size, so just make sure nothing stupid happened 285 * and we got properly aligned address 286 */ 287 if ((uintptr_t)cb_virt & 0x1f) { 288 device_printf(dev, 289 "DMA address is not 32-bytes aligned: %p\n", 290 (void*)cb_virt); 291 break; 292 } 293 294 err = bus_dmamap_load(sc->sc_dma_tag, ch->dma_map, cb_virt, 295 sizeof(struct bcm_dma_cb), bcm_dmamap_cb, &cb_phys, 296 BUS_DMA_WAITOK); 297 if (err) { 298 device_printf(dev, "cannot load DMA memory\n"); 299 break; 300 } 301 302 ch->cb = cb_virt; 303 ch->vc_cb = cb_phys; 304 ch->flags = BCM_DMA_CH_FREE; 305 ch->cb->info = INFO_WAIT_RESP; 306 307 /* reset DMA engine */ 308 bus_write_4(sc->sc_mem, BCM_DMA_CS(i), CS_RESET); 309 } 310 311 return (0); 312 } 313 314 /* 315 * Allocate DMA channel for further use, returns channel # or 316 * BCM_DMA_CH_INVALID 317 */ 318 int 319 bcm_dma_allocate(int req_ch) 320 { 321 struct bcm_dma_softc *sc = bcm_dma_sc; 322 int ch = BCM_DMA_CH_INVALID; 323 int i; 324 325 if (req_ch >= BCM_DMA_CH_MAX) 326 return (BCM_DMA_CH_INVALID); 327 328 /* Auto(req_ch < 0) or CH specified */ 329 mtx_lock(&sc->sc_mtx); 330 331 if (req_ch < 0) { 332 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 333 if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE) { 334 ch = i; 335 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE; 336 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED; 337 break; 338 } 339 } 340 } 341 else { 342 if (sc->sc_dma_ch[req_ch].flags & BCM_DMA_CH_FREE) { 343 ch = req_ch; 344 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE; 345 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED; 346 } 347 } 348 349 mtx_unlock(&sc->sc_mtx); 350 return (ch); 351 } 352 353 /* 354 * Frees allocated channel. Returns 0 on success, -1 otherwise 355 */ 356 int 357 bcm_dma_free(int ch) 358 { 359 struct bcm_dma_softc *sc = bcm_dma_sc; 360 361 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 362 return (-1); 363 364 mtx_lock(&sc->sc_mtx); 365 if (sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED) { 366 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_FREE; 367 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_USED; 368 sc->sc_dma_ch[ch].intr_func = NULL; 369 sc->sc_dma_ch[ch].intr_arg = NULL; 370 371 /* reset DMA engine */ 372 bcm_dma_reset(sc->sc_dev, ch); 373 } 374 375 mtx_unlock(&sc->sc_mtx); 376 return (0); 377 } 378 379 /* 380 * Assign handler function for channel interrupt 381 * Returns 0 on success, -1 otherwise 382 */ 383 int 384 bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg) 385 { 386 struct bcm_dma_softc *sc = bcm_dma_sc; 387 struct bcm_dma_cb *cb; 388 389 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 390 return (-1); 391 392 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 393 return (-1); 394 395 sc->sc_dma_ch[ch].intr_func = func; 396 sc->sc_dma_ch[ch].intr_arg = arg; 397 cb = sc->sc_dma_ch[ch].cb; 398 cb->info |= INFO_INT_EN; 399 400 return (0); 401 } 402 403 /* 404 * Setup DMA source parameters 405 * ch - channel number 406 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if 407 * source is physical memory 408 * inc_addr - BCM_DMA_INC_ADDR if source address 409 * should be increased after each access or 410 * BCM_DMA_SAME_ADDR if address should remain 411 * the same 412 * width - size of read operation, BCM_DMA_32BIT 413 * for 32bit bursts, BCM_DMA_128BIT for 128 bits 414 * 415 * Returns 0 on success, -1 otherwise 416 */ 417 int 418 bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width) 419 { 420 struct bcm_dma_softc *sc = bcm_dma_sc; 421 uint32_t info; 422 423 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 424 return (-1); 425 426 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 427 return (-1); 428 429 info = sc->sc_dma_ch[ch].cb->info; 430 info &= ~INFO_PERMAP_MASK; 431 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; 432 433 if (dreq) 434 info |= INFO_S_DREQ; 435 else 436 info &= ~INFO_S_DREQ; 437 438 if (width == BCM_DMA_128BIT) 439 info |= INFO_S_WIDTH; 440 else 441 info &= ~INFO_S_WIDTH; 442 443 if (inc_addr == BCM_DMA_INC_ADDR) 444 info |= INFO_S_INC; 445 else 446 info &= ~INFO_S_INC; 447 448 sc->sc_dma_ch[ch].cb->info = info; 449 450 return (0); 451 } 452 453 /* 454 * Setup DMA destination parameters 455 * ch - channel number 456 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if 457 * destination is physical memory 458 * inc_addr - BCM_DMA_INC_ADDR if source address 459 * should be increased after each access or 460 * BCM_DMA_SAME_ADDR if address should remain 461 * the same 462 * width - size of write operation, BCM_DMA_32BIT 463 * for 32bit bursts, BCM_DMA_128BIT for 128 bits 464 * 465 * Returns 0 on success, -1 otherwise 466 */ 467 int 468 bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width) 469 { 470 struct bcm_dma_softc *sc = bcm_dma_sc; 471 uint32_t info; 472 473 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 474 return (-1); 475 476 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 477 return (-1); 478 479 info = sc->sc_dma_ch[ch].cb->info; 480 info &= ~INFO_PERMAP_MASK; 481 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; 482 483 if (dreq) 484 info |= INFO_D_DREQ; 485 else 486 info &= ~INFO_D_DREQ; 487 488 if (width == BCM_DMA_128BIT) 489 info |= INFO_D_WIDTH; 490 else 491 info &= ~INFO_D_WIDTH; 492 493 if (inc_addr == BCM_DMA_INC_ADDR) 494 info |= INFO_D_INC; 495 else 496 info &= ~INFO_D_INC; 497 498 sc->sc_dma_ch[ch].cb->info = info; 499 500 return (0); 501 } 502 503 #ifdef DEBUG 504 void 505 bcm_dma_cb_dump(struct bcm_dma_cb *cb) 506 { 507 508 printf("DMA CB "); 509 printf("INFO: %8.8x ", cb->info); 510 printf("SRC: %8.8x ", cb->src); 511 printf("DST: %8.8x ", cb->dst); 512 printf("LEN: %8.8x ", cb->len); 513 printf("\n"); 514 printf("STRIDE: %8.8x ", cb->stride); 515 printf("NEXT: %8.8x ", cb->next); 516 printf("RSVD1: %8.8x ", cb->rsvd1); 517 printf("RSVD2: %8.8x ", cb->rsvd2); 518 printf("\n"); 519 } 520 521 void 522 bcm_dma_reg_dump(int ch) 523 { 524 struct bcm_dma_softc *sc = bcm_dma_sc; 525 int i; 526 uint32_t reg; 527 528 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 529 return; 530 531 printf("DMA%d: ", ch); 532 for (i = 0; i < MAX_REG; i++) { 533 reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4); 534 printf("%8.8x ", reg); 535 } 536 printf("\n"); 537 } 538 #endif 539 540 /* 541 * Start DMA transaction 542 * ch - channel number 543 * src, dst - source and destination address in 544 * ARM physical memory address space. 545 * len - amount of bytes to be transferred 546 * 547 * Returns 0 on success, -1 otherwise 548 */ 549 int 550 bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len) 551 { 552 struct bcm_dma_softc *sc = bcm_dma_sc; 553 struct bcm_dma_cb *cb; 554 555 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 556 return (-1); 557 558 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 559 return (-1); 560 561 cb = sc->sc_dma_ch[ch].cb; 562 if (BCM2835_ARM_IS_IO(src)) 563 cb->src = IO_TO_VCBUS(src); 564 else 565 cb->src = PHYS_TO_VCBUS(src); 566 if (BCM2835_ARM_IS_IO(dst)) 567 cb->dst = IO_TO_VCBUS(dst); 568 else 569 cb->dst = PHYS_TO_VCBUS(dst); 570 cb->len = len; 571 572 bus_dmamap_sync(sc->sc_dma_tag, 573 sc->sc_dma_ch[ch].dma_map, BUS_DMASYNC_PREWRITE); 574 575 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 576 sc->sc_dma_ch[ch].vc_cb); 577 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE); 578 579 #ifdef DEBUG 580 bcm_dma_cb_dump(sc->sc_dma_ch[ch].cb); 581 bcm_dma_reg_dump(ch); 582 #endif 583 584 return (0); 585 } 586 587 /* 588 * Get length requested for DMA transaction 589 * ch - channel number 590 * 591 * Returns size of transaction, 0 if channel is invalid 592 */ 593 uint32_t 594 bcm_dma_length(int ch) 595 { 596 struct bcm_dma_softc *sc = bcm_dma_sc; 597 struct bcm_dma_cb *cb; 598 599 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 600 return (0); 601 602 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 603 return (0); 604 605 cb = sc->sc_dma_ch[ch].cb; 606 607 return (cb->len); 608 } 609 610 static void 611 bcm_dma_intr(void *arg) 612 { 613 struct bcm_dma_softc *sc = bcm_dma_sc; 614 struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg; 615 uint32_t cs, debug; 616 617 /* my interrupt? */ 618 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch)); 619 620 if (!(cs & (CS_INT | CS_ERR))) { 621 device_printf(sc->sc_dev, 622 "unexpected DMA intr CH=%d, CS=%x\n", ch->ch, cs); 623 return; 624 } 625 626 /* running? */ 627 if (!(ch->flags & BCM_DMA_CH_USED)) { 628 device_printf(sc->sc_dev, 629 "unused DMA intr CH=%d, CS=%x\n", ch->ch, cs); 630 return; 631 } 632 633 if (cs & CS_ERR) { 634 debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch)); 635 device_printf(sc->sc_dev, "DMA error %d on CH%d\n", 636 debug & DEBUG_ERROR_MASK, ch->ch); 637 bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch), 638 debug & DEBUG_ERROR_MASK); 639 bcm_dma_reset(sc->sc_dev, ch->ch); 640 } 641 642 if (cs & CS_INT) { 643 /* acknowledge interrupt */ 644 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch), 645 CS_INT | CS_END); 646 647 /* Prepare for possible access to len field */ 648 bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map, 649 BUS_DMASYNC_POSTWRITE); 650 651 /* save callback function and argument */ 652 if (ch->intr_func) 653 ch->intr_func(ch->ch, ch->intr_arg); 654 } 655 } 656 657 static int 658 bcm_dma_probe(device_t dev) 659 { 660 661 if (!ofw_bus_status_okay(dev)) 662 return (ENXIO); 663 664 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 665 return (ENXIO); 666 667 device_set_desc(dev, "BCM2835 DMA Controller"); 668 return (BUS_PROBE_DEFAULT); 669 } 670 671 static int 672 bcm_dma_attach(device_t dev) 673 { 674 struct bcm_dma_softc *sc = device_get_softc(dev); 675 phandle_t node; 676 int rid, err = 0; 677 int i; 678 679 sc->sc_dev = dev; 680 681 if (bcm_dma_sc) 682 return (ENXIO); 683 684 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 685 sc->sc_irq[i] = NULL; 686 sc->sc_intrhand[i] = NULL; 687 } 688 689 /* Get DMA channel mask. */ 690 node = ofw_bus_get_node(sc->sc_dev); 691 if (OF_getencprop(node, "brcm,dma-channel-mask", &bcm_dma_channel_mask, 692 sizeof(bcm_dma_channel_mask)) == -1 && 693 OF_getencprop(node, "broadcom,channels", &bcm_dma_channel_mask, 694 sizeof(bcm_dma_channel_mask)) == -1) { 695 device_printf(dev, "could not get channel mask property\n"); 696 return (ENXIO); 697 } 698 699 /* Mask out channels used by GPU. */ 700 bcm_dma_channel_mask &= ~BCM_DMA_CH_GPU_MASK; 701 702 /* DMA0 - DMA14 */ 703 rid = 0; 704 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 705 if (sc->sc_mem == NULL) { 706 device_printf(dev, "could not allocate memory resource\n"); 707 return (ENXIO); 708 } 709 710 /* IRQ DMA0 - DMA11 XXX NOT USE DMA12(spurious?) */ 711 for (rid = 0; rid < BCM_DMA_CH_MAX; rid++) { 712 if ((bcm_dma_channel_mask & (1 << rid)) == 0) 713 continue; 714 715 sc->sc_irq[rid] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 716 RF_ACTIVE); 717 if (sc->sc_irq[rid] == NULL) { 718 device_printf(dev, "cannot allocate interrupt\n"); 719 err = ENXIO; 720 goto fail; 721 } 722 if (bus_setup_intr(dev, sc->sc_irq[rid], INTR_TYPE_MISC | INTR_MPSAFE, 723 NULL, bcm_dma_intr, &sc->sc_dma_ch[rid], 724 &sc->sc_intrhand[rid])) { 725 device_printf(dev, "cannot setup interrupt handler\n"); 726 err = ENXIO; 727 goto fail; 728 } 729 } 730 731 mtx_init(&sc->sc_mtx, "bcmdma", "bcmdma", MTX_DEF); 732 bcm_dma_sc = sc; 733 734 err = bcm_dma_init(dev); 735 if (err) 736 goto fail; 737 738 return (err); 739 740 fail: 741 if (sc->sc_mem) 742 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem); 743 744 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 745 if (sc->sc_intrhand[i]) 746 bus_teardown_intr(dev, sc->sc_irq[i], sc->sc_intrhand[i]); 747 if (sc->sc_irq[i]) 748 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq[i]); 749 } 750 751 return (err); 752 } 753 754 static device_method_t bcm_dma_methods[] = { 755 DEVMETHOD(device_probe, bcm_dma_probe), 756 DEVMETHOD(device_attach, bcm_dma_attach), 757 { 0, 0 } 758 }; 759 760 static driver_t bcm_dma_driver = { 761 "bcm_dma", 762 bcm_dma_methods, 763 sizeof(struct bcm_dma_softc), 764 }; 765 766 static devclass_t bcm_dma_devclass; 767 768 DRIVER_MODULE(bcm_dma, simplebus, bcm_dma_driver, bcm_dma_devclass, 0, 0); 769 MODULE_VERSION(bcm_dma, 1); 770