1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/fdt/fdt_common.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/mmc/bridge.h> 49 #include <dev/mmc/mmcreg.h> 50 #include <dev/mmc/mmcbrvar.h> 51 52 #include <dev/sdhci/sdhci.h> 53 #include "sdhci_if.h" 54 55 #include "bcm2835_dma.h" 56 #include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h> 57 #include "bcm2835_vcbus.h" 58 59 #define BCM2835_DEFAULT_SDHCI_FREQ 50 60 61 #define BCM_SDHCI_BUFFER_SIZE 512 62 #define NUM_DMA_SEGS 2 63 64 #ifdef DEBUG 65 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define dprintf(fmt, args...) 69 #endif 70 71 static int bcm2835_sdhci_hs = 1; 72 static int bcm2835_sdhci_pio_mode = 0; 73 74 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 75 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 76 77 struct bcm_sdhci_softc { 78 device_t sc_dev; 79 struct resource * sc_mem_res; 80 struct resource * sc_irq_res; 81 bus_space_tag_t sc_bst; 82 bus_space_handle_t sc_bsh; 83 void * sc_intrhand; 84 struct mmc_request * sc_req; 85 struct sdhci_slot sc_slot; 86 int sc_dma_ch; 87 bus_dma_tag_t sc_dma_tag; 88 bus_dmamap_t sc_dma_map; 89 vm_paddr_t sc_sdhci_buffer_phys; 90 uint32_t cmd_and_mode; 91 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; 92 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; 93 int dmamap_seg_count; 94 int dmamap_seg_index; 95 int dmamap_status; 96 }; 97 98 static int bcm_sdhci_probe(device_t); 99 static int bcm_sdhci_attach(device_t); 100 static int bcm_sdhci_detach(device_t); 101 static void bcm_sdhci_intr(void *); 102 103 static int bcm_sdhci_get_ro(device_t, device_t); 104 static void bcm_sdhci_dma_intr(int ch, void *arg); 105 106 static void 107 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 108 { 109 struct bcm_sdhci_softc *sc = arg; 110 int i; 111 112 sc->dmamap_status = err; 113 sc->dmamap_seg_count = nseg; 114 115 /* Note nseg is guaranteed to be zero if err is non-zero. */ 116 for (i = 0; i < nseg; i++) { 117 sc->dmamap_seg_addrs[i] = segs[i].ds_addr; 118 sc->dmamap_seg_sizes[i] = segs[i].ds_len; 119 } 120 } 121 122 static int 123 bcm_sdhci_probe(device_t dev) 124 { 125 126 if (!ofw_bus_status_okay(dev)) 127 return (ENXIO); 128 129 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 130 return (ENXIO); 131 132 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 133 return (BUS_PROBE_DEFAULT); 134 } 135 136 static int 137 bcm_sdhci_attach(device_t dev) 138 { 139 struct bcm_sdhci_softc *sc = device_get_softc(dev); 140 int rid, err; 141 phandle_t node; 142 pcell_t cell; 143 u_int default_freq; 144 145 sc->sc_dev = dev; 146 sc->sc_req = NULL; 147 148 err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, 149 TRUE); 150 if (err != 0) { 151 if (bootverbose) 152 device_printf(dev, "Unable to enable the power\n"); 153 return (err); 154 } 155 156 default_freq = 0; 157 err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, 158 &default_freq); 159 if (err == 0) { 160 /* Convert to MHz */ 161 default_freq /= 1000000; 162 } 163 if (default_freq == 0) { 164 node = ofw_bus_get_node(sc->sc_dev); 165 if ((OF_getencprop(node, "clock-frequency", &cell, 166 sizeof(cell))) > 0) 167 default_freq = cell / 1000000; 168 } 169 if (default_freq == 0) 170 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 171 172 if (bootverbose) 173 device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); 174 175 rid = 0; 176 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 177 RF_ACTIVE); 178 if (!sc->sc_mem_res) { 179 device_printf(dev, "cannot allocate memory window\n"); 180 err = ENXIO; 181 goto fail; 182 } 183 184 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 185 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 186 187 rid = 0; 188 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 189 RF_ACTIVE); 190 if (!sc->sc_irq_res) { 191 device_printf(dev, "cannot allocate interrupt\n"); 192 err = ENXIO; 193 goto fail; 194 } 195 196 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 197 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { 198 device_printf(dev, "cannot setup interrupt handler\n"); 199 err = ENXIO; 200 goto fail; 201 } 202 203 if (!bcm2835_sdhci_pio_mode) 204 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 205 206 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 207 if (bcm2835_sdhci_hs) 208 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 209 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 210 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 211 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 212 | SDHCI_QUIRK_DONT_SET_HISPD_BIT 213 | SDHCI_QUIRK_MISSING_CAPS; 214 215 sdhci_init_slot(dev, &sc->sc_slot, 0); 216 217 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 218 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 219 goto fail; 220 221 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 222 223 /* Allocate bus_dma resources. */ 224 err = bus_dma_tag_create(bus_get_dma_tag(dev), 225 1, 0, BUS_SPACE_MAXADDR_32BIT, 226 BUS_SPACE_MAXADDR, NULL, NULL, 227 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, 228 BUS_DMA_ALLOCNOW, NULL, NULL, 229 &sc->sc_dma_tag); 230 231 if (err) { 232 device_printf(dev, "failed allocate DMA tag"); 233 goto fail; 234 } 235 236 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 237 if (err) { 238 device_printf(dev, "bus_dmamap_create failed\n"); 239 goto fail; 240 } 241 242 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 243 SDHCI_BUFFER); 244 245 bus_generic_probe(dev); 246 bus_generic_attach(dev); 247 248 sdhci_start_slot(&sc->sc_slot); 249 250 return (0); 251 252 fail: 253 if (sc->sc_intrhand) 254 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 255 if (sc->sc_irq_res) 256 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 257 if (sc->sc_mem_res) 258 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 259 260 return (err); 261 } 262 263 static int 264 bcm_sdhci_detach(device_t dev) 265 { 266 267 return (EBUSY); 268 } 269 270 static void 271 bcm_sdhci_intr(void *arg) 272 { 273 struct bcm_sdhci_softc *sc = arg; 274 275 sdhci_generic_intr(&sc->sc_slot); 276 } 277 278 static int 279 bcm_sdhci_get_ro(device_t bus, device_t child) 280 { 281 282 return (0); 283 } 284 285 static inline uint32_t 286 RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 287 { 288 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 289 return val; 290 } 291 292 static inline void 293 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 294 { 295 296 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 297 /* 298 * The Arasan HC has a bug where it may lose the content of 299 * consecutive writes to registers that are within two SD-card 300 * clock cycles of each other (a clock domain crossing problem). 301 */ 302 if (sc->sc_slot.clock > 0) 303 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 304 } 305 306 static uint8_t 307 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 308 { 309 struct bcm_sdhci_softc *sc = device_get_softc(dev); 310 uint32_t val = RD4(sc, off & ~3); 311 312 return ((val >> (off & 3)*8) & 0xff); 313 } 314 315 static uint16_t 316 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 317 { 318 struct bcm_sdhci_softc *sc = device_get_softc(dev); 319 uint32_t val = RD4(sc, off & ~3); 320 321 /* 322 * Standard 32-bit handling of command and transfer mode. 323 */ 324 if (off == SDHCI_TRANSFER_MODE) { 325 return (sc->cmd_and_mode >> 16); 326 } else if (off == SDHCI_COMMAND_FLAGS) { 327 return (sc->cmd_and_mode & 0x0000ffff); 328 } 329 return ((val >> (off & 3)*8) & 0xffff); 330 } 331 332 static uint32_t 333 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 334 { 335 struct bcm_sdhci_softc *sc = device_get_softc(dev); 336 337 return RD4(sc, off); 338 } 339 340 static void 341 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 342 uint32_t *data, bus_size_t count) 343 { 344 struct bcm_sdhci_softc *sc = device_get_softc(dev); 345 346 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 347 } 348 349 static void 350 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 351 { 352 struct bcm_sdhci_softc *sc = device_get_softc(dev); 353 uint32_t val32 = RD4(sc, off & ~3); 354 val32 &= ~(0xff << (off & 3)*8); 355 val32 |= (val << (off & 3)*8); 356 WR4(sc, off & ~3, val32); 357 } 358 359 static void 360 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 361 { 362 struct bcm_sdhci_softc *sc = device_get_softc(dev); 363 uint32_t val32; 364 if (off == SDHCI_COMMAND_FLAGS) 365 val32 = sc->cmd_and_mode; 366 else 367 val32 = RD4(sc, off & ~3); 368 val32 &= ~(0xffff << (off & 3)*8); 369 val32 |= (val << (off & 3)*8); 370 if (off == SDHCI_TRANSFER_MODE) 371 sc->cmd_and_mode = val32; 372 else { 373 WR4(sc, off & ~3, val32); 374 if (off == SDHCI_COMMAND_FLAGS) 375 sc->cmd_and_mode = val32; 376 } 377 } 378 379 static void 380 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 381 { 382 struct bcm_sdhci_softc *sc = device_get_softc(dev); 383 WR4(sc, off, val); 384 } 385 386 static void 387 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 388 uint32_t *data, bus_size_t count) 389 { 390 struct bcm_sdhci_softc *sc = device_get_softc(dev); 391 392 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 393 } 394 395 static void 396 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) 397 { 398 struct sdhci_slot *slot; 399 vm_paddr_t pdst, psrc; 400 int err, idx, len, sync_op; 401 402 slot = &sc->sc_slot; 403 idx = sc->dmamap_seg_index++; 404 len = sc->dmamap_seg_sizes[idx]; 405 slot->offset += len; 406 407 if (slot->curcmd->data->flags & MMC_DATA_READ) { 408 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 409 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 410 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 411 BCM_DMA_INC_ADDR, 412 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 413 psrc = sc->sc_sdhci_buffer_phys; 414 pdst = sc->dmamap_seg_addrs[idx]; 415 sync_op = BUS_DMASYNC_PREREAD; 416 } else { 417 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 418 BCM_DMA_INC_ADDR, 419 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 420 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 421 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 422 psrc = sc->dmamap_seg_addrs[idx]; 423 pdst = sc->sc_sdhci_buffer_phys; 424 sync_op = BUS_DMASYNC_PREWRITE; 425 } 426 427 /* 428 * When starting a new DMA operation do the busdma sync operation, and 429 * disable SDCHI data interrrupts because we'll be driven by DMA 430 * interrupts (or SDHCI error interrupts) until the IO is done. 431 */ 432 if (idx == 0) { 433 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 434 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | 435 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 436 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, 437 slot->intmask); 438 } 439 440 /* 441 * Start the DMA transfer. Only programming errors (like failing to 442 * allocate a channel) cause a non-zero return from bcm_dma_start(). 443 */ 444 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); 445 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); 446 } 447 448 static void 449 bcm_sdhci_dma_intr(int ch, void *arg) 450 { 451 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 452 struct sdhci_slot *slot = &sc->sc_slot; 453 uint32_t reg, mask; 454 int left, sync_op; 455 456 mtx_lock(&slot->mtx); 457 458 /* 459 * If there are more segments for the current dma, start the next one. 460 * Otherwise unload the dma map and decide what to do next based on the 461 * status of the sdhci controller and whether there's more data left. 462 */ 463 if (sc->dmamap_seg_index < sc->dmamap_seg_count) { 464 bcm_sdhci_start_dma_seg(sc); 465 mtx_unlock(&slot->mtx); 466 return; 467 } 468 469 if (slot->curcmd->data->flags & MMC_DATA_READ) { 470 sync_op = BUS_DMASYNC_POSTREAD; 471 mask = SDHCI_INT_DATA_AVAIL; 472 } else { 473 sync_op = BUS_DMASYNC_POSTWRITE; 474 mask = SDHCI_INT_SPACE_AVAIL; 475 } 476 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 477 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 478 479 sc->dmamap_seg_count = 0; 480 sc->dmamap_seg_index = 0; 481 482 left = min(BCM_SDHCI_BUFFER_SIZE, 483 slot->curcmd->data->len - slot->offset); 484 485 /* DATA END? */ 486 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 487 488 if (reg & SDHCI_INT_DATA_END) { 489 /* ACK for all outstanding interrupts */ 490 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 491 492 /* enable INT */ 493 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 494 | SDHCI_INT_DATA_END; 495 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 496 slot->intmask); 497 498 /* finish this data */ 499 sdhci_finish_data(slot); 500 } 501 else { 502 /* already available? */ 503 if (reg & mask) { 504 505 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 506 bcm_sdhci_write_4(slot->bus, slot, 507 SDHCI_INT_STATUS, mask); 508 509 /* continue next DMA transfer */ 510 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 511 (uint8_t *)slot->curcmd->data->data + 512 slot->offset, left, bcm_sdhci_dmacb, sc, 513 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { 514 slot->curcmd->error = MMC_ERR_NO_MEMORY; 515 sdhci_finish_data(slot); 516 } else { 517 bcm_sdhci_start_dma_seg(sc); 518 } 519 } else { 520 /* wait for next data by INT */ 521 522 /* enable INT */ 523 slot->intmask |= SDHCI_INT_DATA_AVAIL | 524 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 525 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 526 slot->intmask); 527 } 528 } 529 530 mtx_unlock(&slot->mtx); 531 } 532 533 static void 534 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) 535 { 536 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 537 size_t left; 538 539 if (sc->dmamap_seg_count != 0) { 540 device_printf(sc->sc_dev, "DMA in use\n"); 541 return; 542 } 543 544 left = min(BCM_SDHCI_BUFFER_SIZE, 545 slot->curcmd->data->len - slot->offset); 546 547 KASSERT((left & 3) == 0, 548 ("%s: len = %d, not word-aligned", __func__, left)); 549 550 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 551 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 552 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 553 sc->dmamap_status != 0) { 554 slot->curcmd->error = MMC_ERR_NO_MEMORY; 555 return; 556 } 557 558 /* DMA start */ 559 bcm_sdhci_start_dma_seg(sc); 560 } 561 562 static void 563 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) 564 { 565 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 566 size_t left; 567 568 if (sc->dmamap_seg_count != 0) { 569 device_printf(sc->sc_dev, "DMA in use\n"); 570 return; 571 } 572 573 left = min(BCM_SDHCI_BUFFER_SIZE, 574 slot->curcmd->data->len - slot->offset); 575 576 KASSERT((left & 3) == 0, 577 ("%s: len = %d, not word-aligned", __func__, left)); 578 579 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 580 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 581 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || 582 sc->dmamap_status != 0) { 583 slot->curcmd->error = MMC_ERR_NO_MEMORY; 584 return; 585 } 586 587 /* DMA start */ 588 bcm_sdhci_start_dma_seg(sc); 589 } 590 591 static int 592 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 593 { 594 size_t left; 595 596 /* 597 * Do not use DMA for transfers less than block size or with a length 598 * that is not a multiple of four. 599 */ 600 left = min(BCM_DMA_BLOCK_SIZE, 601 slot->curcmd->data->len - slot->offset); 602 if (left < BCM_DMA_BLOCK_SIZE) 603 return (0); 604 if (left & 0x03) 605 return (0); 606 607 return (1); 608 } 609 610 static void 611 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 612 uint32_t *intmask) 613 { 614 615 /* DMA transfer FIFO 1KB */ 616 if (slot->curcmd->data->flags & MMC_DATA_READ) 617 bcm_sdhci_read_dma(dev, slot); 618 else 619 bcm_sdhci_write_dma(dev, slot); 620 } 621 622 static void 623 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 624 { 625 626 sdhci_finish_data(slot); 627 } 628 629 static device_method_t bcm_sdhci_methods[] = { 630 /* Device interface */ 631 DEVMETHOD(device_probe, bcm_sdhci_probe), 632 DEVMETHOD(device_attach, bcm_sdhci_attach), 633 DEVMETHOD(device_detach, bcm_sdhci_detach), 634 635 /* Bus interface */ 636 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 637 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 638 DEVMETHOD(bus_print_child, bus_generic_print_child), 639 640 /* MMC bridge interface */ 641 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 642 DEVMETHOD(mmcbr_request, sdhci_generic_request), 643 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 644 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 645 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 646 647 /* Platform transfer methods */ 648 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 649 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 650 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 651 /* SDHCI registers accessors */ 652 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 653 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 654 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 655 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 656 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 657 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 658 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 659 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 660 661 { 0, 0 } 662 }; 663 664 static devclass_t bcm_sdhci_devclass; 665 666 static driver_t bcm_sdhci_driver = { 667 "sdhci_bcm", 668 bcm_sdhci_methods, 669 sizeof(struct bcm_sdhci_softc), 670 }; 671 672 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 673 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 674 DRIVER_MODULE(mmc, sdhci_bcm, mmc_driver, mmc_devclass, NULL, NULL); 675