1 /*- 2 * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de> 3 * Copyright (c) 2014 Ian Lepore <ian@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/smp.h> 36 37 #include <vm/vm.h> 38 #include <vm/pmap.h> 39 40 #include <machine/smp.h> 41 #include <machine/fdt.h> 42 #include <machine/intr.h> 43 44 #define SCU_PHYSBASE 0x00a00000 45 #define SCU_SIZE 0x00001000 46 47 #define SCU_CONTROL_REG 0x00 48 #define SCU_CONTROL_ENABLE (1 << 0) 49 #define SCU_CONFIG_REG 0x04 50 #define SCU_CONFIG_REG_NCPU_MASK 0x03 51 #define SCU_CPUPOWER_REG 0x08 52 #define SCU_INV_TAGS_REG 0x0c 53 #define SCU_DIAG_CONTROL 0x30 54 #define SCU_DIAG_DISABLE_MIGBIT (1 << 0) 55 #define SCU_FILTER_START_REG 0x40 56 #define SCU_FILTER_END_REG 0x44 57 #define SCU_SECURE_ACCESS_REG 0x50 58 #define SCU_NONSECURE_ACCESS_REG 0x54 59 60 #define SRC_PHYSBASE 0x020d8000 61 #define SRC_SIZE 0x4000 62 #define SRC_CONTROL_REG 0x00 63 #define SRC_CONTROL_C1ENA_SHIFT 22 /* Bit for Core 1 enable */ 64 #define SRC_CONTROL_C1RST_SHIFT 14 /* Bit for Core 1 reset */ 65 #define SRC_GPR0_C1FUNC 0x20 /* Register for Core 1 entry func */ 66 #define SRC_GPR1_C1ARG 0x24 /* Register for Core 1 entry arg */ 67 68 void 69 platform_mp_init_secondary(void) 70 { 71 72 intr_pic_init_secondary(); 73 } 74 75 void 76 platform_mp_setmaxid(void) 77 { 78 bus_space_handle_t scu; 79 int hwcpu, ncpu; 80 uint32_t val; 81 82 /* If we've already set the global vars don't bother to do it again. */ 83 if (mp_ncpus != 0) 84 return; 85 86 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) 87 panic("Couldn't map the SCU\n"); 88 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG); 89 hwcpu = (val & SCU_CONFIG_REG_NCPU_MASK) + 1; 90 bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); 91 92 ncpu = hwcpu; 93 TUNABLE_INT_FETCH("hw.ncpu", &ncpu); 94 if (ncpu < 1 || ncpu > hwcpu) 95 ncpu = hwcpu; 96 97 mp_ncpus = ncpu; 98 mp_maxid = ncpu - 1; 99 } 100 101 int 102 platform_mp_probe(void) 103 { 104 105 /* I think platform_mp_setmaxid must get called first, but be safe. */ 106 if (mp_ncpus == 0) 107 platform_mp_setmaxid(); 108 109 return (mp_ncpus > 1); 110 } 111 112 void 113 platform_mp_start_ap(void) 114 { 115 bus_space_handle_t scu; 116 bus_space_handle_t src; 117 118 uint32_t val; 119 int i; 120 121 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0) 122 panic("Couldn't map the SCU\n"); 123 if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0) 124 panic("Couldn't map the system reset controller (SRC)\n"); 125 126 /* 127 * Invalidate SCU cache tags. The 0x0000ffff constant invalidates all 128 * ways on all cores 0-3. Per the ARM docs, it's harmless to write to 129 * the bits for cores that are not present. 130 */ 131 bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff); 132 133 /* 134 * Erratum ARM/MP: 764369 (problems with cache maintenance). 135 * Setting the "disable-migratory bit" in the undocumented SCU 136 * Diagnostic Control Register helps work around the problem. 137 */ 138 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL); 139 bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, 140 val | SCU_DIAG_DISABLE_MIGBIT); 141 142 /* 143 * Enable the SCU, then clean the cache on this core. After these two 144 * operations the cache tag ram in the SCU is coherent with the contents 145 * of the cache on this core. The other cores aren't running yet so 146 * their caches can't contain valid data yet, but we've initialized 147 * their SCU tag ram above, so they will be coherent from startup. 148 */ 149 val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG); 150 bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, 151 val | SCU_CONTROL_ENABLE); 152 cpu_idcache_wbinv_all(); 153 154 /* 155 * For each AP core, set the entry point address and argument registers, 156 * and set the core-enable and core-reset bits in the control register. 157 */ 158 val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG); 159 for (i=1; i < mp_ncpus; i++) { 160 bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i, 161 pmap_kextract((vm_offset_t)mpentry)); 162 bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG + 8*i, 0); 163 164 val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) | 165 ( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i))); 166 167 } 168 bus_space_write_4(fdtbus_bs_tag, src, SRC_CONTROL_REG, val); 169 170 armv7_sev(); 171 172 bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE); 173 bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE); 174 } 175 176 void 177 platform_ipi_send(cpuset_t cpus, u_int ipi) 178 { 179 180 pic_ipi_send(cpus, ipi); 181 } 182