1 /*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/module.h> 38 #include <sys/malloc.h> 39 #include <sys/rman.h> 40 #include <sys/timeet.h> 41 #include <sys/timetc.h> 42 #include <sys/watchdog.h> 43 #include <machine/bus.h> 44 #include <machine/cpu.h> 45 #include <machine/intr.h> 46 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <arm/freescale/imx/imx_gptvar.h> 52 #include <arm/freescale/imx/imx_gptreg.h> 53 54 #include <sys/kdb.h> 55 #include <arm/freescale/imx/imx_ccmvar.h> 56 57 #define WRITE4(_sc, _r, _v) \ 58 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 59 #define READ4(_sc, _r) \ 60 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 61 #define SET4(_sc, _r, _m) \ 62 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 63 #define CLEAR4(_sc, _r, _m) \ 64 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 65 66 static u_int imx_gpt_get_timecount(struct timecounter *); 67 static int imx_gpt_timer_start(struct eventtimer *, sbintime_t, 68 sbintime_t); 69 static int imx_gpt_timer_stop(struct eventtimer *); 70 71 static int imx_gpt_intr(void *); 72 static int imx_gpt_probe(device_t); 73 static int imx_gpt_attach(device_t); 74 75 static struct timecounter imx_gpt_timecounter = { 76 .tc_name = "iMXGPT", 77 .tc_get_timecount = imx_gpt_get_timecount, 78 .tc_counter_mask = ~0u, 79 .tc_frequency = 0, 80 .tc_quality = 1000, 81 }; 82 83 /* Global softc pointer for use in DELAY(). */ 84 struct imx_gpt_softc *imx_gpt_sc = NULL; 85 86 /* 87 * Hand-calibrated delay-loop counter. This was calibrated on an i.MX6 running 88 * at 792mhz. It will delay a bit too long on slower processors -- that's 89 * better than not delaying long enough. In practice this is unlikely to get 90 * used much since the clock driver is one of the first to start up, and once 91 * we're attached the delay loop switches to using the timer hardware. 92 */ 93 static const int imx_gpt_delay_count = 78; 94 95 /* Try to divide down an available fast clock to this frequency. */ 96 #define TARGET_FREQUENCY 1000000000 97 98 /* Don't try to set an event timer period smaller than this. */ 99 #define MIN_ET_PERIOD 10LLU 100 101 102 static struct resource_spec imx_gpt_spec[] = { 103 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 104 { SYS_RES_IRQ, 0, RF_ACTIVE }, 105 { -1, 0 } 106 }; 107 108 static struct ofw_compat_data compat_data[] = { 109 {"fsl,imx6dl-gpt", 1}, 110 {"fsl,imx6q-gpt", 1}, 111 {"fsl,imx53-gpt", 1}, 112 {"fsl,imx51-gpt", 1}, 113 {"fsl,imx31-gpt", 1}, 114 {"fsl,imx27-gpt", 1}, 115 {"fsl,imx25-gpt", 1}, 116 {NULL, 0} 117 }; 118 119 static int 120 imx_gpt_probe(device_t dev) 121 { 122 123 if (!ofw_bus_status_okay(dev)) 124 return (ENXIO); 125 126 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 127 device_set_desc(dev, "Freescale i.MX GPT timer"); 128 return (BUS_PROBE_DEFAULT); 129 } 130 131 return (ENXIO); 132 } 133 134 static int 135 imx_gpt_attach(device_t dev) 136 { 137 struct imx_gpt_softc *sc; 138 int ctlreg, err; 139 uint32_t basefreq, prescale; 140 141 sc = device_get_softc(dev); 142 143 if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) { 144 device_printf(dev, "could not allocate resources\n"); 145 return (ENXIO); 146 } 147 148 sc->sc_dev = dev; 149 sc->sc_iot = rman_get_bustag(sc->res[0]); 150 sc->sc_ioh = rman_get_bushandle(sc->res[0]); 151 152 /* 153 * For now, just automatically choose a good clock for the hardware 154 * we're running on. Eventually we could allow selection from the fdt; 155 * the code in this driver will cope with any clock frequency. 156 */ 157 sc->sc_clksrc = GPT_CR_CLKSRC_IPG; 158 159 ctlreg = 0; 160 161 switch (sc->sc_clksrc) { 162 case GPT_CR_CLKSRC_32K: 163 basefreq = 32768; 164 break; 165 case GPT_CR_CLKSRC_IPG: 166 basefreq = imx_ccm_ipg_hz(); 167 break; 168 case GPT_CR_CLKSRC_IPG_HIGH: 169 basefreq = imx_ccm_ipg_hz() * 2; 170 break; 171 case GPT_CR_CLKSRC_24M: 172 ctlreg |= GPT_CR_24MEN; 173 basefreq = 24000000; 174 break; 175 case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */ 176 case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */ 177 default: 178 device_printf(dev, "Unsupported clock source '%d'\n", 179 sc->sc_clksrc); 180 return (EINVAL); 181 } 182 183 /* 184 * The following setup sequence is from the I.MX6 reference manual, 185 * "Selecting the clock source". First, disable the clock and 186 * interrupts. This also clears input and output mode bits and in 187 * general completes several of the early steps in the procedure. 188 */ 189 WRITE4(sc, IMX_GPT_CR, 0); 190 WRITE4(sc, IMX_GPT_IR, 0); 191 192 /* Choose the clock and the power-saving behaviors. */ 193 ctlreg |= 194 sc->sc_clksrc | /* Use selected clock */ 195 GPT_CR_FRR | /* Just count (FreeRunner mode) */ 196 GPT_CR_STOPEN | /* Run in STOP mode */ 197 GPT_CR_DOZEEN | /* Run in DOZE mode */ 198 GPT_CR_WAITEN | /* Run in WAIT mode */ 199 GPT_CR_DBGEN; /* Run in DEBUG mode */ 200 WRITE4(sc, IMX_GPT_CR, ctlreg); 201 202 /* 203 * The datasheet says to do the software reset after choosing the clock 204 * source. It says nothing about needing to wait for the reset to 205 * complete, but the register description does document the fact that 206 * the reset isn't complete until the SWR bit reads 0, so let's be safe. 207 * The reset also clears all registers except for a few of the bits in 208 * CR, but we'll rewrite all the CR bits when we start the counter. 209 */ 210 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR); 211 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR) 212 continue; 213 214 /* Set a prescaler value that gets us near the target frequency. */ 215 if (basefreq < TARGET_FREQUENCY) { 216 prescale = 0; 217 sc->clkfreq = basefreq; 218 } else { 219 prescale = basefreq / TARGET_FREQUENCY; 220 sc->clkfreq = basefreq / prescale; 221 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */ 222 } 223 WRITE4(sc, IMX_GPT_PR, prescale); 224 225 /* Clear the status register. */ 226 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL); 227 228 /* Start the counter. */ 229 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN); 230 231 if (bootverbose) 232 device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n", 233 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR)); 234 235 /* Setup the timer interrupt. */ 236 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr, 237 NULL, sc, &sc->sc_ih); 238 if (err != 0) { 239 bus_release_resources(dev, imx_gpt_spec, sc->res); 240 device_printf(dev, "Unable to setup the clock irq handler, " 241 "err = %d\n", err); 242 return (ENXIO); 243 } 244 245 /* Register as an eventtimer. */ 246 sc->et.et_name = "iMXGPT"; 247 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC; 248 sc->et.et_quality = 800; 249 sc->et.et_frequency = sc->clkfreq; 250 sc->et.et_min_period = (MIN_ET_PERIOD << 32) / sc->et.et_frequency; 251 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 252 sc->et.et_start = imx_gpt_timer_start; 253 sc->et.et_stop = imx_gpt_timer_stop; 254 sc->et.et_priv = sc; 255 et_register(&sc->et); 256 257 /* Register as a timecounter. */ 258 imx_gpt_timecounter.tc_frequency = sc->clkfreq; 259 tc_init(&imx_gpt_timecounter); 260 261 /* If this is the first unit, store the softc for use in DELAY. */ 262 if (device_get_unit(dev) == 0) 263 imx_gpt_sc = sc; 264 265 return (0); 266 } 267 268 static int 269 imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 270 { 271 struct imx_gpt_softc *sc; 272 uint32_t ticks; 273 274 sc = (struct imx_gpt_softc *)et->et_priv; 275 276 if (period != 0) { 277 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32; 278 /* Set expected value */ 279 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period); 280 /* Enable compare register 2 Interrupt */ 281 SET4(sc, IMX_GPT_IR, GPT_IR_OF2); 282 return (0); 283 } else if (first != 0) { 284 ticks = ((uint32_t)et->et_frequency * first) >> 32; 285 /* Do not disturb, otherwise event will be lost */ 286 spinlock_enter(); 287 /* Set expected value */ 288 WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks); 289 /* Enable compare register 1 Interrupt */ 290 SET4(sc, IMX_GPT_IR, GPT_IR_OF3); 291 /* Now everybody can relax */ 292 spinlock_exit(); 293 return (0); 294 } 295 296 return (EINVAL); 297 } 298 299 static int 300 imx_gpt_timer_stop(struct eventtimer *et) 301 { 302 struct imx_gpt_softc *sc; 303 304 sc = (struct imx_gpt_softc *)et->et_priv; 305 306 /* Disable OF2 Interrupt */ 307 CLEAR4(sc, IMX_GPT_IR, GPT_IR_OF2); 308 WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2); 309 sc->sc_period = 0; 310 311 return (0); 312 } 313 314 int 315 imx_gpt_get_timerfreq(struct imx_gpt_softc *sc) 316 { 317 318 return (sc->clkfreq); 319 } 320 321 static int 322 imx_gpt_intr(void *arg) 323 { 324 struct imx_gpt_softc *sc; 325 uint32_t status; 326 327 sc = (struct imx_gpt_softc *)arg; 328 329 status = READ4(sc, IMX_GPT_SR); 330 331 /* 332 * Clear interrupt status before invoking event callbacks. The callback 333 * often sets up a new one-shot timer event and if the interval is short 334 * enough it can fire before we get out of this function. If we cleared 335 * at the bottom we'd miss the interrupt and hang until the clock wraps. 336 */ 337 WRITE4(sc, IMX_GPT_SR, status); 338 339 /* Handle one-shot timer events. */ 340 if (status & GPT_IR_OF3) { 341 if (sc->et.et_active) { 342 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 343 } 344 } 345 346 /* Handle periodic timer events. */ 347 if (status & GPT_IR_OF2) { 348 if (sc->et.et_active) 349 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 350 if (sc->sc_period != 0) 351 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + 352 sc->sc_period); 353 } 354 355 return (FILTER_HANDLED); 356 } 357 358 u_int 359 imx_gpt_get_timecount(struct timecounter *tc) 360 { 361 362 if (imx_gpt_sc == NULL) 363 return (0); 364 365 return (READ4(imx_gpt_sc, IMX_GPT_CNT)); 366 } 367 368 static device_method_t imx_gpt_methods[] = { 369 DEVMETHOD(device_probe, imx_gpt_probe), 370 DEVMETHOD(device_attach, imx_gpt_attach), 371 372 DEVMETHOD_END 373 }; 374 375 static driver_t imx_gpt_driver = { 376 "imx_gpt", 377 imx_gpt_methods, 378 sizeof(struct imx_gpt_softc), 379 }; 380 381 static devclass_t imx_gpt_devclass; 382 383 EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0, 384 0, BUS_PASS_TIMER); 385 386 void 387 DELAY(int usec) 388 { 389 uint64_t curcnt, endcnt, startcnt, ticks; 390 391 /* If the timer hardware is not accessible, just use a loop. */ 392 if (imx_gpt_sc == NULL) { 393 while (usec-- > 0) 394 for (ticks = 0; ticks < imx_gpt_delay_count; ++ticks) 395 cpufunc_nullop(); 396 return; 397 } 398 399 /* 400 * Calculate the tick count with 64-bit values so that it works for any 401 * clock frequency. Loop until the hardware count reaches start+ticks. 402 * If the 32-bit hardware count rolls over while we're looping, just 403 * manually do a carry into the high bits after each read; don't worry 404 * that doing this on each loop iteration is inefficient -- we're trying 405 * to waste time here. 406 */ 407 ticks = 1 + ((uint64_t)usec * imx_gpt_sc->clkfreq) / 1000000; 408 curcnt = startcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 409 endcnt = startcnt + ticks; 410 while (curcnt < endcnt) { 411 curcnt = READ4(imx_gpt_sc, IMX_GPT_CNT); 412 if (curcnt < startcnt) 413 curcnt += 1ULL << 32; 414 } 415 } 416