1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 6 * Copyright (c) 2017 Semihalf. 7 * All rights reserved. 8 * 9 * Adapted and extended for Marvell SoCs by Semihalf. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/interrupt.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/queue.h> 48 #include <sys/timetc.h> 49 #include <sys/callout.h> 50 #include <sys/gpio.h> 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/gpio/gpiobusvar.h> 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 58 #include <arm/mv/mvvar.h> 59 #include <arm/mv/mvreg.h> 60 61 #include "gpio_if.h" 62 63 #define GPIO_MAX_INTR_COUNT 8 64 #define GPIO_PINS_PER_REG 32 65 #define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 66 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \ 67 GPIO_PIN_TRISTATE | GPIO_PIN_PULLUP | \ 68 GPIO_PIN_PULLDOWN | GPIO_PIN_INVIN | \ 69 GPIO_PIN_INVOUT) 70 71 #define DEBOUNCE_CHECK_MS 1 72 #define DEBOUNCE_LO_HI_MS 2 73 #define DEBOUNCE_HI_LO_MS 2 74 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS) 75 76 struct mv_gpio_softc { 77 device_t sc_busdev; 78 struct resource * mem_res; 79 int mem_rid; 80 struct resource * irq_res[GPIO_MAX_INTR_COUNT]; 81 int irq_rid[GPIO_MAX_INTR_COUNT]; 82 struct intr_event * gpio_events[MV_GPIO_MAX_NPINS]; 83 void *ih_cookie[GPIO_MAX_INTR_COUNT]; 84 bus_space_tag_t bst; 85 bus_space_handle_t bsh; 86 struct mtx mutex; 87 uint8_t pin_num; /* number of GPIO pins */ 88 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */ 89 struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS]; 90 91 /* Used for debouncing. */ 92 uint32_t debounced_state_lo; 93 uint32_t debounced_state_hi; 94 struct callout **debounce_callouts; 95 int *debounce_counters; 96 }; 97 98 struct mv_gpio_pindev { 99 device_t dev; 100 int pin; 101 }; 102 103 static int mv_gpio_probe(device_t); 104 static int mv_gpio_attach(device_t); 105 static int mv_gpio_intr(device_t, void *); 106 107 static void mv_gpio_double_edge_init(device_t, int); 108 109 static int mv_gpio_debounce_setup(device_t, int); 110 static int mv_gpio_debounce_prepare(device_t, int); 111 static int mv_gpio_debounce_init(device_t, int); 112 static void mv_gpio_debounce_start(device_t, int); 113 static void mv_gpio_debounce(void *); 114 static void mv_gpio_debounced_state_set(device_t, int, uint8_t); 115 static uint32_t mv_gpio_debounced_state_get(device_t, int); 116 117 static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int); 118 static void mv_gpio_intr_handler(device_t, int); 119 static uint32_t mv_gpio_reg_read(device_t, uint32_t); 120 static void mv_gpio_reg_write(device_t, uint32_t, uint32_t); 121 static void mv_gpio_reg_set(device_t, uint32_t, uint32_t); 122 static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t); 123 124 static void mv_gpio_blink(device_t, uint32_t, uint8_t); 125 static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t); 126 static void mv_gpio_level(device_t, uint32_t, uint8_t); 127 static void mv_gpio_edge(device_t, uint32_t, uint8_t); 128 static void mv_gpio_out_en(device_t, uint32_t, uint8_t); 129 static void mv_gpio_int_ack(struct mv_gpio_pindev *); 130 static void mv_gpio_value_set(device_t, uint32_t, uint8_t); 131 static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t); 132 133 static void mv_gpio_intr_mask(struct mv_gpio_pindev *); 134 static void mv_gpio_intr_unmask(struct mv_gpio_pindev *); 135 136 void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *); 137 int mv_gpio_setup_intrhandler(device_t, const char *, 138 driver_filter_t *, void (*)(void *), void *, 139 int, int, void **); 140 int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t); 141 void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t); 142 uint8_t mv_gpio_in(device_t, uint32_t); 143 144 /* 145 * GPIO interface 146 */ 147 static device_t mv_gpio_get_bus(device_t); 148 static int mv_gpio_pin_max(device_t, int *); 149 static int mv_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 150 static int mv_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 151 static int mv_gpio_pin_getname(device_t, uint32_t, char *); 152 static int mv_gpio_pin_setflags(device_t, uint32_t, uint32_t); 153 static int mv_gpio_pin_set(device_t, uint32_t, unsigned int); 154 static int mv_gpio_pin_get(device_t, uint32_t, unsigned int *); 155 static int mv_gpio_pin_toggle(device_t, uint32_t); 156 static int mv_gpio_map_gpios(device_t, phandle_t, phandle_t, 157 int, pcell_t *, uint32_t *, uint32_t *); 158 159 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex) 160 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex) 161 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED) 162 163 static device_method_t mv_gpio_methods[] = { 164 DEVMETHOD(device_probe, mv_gpio_probe), 165 DEVMETHOD(device_attach, mv_gpio_attach), 166 167 /* GPIO protocol */ 168 DEVMETHOD(gpio_get_bus, mv_gpio_get_bus), 169 DEVMETHOD(gpio_pin_max, mv_gpio_pin_max), 170 DEVMETHOD(gpio_pin_getname, mv_gpio_pin_getname), 171 DEVMETHOD(gpio_pin_getflags, mv_gpio_pin_getflags), 172 DEVMETHOD(gpio_pin_getcaps, mv_gpio_pin_getcaps), 173 DEVMETHOD(gpio_pin_setflags, mv_gpio_pin_setflags), 174 DEVMETHOD(gpio_pin_get, mv_gpio_pin_get), 175 DEVMETHOD(gpio_pin_set, mv_gpio_pin_set), 176 DEVMETHOD(gpio_pin_toggle, mv_gpio_pin_toggle), 177 DEVMETHOD(gpio_map_gpios, mv_gpio_map_gpios), 178 179 DEVMETHOD_END 180 }; 181 182 static driver_t mv_gpio_driver = { 183 "gpio", 184 mv_gpio_methods, 185 sizeof(struct mv_gpio_softc), 186 }; 187 188 static devclass_t mv_gpio_devclass; 189 190 DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0); 191 192 struct ofw_compat_data gpio_controllers[] = { 193 { "mrvl,gpio", (uintptr_t)true }, 194 { "marvell,orion-gpio", (uintptr_t)true }, 195 { NULL, 0 } 196 }; 197 198 static int 199 mv_gpio_probe(device_t dev) 200 { 201 if (!ofw_bus_status_okay(dev)) 202 return (ENXIO); 203 204 if (ofw_bus_search_compatible(dev, gpio_controllers)->ocd_data == 0) 205 return (ENXIO); 206 207 device_set_desc(dev, "Marvell Integrated GPIO Controller"); 208 return (0); 209 } 210 211 static int 212 mv_gpio_attach(device_t dev) 213 { 214 int i, size; 215 struct mv_gpio_softc *sc; 216 pcell_t pincnt = 0; 217 pcell_t irq_cells = 0; 218 phandle_t iparent; 219 220 sc = (struct mv_gpio_softc *)device_get_softc(dev); 221 if (sc == NULL) 222 return (ENXIO); 223 224 if (OF_getencprop(ofw_bus_get_node(dev), "pin-count", &pincnt, 225 sizeof(pcell_t)) >= 0 || 226 OF_getencprop(ofw_bus_get_node(dev), "ngpios", &pincnt, 227 sizeof(pcell_t)) >= 0) { 228 sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS); 229 if (bootverbose) 230 device_printf(dev, "%d pins available\n", sc->pin_num); 231 } else { 232 device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n"); 233 return (ENXIO); 234 } 235 236 /* Assign generic capabilities to every gpio pin */ 237 for(i = 0; i < sc->pin_num; i++) 238 sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP; 239 240 /* Find root interrupt controller */ 241 iparent = ofw_bus_find_iparent(ofw_bus_get_node(dev)); 242 if (iparent == 0) { 243 device_printf(dev, "No interrupt-parrent found. " 244 "Error in DTB\n"); 245 return (ENXIO); 246 } else { 247 /* While at parent - store interrupt cells prop */ 248 if (OF_searchencprop(OF_node_from_xref(iparent), 249 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) { 250 device_printf(dev, "DTB: Missing #interrupt-cells " 251 "property in interrupt parent node\n"); 252 return (ENXIO); 253 } 254 } 255 256 size = OF_getproplen(ofw_bus_get_node(dev), "interrupts"); 257 if (size != -1) { 258 size = size / sizeof(pcell_t); 259 size = size / irq_cells; 260 sc->irq_num = size; 261 device_printf(dev, "%d IRQs available\n", sc->irq_num); 262 } else { 263 device_printf(dev, "ERROR: no interrupts entry found!\n"); 264 return (ENXIO); 265 } 266 267 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num * 268 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO); 269 if (sc->debounce_callouts == NULL) 270 return (ENOMEM); 271 272 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int), 273 M_DEVBUF, M_WAITOK); 274 if (sc->debounce_counters == NULL) 275 return (ENOMEM); 276 277 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 278 279 sc->mem_rid = 0; 280 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 281 RF_ACTIVE); 282 283 if (!sc->mem_res) { 284 mtx_destroy(&sc->mutex); 285 device_printf(dev, "could not allocate memory window\n"); 286 return (ENXIO); 287 } 288 289 sc->bst = rman_get_bustag(sc->mem_res); 290 sc->bsh = rman_get_bushandle(sc->mem_res); 291 292 for (i = 0; i < sc->irq_num; i++) { 293 sc->irq_rid[i] = i; 294 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, 295 &sc->irq_rid[i], RF_ACTIVE); 296 if (!sc->irq_res[i]) { 297 mtx_destroy(&sc->mutex); 298 device_printf(dev, 299 "could not allocate gpio%d interrupt\n", i+1); 300 return (ENXIO); 301 } 302 } 303 304 /* Disable all interrupts */ 305 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0); 306 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0); 307 308 for (i = 0; i < sc->irq_num; i++) { 309 if (bus_setup_intr(dev, sc->irq_res[i], 310 INTR_TYPE_MISC, 311 (driver_filter_t *)mv_gpio_intr, NULL, 312 sc, &sc->ih_cookie[i]) != 0) { 313 mtx_destroy(&sc->mutex); 314 bus_release_resource(dev, SYS_RES_IRQ, 315 sc->irq_rid[i], sc->irq_res[i]); 316 device_printf(dev, "could not set up intr %d\n", i); 317 return (ENXIO); 318 } 319 } 320 321 /* Clear interrupt status. */ 322 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0); 323 324 sc->sc_busdev = gpiobus_attach_bus(dev); 325 if (sc->sc_busdev == NULL) { 326 mtx_destroy(&sc->mutex); 327 bus_release_resource(dev, SYS_RES_IRQ, 328 sc->irq_rid[i], sc->irq_res[i]); 329 return (ENXIO); 330 } 331 332 return (0); 333 } 334 335 static int 336 mv_gpio_intr(device_t dev, void *arg) 337 { 338 uint32_t int_cause, gpio_val; 339 struct mv_gpio_softc *sc; 340 sc = (struct mv_gpio_softc *)device_get_softc(dev); 341 342 MV_GPIO_LOCK(); 343 344 /* 345 * According to documentation, edge sensitive interrupts are asserted 346 * when unmasked GPIO_INT_CAUSE register bits are set. 347 */ 348 int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE); 349 int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK); 350 351 /* 352 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN 353 * register bits are set. 354 */ 355 gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN); 356 gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK); 357 358 mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0); 359 360 MV_GPIO_UNLOCK(); 361 362 return (FILTER_HANDLED); 363 } 364 365 /* 366 * GPIO interrupt handling 367 */ 368 369 void 370 mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s) 371 { 372 /* When we acheive full interrupt support 373 * This function will be opposite to 374 * mv_gpio_setup_intrhandler 375 */ 376 377 /* Now it exists only to remind that 378 * there should be place to free mv_gpio_pindev 379 * allocated by mv_gpio_setup_intrhandler 380 */ 381 free(s, M_DEVBUF); 382 } 383 384 int 385 mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt, 386 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep) 387 { 388 struct intr_event *event; 389 int error; 390 struct mv_gpio_pindev *s; 391 struct mv_gpio_softc *sc; 392 sc = (struct mv_gpio_softc *)device_get_softc(dev); 393 s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO); 394 395 if (pin < 0 || pin >= sc->pin_num) 396 return (ENXIO); 397 event = sc->gpio_events[pin]; 398 if (event == NULL) { 399 MV_GPIO_LOCK(); 400 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 401 error = mv_gpio_debounce_init(dev, pin); 402 if (error != 0) { 403 MV_GPIO_UNLOCK(); 404 return (error); 405 } 406 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) 407 mv_gpio_double_edge_init(dev, pin); 408 MV_GPIO_UNLOCK(); 409 error = intr_event_create(&event, (void *)s, 0, pin, 410 (void (*)(void *))mv_gpio_intr_mask, 411 (void (*)(void *))mv_gpio_intr_unmask, 412 (void (*)(void *))mv_gpio_int_ack, 413 NULL, 414 "gpio%d:", pin); 415 if (error != 0) 416 return (error); 417 sc->gpio_events[pin] = event; 418 } 419 420 intr_event_add_handler(event, name, filt, hand, arg, 421 intr_priority(flags), flags, cookiep); 422 return (0); 423 } 424 425 static void 426 mv_gpio_intr_mask(struct mv_gpio_pindev *s) 427 { 428 struct mv_gpio_softc *sc; 429 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 430 431 if (s->pin >= sc->pin_num) 432 return; 433 434 MV_GPIO_LOCK(); 435 436 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 437 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 438 mv_gpio_edge(s->dev, s->pin, 0); 439 else 440 mv_gpio_level(s->dev, s->pin, 0); 441 442 /* 443 * The interrupt has to be acknowledged before scheduling an interrupt 444 * thread. This way we allow for interrupt source to trigger again 445 * (which can happen with shared IRQs e.g. PCI) while processing the 446 * current event. 447 */ 448 mv_gpio_int_ack(s); 449 450 MV_GPIO_UNLOCK(); 451 452 return; 453 } 454 455 static void 456 mv_gpio_intr_unmask(struct mv_gpio_pindev *s) 457 { 458 struct mv_gpio_softc *sc; 459 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 460 461 if (s->pin >= sc->pin_num) 462 return; 463 464 MV_GPIO_LOCK(); 465 466 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 467 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 468 mv_gpio_edge(s->dev, s->pin, 1); 469 else 470 mv_gpio_level(s->dev, s->pin, 1); 471 472 MV_GPIO_UNLOCK(); 473 474 return; 475 } 476 477 static void 478 mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high) 479 { 480 int i, pin; 481 struct mv_gpio_softc *sc; 482 sc = (struct mv_gpio_softc *)device_get_softc(dev); 483 484 MV_GPIO_ASSERT_LOCKED(); 485 486 i = 0; 487 while (status != 0) { 488 if (status & 1) { 489 pin = (high ? (i + GPIO_PINS_PER_REG) : i); 490 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) 491 mv_gpio_debounce_start(dev, pin); 492 else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 493 mv_gpio_polarity(dev, pin, 0, 1); 494 mv_gpio_intr_handler(dev, pin); 495 } else 496 mv_gpio_intr_handler(dev, pin); 497 } 498 status >>= 1; 499 i++; 500 } 501 } 502 503 static void 504 mv_gpio_intr_handler(device_t dev, int pin) 505 { 506 #ifdef INTRNG 507 struct intr_irqsrc isrc; 508 struct mv_gpio_softc *sc; 509 sc = (struct mv_gpio_softc *)device_get_softc(dev); 510 511 MV_GPIO_ASSERT_LOCKED(); 512 513 #ifdef INTR_SOLO 514 isrc.isrc_filter = NULL; 515 #endif 516 isrc.isrc_event = sc->gpio_events[pin]; 517 518 if (isrc.isrc_event == NULL || TAILQ_EMPTY(&isrc.isrc_event->ie_handlers)) 519 return; 520 521 intr_isrc_dispatch(&isrc, NULL); 522 #endif 523 } 524 525 int 526 mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask) 527 { 528 int error; 529 struct mv_gpio_softc *sc; 530 sc = (struct mv_gpio_softc *)device_get_softc(dev); 531 error = 0; 532 533 if (pin >= sc->pin_num) 534 return (EINVAL); 535 536 /* check flags consistency */ 537 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 538 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) 539 return (EINVAL); 540 541 if (mask & MV_GPIO_IN_DEBOUNCE) { 542 error = mv_gpio_debounce_prepare(dev, pin); 543 if (error != 0) 544 return (error); 545 } 546 547 MV_GPIO_LOCK(); 548 549 if ((mask & flags) & GPIO_PIN_INPUT) 550 mv_gpio_out_en(dev, pin, 0); 551 if ((mask & flags) & GPIO_PIN_OUTPUT) { 552 if ((flags & mask) & GPIO_PIN_OPENDRAIN) 553 mv_gpio_value_set(dev, pin, 0); 554 else 555 mv_gpio_value_set(dev, pin, 1); 556 mv_gpio_out_en(dev, pin, 1); 557 } 558 559 if (mask & MV_GPIO_OUT_BLINK) 560 mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK); 561 if (mask & MV_GPIO_IN_POL_LOW) 562 mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0); 563 if (mask & MV_GPIO_IN_DEBOUNCE) { 564 error = mv_gpio_debounce_setup(dev, pin); 565 if (error) { 566 MV_GPIO_UNLOCK(); 567 return (error); 568 } 569 } 570 571 sc->gpio_setup[pin].gp_flags &= ~(mask); 572 sc->gpio_setup[pin].gp_flags |= (flags & mask); 573 574 MV_GPIO_UNLOCK(); 575 576 return (0); 577 } 578 579 static void 580 mv_gpio_double_edge_init(device_t dev, int pin) 581 { 582 uint8_t raw_read; 583 struct mv_gpio_softc *sc; 584 sc = (struct mv_gpio_softc *)device_get_softc(dev); 585 586 MV_GPIO_ASSERT_LOCKED(); 587 588 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 589 590 if (raw_read) 591 mv_gpio_polarity(dev, pin, 1, 0); 592 else 593 mv_gpio_polarity(dev, pin, 0, 0); 594 } 595 596 static int 597 mv_gpio_debounce_setup(device_t dev, int pin) 598 { 599 struct callout *c; 600 struct mv_gpio_softc *sc; 601 602 sc = (struct mv_gpio_softc *)device_get_softc(dev); 603 604 MV_GPIO_ASSERT_LOCKED(); 605 606 c = sc->debounce_callouts[pin]; 607 if (c == NULL) 608 return (ENXIO); 609 610 if (callout_active(c)) 611 callout_deactivate(c); 612 613 callout_stop(c); 614 615 return (0); 616 } 617 618 static int 619 mv_gpio_debounce_prepare(device_t dev, int pin) 620 { 621 struct callout *c; 622 struct mv_gpio_softc *sc; 623 624 sc = (struct mv_gpio_softc *)device_get_softc(dev); 625 626 c = sc->debounce_callouts[pin]; 627 if (c == NULL) { 628 c = (struct callout *)malloc(sizeof(struct callout), 629 M_DEVBUF, M_WAITOK); 630 sc->debounce_callouts[pin] = c; 631 if (c == NULL) 632 return (ENOMEM); 633 callout_init(c, 1); 634 } 635 636 return (0); 637 } 638 639 static int 640 mv_gpio_debounce_init(device_t dev, int pin) 641 { 642 uint8_t raw_read; 643 int *cnt; 644 struct mv_gpio_softc *sc; 645 646 sc = (struct mv_gpio_softc *)device_get_softc(dev); 647 648 MV_GPIO_ASSERT_LOCKED(); 649 650 cnt = &sc->debounce_counters[pin]; 651 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 652 if (raw_read) { 653 mv_gpio_polarity(dev, pin, 1, 0); 654 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS; 655 } else { 656 mv_gpio_polarity(dev, pin, 0, 0); 657 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS; 658 } 659 660 mv_gpio_debounced_state_set(dev, pin, raw_read); 661 662 return (0); 663 } 664 665 static void 666 mv_gpio_debounce_start(device_t dev, int pin) 667 { 668 struct callout *c; 669 struct mv_gpio_pindev s = {dev, pin}; 670 struct mv_gpio_pindev *sd; 671 struct mv_gpio_softc *sc; 672 sc = (struct mv_gpio_softc *)device_get_softc(dev); 673 674 MV_GPIO_ASSERT_LOCKED(); 675 676 c = sc->debounce_callouts[pin]; 677 if (c == NULL) { 678 mv_gpio_int_ack(&s); 679 return; 680 } 681 682 if (callout_pending(c) || callout_active(c)) { 683 mv_gpio_int_ack(&s); 684 return; 685 } 686 687 sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev), 688 M_DEVBUF, M_WAITOK); 689 if (sd == NULL) { 690 mv_gpio_int_ack(&s); 691 return; 692 } 693 sd->pin = pin; 694 sd->dev = dev; 695 696 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd); 697 } 698 699 static void 700 mv_gpio_debounce(void *arg) 701 { 702 uint8_t raw_read, last_state; 703 int pin; 704 device_t dev; 705 int *debounce_counter; 706 struct mv_gpio_softc *sc; 707 struct mv_gpio_pindev *s; 708 709 s = (struct mv_gpio_pindev *)arg; 710 dev = s->dev; 711 pin = s->pin; 712 sc = (struct mv_gpio_softc *)device_get_softc(dev); 713 714 MV_GPIO_LOCK(); 715 716 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 717 last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 718 debounce_counter = &sc->debounce_counters[pin]; 719 720 if (raw_read == last_state) { 721 if (last_state) 722 *debounce_counter = DEBOUNCE_HI_LO_MS / 723 DEBOUNCE_CHECK_MS; 724 else 725 *debounce_counter = DEBOUNCE_LO_HI_MS / 726 DEBOUNCE_CHECK_MS; 727 728 callout_reset(sc->debounce_callouts[pin], 729 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 730 } else { 731 *debounce_counter = *debounce_counter - 1; 732 if (*debounce_counter != 0) 733 callout_reset(sc->debounce_callouts[pin], 734 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 735 else { 736 mv_gpio_debounced_state_set(dev, pin, raw_read); 737 738 if (last_state) 739 *debounce_counter = DEBOUNCE_HI_LO_MS / 740 DEBOUNCE_CHECK_MS; 741 else 742 *debounce_counter = DEBOUNCE_LO_HI_MS / 743 DEBOUNCE_CHECK_MS; 744 745 if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) && 746 (raw_read == 0)) || 747 (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) && 748 raw_read) || 749 (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 750 mv_gpio_intr_handler(dev, pin); 751 752 /* Toggle polarity for next edge. */ 753 mv_gpio_polarity(dev, pin, 0, 1); 754 755 free(arg, M_DEVBUF); 756 callout_deactivate(sc->debounce_callouts[pin]); 757 } 758 } 759 760 MV_GPIO_UNLOCK(); 761 } 762 763 static void 764 mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state) 765 { 766 uint32_t *old_state; 767 struct mv_gpio_softc *sc; 768 sc = (struct mv_gpio_softc *)device_get_softc(dev); 769 770 MV_GPIO_ASSERT_LOCKED(); 771 772 if (pin >= GPIO_PINS_PER_REG) { 773 old_state = &sc->debounced_state_hi; 774 pin -= GPIO_PINS_PER_REG; 775 } else 776 old_state = &sc->debounced_state_lo; 777 778 if (new_state) 779 *old_state |= (1 << pin); 780 else 781 *old_state &= ~(1 << pin); 782 } 783 784 static uint32_t 785 mv_gpio_debounced_state_get(device_t dev, int pin) 786 { 787 uint32_t *state; 788 struct mv_gpio_softc *sc; 789 sc = (struct mv_gpio_softc *)device_get_softc(dev); 790 791 MV_GPIO_ASSERT_LOCKED(); 792 793 if (pin >= GPIO_PINS_PER_REG) { 794 state = &sc->debounced_state_hi; 795 pin -= GPIO_PINS_PER_REG; 796 } else 797 state = &sc->debounced_state_lo; 798 799 return (*state & (1 << pin)); 800 } 801 802 void 803 mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable) 804 { 805 struct mv_gpio_softc *sc; 806 sc = (struct mv_gpio_softc *)device_get_softc(dev); 807 808 MV_GPIO_LOCK(); 809 810 mv_gpio_value_set(dev, pin, val); 811 mv_gpio_out_en(dev, pin, enable); 812 813 MV_GPIO_UNLOCK(); 814 } 815 816 uint8_t 817 mv_gpio_in(device_t dev, uint32_t pin) 818 { 819 uint8_t state; 820 struct mv_gpio_softc *sc; 821 sc = (struct mv_gpio_softc *)device_get_softc(dev); 822 823 MV_GPIO_ASSERT_LOCKED(); 824 825 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 826 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 827 state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1); 828 else 829 state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 830 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 831 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 832 state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1); 833 else 834 state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 835 } else 836 state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0); 837 838 return (state); 839 } 840 841 static uint32_t 842 mv_gpio_reg_read(device_t dev, uint32_t reg) 843 { 844 struct mv_gpio_softc *sc; 845 sc = (struct mv_gpio_softc *)device_get_softc(dev); 846 847 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 848 } 849 850 static void 851 mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val) 852 { 853 struct mv_gpio_softc *sc; 854 sc = (struct mv_gpio_softc *)device_get_softc(dev); 855 856 bus_space_write_4(sc->bst, sc->bsh, reg, val); 857 } 858 859 static void 860 mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin) 861 { 862 uint32_t reg_val; 863 864 reg_val = mv_gpio_reg_read(dev, reg); 865 reg_val |= GPIO(pin); 866 mv_gpio_reg_write(dev, reg, reg_val); 867 } 868 869 static void 870 mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin) 871 { 872 uint32_t reg_val; 873 874 reg_val = mv_gpio_reg_read(dev, reg); 875 reg_val &= ~(GPIO(pin)); 876 mv_gpio_reg_write(dev, reg, reg_val); 877 } 878 879 static void 880 mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable) 881 { 882 uint32_t reg; 883 struct mv_gpio_softc *sc; 884 sc = (struct mv_gpio_softc *)device_get_softc(dev); 885 886 if (pin >= sc->pin_num) 887 return; 888 889 reg = GPIO_DATA_OUT_EN_CTRL; 890 891 if (enable) 892 mv_gpio_reg_clear(dev, reg, pin); 893 else 894 mv_gpio_reg_set(dev, reg, pin); 895 } 896 897 static void 898 mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable) 899 { 900 uint32_t reg; 901 struct mv_gpio_softc *sc; 902 sc = (struct mv_gpio_softc *)device_get_softc(dev); 903 904 if (pin >= sc->pin_num) 905 return; 906 907 reg = GPIO_BLINK_EN; 908 909 if (enable) 910 mv_gpio_reg_set(dev, reg, pin); 911 else 912 mv_gpio_reg_clear(dev, reg, pin); 913 } 914 915 static void 916 mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle) 917 { 918 uint32_t reg, reg_val; 919 struct mv_gpio_softc *sc; 920 sc = (struct mv_gpio_softc *)device_get_softc(dev); 921 922 if (pin >= sc->pin_num) 923 return; 924 925 reg = GPIO_DATA_IN_POLAR; 926 927 if (toggle) { 928 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin); 929 if (reg_val) 930 mv_gpio_reg_clear(dev, reg, pin); 931 else 932 mv_gpio_reg_set(dev, reg, pin); 933 } else if (enable) 934 mv_gpio_reg_set(dev, reg, pin); 935 else 936 mv_gpio_reg_clear(dev, reg, pin); 937 } 938 939 static void 940 mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable) 941 { 942 uint32_t reg; 943 struct mv_gpio_softc *sc; 944 sc = (struct mv_gpio_softc *)device_get_softc(dev); 945 946 if (pin >= sc->pin_num) 947 return; 948 949 reg = GPIO_INT_LEV_MASK; 950 951 if (enable) 952 mv_gpio_reg_set(dev, reg, pin); 953 else 954 mv_gpio_reg_clear(dev, reg, pin); 955 } 956 957 static void 958 mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable) 959 { 960 uint32_t reg; 961 struct mv_gpio_softc *sc; 962 sc = (struct mv_gpio_softc *)device_get_softc(dev); 963 964 if (pin >= sc->pin_num) 965 return; 966 967 reg = GPIO_INT_EDGE_MASK; 968 969 if (enable) 970 mv_gpio_reg_set(dev, reg, pin); 971 else 972 mv_gpio_reg_clear(dev, reg, pin); 973 } 974 975 static void 976 mv_gpio_int_ack(struct mv_gpio_pindev *s) 977 { 978 uint32_t reg, pin; 979 struct mv_gpio_softc *sc; 980 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 981 pin = s->pin; 982 983 if (pin >= sc->pin_num) 984 return; 985 986 reg = GPIO_INT_CAUSE; 987 988 mv_gpio_reg_clear(s->dev, reg, pin); 989 } 990 991 static uint32_t 992 mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar) 993 { 994 uint32_t reg, polar_reg, reg_val, polar_reg_val; 995 struct mv_gpio_softc *sc; 996 sc = (struct mv_gpio_softc *)device_get_softc(dev); 997 998 if (pin >= sc->pin_num) 999 return (0); 1000 1001 reg = GPIO_DATA_IN; 1002 polar_reg = GPIO_DATA_IN_POLAR; 1003 1004 reg_val = mv_gpio_reg_read(dev, reg); 1005 1006 if (exclude_polar) { 1007 polar_reg_val = mv_gpio_reg_read(dev, polar_reg); 1008 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin))); 1009 } else 1010 return (reg_val & GPIO(pin)); 1011 } 1012 1013 static void 1014 mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val) 1015 { 1016 uint32_t reg; 1017 struct mv_gpio_softc *sc; 1018 sc = (struct mv_gpio_softc *)device_get_softc(dev); 1019 1020 MV_GPIO_ASSERT_LOCKED(); 1021 1022 if (pin >= sc->pin_num) 1023 return; 1024 1025 reg = GPIO_DATA_OUT; 1026 1027 if (val) 1028 mv_gpio_reg_set(dev, reg, pin); 1029 else 1030 mv_gpio_reg_clear(dev, reg, pin); 1031 } 1032 1033 /* 1034 * GPIO interface methods 1035 */ 1036 1037 static int 1038 mv_gpio_pin_max(device_t dev, int *maxpin) 1039 { 1040 struct mv_gpio_softc *sc; 1041 if (maxpin == NULL) 1042 return (EINVAL); 1043 1044 sc = device_get_softc(dev); 1045 *maxpin = sc->pin_num; 1046 1047 return (0); 1048 } 1049 1050 static int 1051 mv_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 1052 { 1053 struct mv_gpio_softc *sc = device_get_softc(dev); 1054 if (caps == NULL) 1055 return (EINVAL); 1056 1057 if (pin >= sc->pin_num) 1058 return (EINVAL); 1059 1060 MV_GPIO_LOCK(); 1061 *caps = sc->gpio_setup[pin].gp_caps; 1062 MV_GPIO_UNLOCK(); 1063 1064 return (0); 1065 } 1066 1067 static int 1068 mv_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 1069 { 1070 struct mv_gpio_softc *sc = device_get_softc(dev); 1071 if (flags == NULL) 1072 return (EINVAL); 1073 1074 if (pin >= sc->pin_num) 1075 return (EINVAL); 1076 1077 MV_GPIO_LOCK(); 1078 *flags = sc->gpio_setup[pin].gp_flags; 1079 MV_GPIO_UNLOCK(); 1080 1081 return (0); 1082 } 1083 1084 static int 1085 mv_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 1086 { 1087 struct mv_gpio_softc *sc = device_get_softc(dev); 1088 if (name == NULL) 1089 return (EINVAL); 1090 1091 if (pin >= sc->pin_num) 1092 return (EINVAL); 1093 1094 MV_GPIO_LOCK(); 1095 memcpy(name, sc->gpio_setup[pin].gp_name, GPIOMAXNAME); 1096 MV_GPIO_UNLOCK(); 1097 1098 return (0); 1099 } 1100 1101 static int 1102 mv_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 1103 { 1104 int ret; 1105 struct mv_gpio_softc *sc = device_get_softc(dev); 1106 if (pin >= sc->pin_num) 1107 return (EINVAL); 1108 1109 /* Check for unwanted flags. */ 1110 if ((flags & sc->gpio_setup[pin].gp_caps) != flags) 1111 return (EINVAL); 1112 1113 ret = mv_gpio_configure(dev, pin, flags, ~0); 1114 1115 return (ret); 1116 } 1117 1118 static int 1119 mv_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 1120 { 1121 struct mv_gpio_softc *sc = device_get_softc(dev); 1122 if (pin >= sc->pin_num) 1123 return (EINVAL); 1124 1125 MV_GPIO_LOCK(); 1126 mv_gpio_value_set(dev, pin, value); 1127 MV_GPIO_UNLOCK(); 1128 1129 return (0); 1130 } 1131 1132 static int 1133 mv_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 1134 { 1135 struct mv_gpio_softc *sc = device_get_softc(dev); 1136 if (value == NULL) 1137 return (EINVAL); 1138 1139 if (pin >= sc->pin_num) 1140 return (EINVAL); 1141 1142 MV_GPIO_LOCK(); 1143 *value = mv_gpio_in(dev, pin); 1144 MV_GPIO_UNLOCK(); 1145 1146 return (0); 1147 } 1148 1149 static int 1150 mv_gpio_pin_toggle(device_t dev, uint32_t pin) 1151 { 1152 struct mv_gpio_softc *sc = device_get_softc(dev); 1153 uint32_t value; 1154 if (pin >= sc->pin_num) 1155 return (EINVAL); 1156 1157 MV_GPIO_LOCK(); 1158 value = mv_gpio_in(dev, pin); 1159 value = (~value) & 1; 1160 mv_gpio_value_set(dev, pin, value); 1161 MV_GPIO_UNLOCK(); 1162 1163 return (0); 1164 } 1165 1166 static device_t 1167 mv_gpio_get_bus(device_t dev) 1168 { 1169 struct mv_gpio_softc *sc = device_get_softc(dev); 1170 1171 return (sc->sc_busdev); 1172 } 1173 1174 static int 1175 mv_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 1176 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 1177 { 1178 struct mv_gpio_softc *sc = device_get_softc(bus); 1179 1180 if (gpios[0] >= sc->pin_num) 1181 return (EINVAL); 1182 1183 *pin = gpios[0]; 1184 *flags = gpios[1]; 1185 mv_gpio_configure(bus, *pin, *flags, ~0); 1186 1187 return (0); 1188 } 1189