1 /*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _MVREG_H_ 35 #define _MVREG_H_ 36 37 #if defined(SOC_MV_DISCOVERY) 38 #define IRQ_CAUSE_ERROR 0x0 39 #define IRQ_CAUSE 0x4 40 #define IRQ_CAUSE_HI 0x8 41 #define IRQ_MASK_ERROR 0xC 42 #define IRQ_MASK 0x10 43 #define IRQ_MASK_HI 0x14 44 #define IRQ_CAUSE_SELECT 0x18 45 #define FIQ_MASK_ERROR 0x1C 46 #define FIQ_MASK 0x20 47 #define FIQ_MASK_HI 0x24 48 #define FIQ_CAUSE_SELECT 0x28 49 #define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 50 #define ENDPOINT_IRQ_MASK(n) 0x30 51 #define ENDPOINT_IRQ_MASK_HI(n) 0x34 52 #define ENDPOINT_IRQ_CAUSE_SELECT 0x38 53 #elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) 54 #define IRQ_CAUSE 0x0 55 #define IRQ_MASK 0x4 56 #define FIQ_MASK 0x8 57 #define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 58 #define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 59 #define IRQ_MASK_HI (-1) /* interrupt controller code */ 60 #define FIQ_MASK_HI (-1) 61 #define ENDPOINT_IRQ_MASK_HI(n) (-1) 62 #define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 63 #define IRQ_CAUSE_ERROR (-1) 64 #define IRQ_MASK_ERROR (-1) 65 #elif defined (SOC_MV_ARMADAXP) 66 #define IRQ_CAUSE 0x18 67 #define IRQ_MASK 0x30 68 #else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */ 69 #define IRQ_CAUSE 0x0 70 #define IRQ_MASK 0x4 71 #define FIQ_MASK 0x8 72 #define ENDPOINT_IRQ_MASK(n) 0xC 73 #define IRQ_CAUSE_HI 0x10 74 #define IRQ_MASK_HI 0x14 75 #define FIQ_MASK_HI 0x18 76 #define ENDPOINT_IRQ_MASK_HI(n) 0x1C 77 #define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 78 #define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 79 #define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 80 #endif 81 82 #if defined(SOC_MV_FREY) 83 #define BRIDGE_IRQ_CAUSE 0x118 84 #define IRQ_TIMER0 0x00000002 85 #define IRQ_TIMER1 0x00000004 86 #define IRQ_TIMER_WD 0x00000008 87 88 #define BRIDGE_IRQ_MASK 0x11c 89 #define IRQ_TIMER0_MASK 0x00000002 90 #define IRQ_TIMER1_MASK 0x00000004 91 #define IRQ_TIMER_WD_MASK 0x00000008 92 #elif defined(SOC_MV_ARMADAXP) 93 #define BRIDGE_IRQ_CAUSE 0x68 94 #define IRQ_TIMER0 0x00000001 95 #define IRQ_TIMER1 0x00000002 96 #define IRQ_TIMER_WD 0x00000004 97 #else 98 #define BRIDGE_IRQ_CAUSE 0x10 99 #define IRQ_CPU_SELF 0x00000001 100 #define IRQ_TIMER0 0x00000002 101 #define IRQ_TIMER1 0x00000004 102 #define IRQ_TIMER_WD 0x00000008 103 104 #define BRIDGE_IRQ_MASK 0x14 105 #define IRQ_CPU_MASK 0x00000001 106 #define IRQ_TIMER0_MASK 0x00000002 107 #define IRQ_TIMER1_MASK 0x00000004 108 #define IRQ_TIMER_WD_MASK 0x00000008 109 #endif 110 111 #if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 112 #define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 113 #define IRQ_TIMER0_CLR IRQ_TIMER0 114 #define IRQ_TIMER1_CLR IRQ_TIMER1 115 #define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 116 #else 117 #define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 118 #define IRQ_TIMER0_CLR (~IRQ_TIMER0) 119 #define IRQ_TIMER1_CLR (~IRQ_TIMER1) 120 #define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 121 #endif 122 123 /* 124 * System reset 125 */ 126 #if defined(SOC_MV_ARMADAXP) 127 #define RSTOUTn_MASK 0x60 128 #define SYSTEM_SOFT_RESET 0x64 129 #define WD_RSTOUTn_MASK 0x4 130 #define WD_GLOBAL_MASK 0x00000100 131 #define WD_CPU0_MASK 0x00000001 132 #define SOFT_RST_OUT_EN 0x00000001 133 #define SYS_SOFT_RST 0x00000001 134 #else 135 #define RSTOUTn_MASK 0x8 136 #define WD_RST_OUT_EN 0x00000002 137 #define SOFT_RST_OUT_EN 0x00000004 138 #define SYSTEM_SOFT_RESET 0xc 139 #define SYS_SOFT_RST 0x00000001 140 #endif 141 142 /* 143 * Power Control 144 */ 145 #if defined(SOC_MV_KIRKWOOD) 146 #define CPU_PM_CTRL 0x18 147 #else 148 #define CPU_PM_CTRL 0x1C 149 #endif 150 #define CPU_PM_CTRL_NONE 0 151 #define CPU_PM_CTRL_ALL ~0x0 152 153 #if defined(SOC_MV_KIRKWOOD) 154 #define CPU_PM_CTRL_GE0 (1 << 0) 155 #define CPU_PM_CTRL_PEX0_PHY (1 << 1) 156 #define CPU_PM_CTRL_PEX0 (1 << 2) 157 #define CPU_PM_CTRL_USB0 (1 << 3) 158 #define CPU_PM_CTRL_SDIO (1 << 4) 159 #define CPU_PM_CTRL_TSU (1 << 5) 160 #define CPU_PM_CTRL_DUNIT (1 << 6) 161 #define CPU_PM_CTRL_RUNIT (1 << 7) 162 #define CPU_PM_CTRL_XOR0 (1 << 8) 163 #define CPU_PM_CTRL_AUDIO (1 << 9) 164 #define CPU_PM_CTRL_SATA0 (1 << 14) 165 #define CPU_PM_CTRL_SATA1 (1 << 15) 166 #define CPU_PM_CTRL_XOR1 (1 << 16) 167 #define CPU_PM_CTRL_CRYPTO (1 << 17) 168 #define CPU_PM_CTRL_GE1 (1 << 19) 169 #define CPU_PM_CTRL_TDM (1 << 20) 170 #define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 171 #define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 172 #define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 173 #define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 174 (1 - (u))) 175 #define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 176 #elif defined(SOC_MV_DISCOVERY) 177 #define CPU_PM_CTRL_GE0 (1 << 1) 178 #define CPU_PM_CTRL_GE1 (1 << 2) 179 #define CPU_PM_CTRL_PEX00 (1 << 5) 180 #define CPU_PM_CTRL_PEX01 (1 << 6) 181 #define CPU_PM_CTRL_PEX02 (1 << 7) 182 #define CPU_PM_CTRL_PEX03 (1 << 8) 183 #define CPU_PM_CTRL_PEX10 (1 << 9) 184 #define CPU_PM_CTRL_PEX11 (1 << 10) 185 #define CPU_PM_CTRL_PEX12 (1 << 11) 186 #define CPU_PM_CTRL_PEX13 (1 << 12) 187 #define CPU_PM_CTRL_SATA0_PHY (1 << 13) 188 #define CPU_PM_CTRL_SATA0 (1 << 14) 189 #define CPU_PM_CTRL_SATA1_PHY (1 << 15) 190 #define CPU_PM_CTRL_SATA1 (1 << 16) 191 #define CPU_PM_CTRL_USB0 (1 << 17) 192 #define CPU_PM_CTRL_USB1 (1 << 18) 193 #define CPU_PM_CTRL_USB2 (1 << 19) 194 #define CPU_PM_CTRL_IDMA (1 << 20) 195 #define CPU_PM_CTRL_XOR (1 << 21) 196 #define CPU_PM_CTRL_CRYPTO (1 << 22) 197 #define CPU_PM_CTRL_DEVICE (1 << 23) 198 #define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 199 #define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 200 #define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 201 (1 - (u))) 202 #else 203 #define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 204 #define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 205 #define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 206 #define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 207 #define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 208 #define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 209 #endif 210 211 /* 212 * Timers 213 */ 214 #define CPU_TIMERS_BASE 0x300 215 #define CPU_TIMER_CONTROL 0x0 216 #define CPU_TIMER0_EN 0x00000001 217 #define CPU_TIMER0_AUTO 0x00000002 218 #define CPU_TIMER1_EN 0x00000004 219 #define CPU_TIMER1_AUTO 0x00000008 220 #define CPU_TIMER_WD_EN 0x00000010 221 #define CPU_TIMER_WD_AUTO 0x00000020 222 /* 25MHz mode is Armada XP - specific */ 223 #define CPU_TIMER_WD_25MHZ_EN 0x00000400 224 #define CPU_TIMER0_25MHZ_EN 0x00000800 225 #define CPU_TIMER1_25MHZ_EN 0x00001000 226 #define CPU_TIMER0_REL 0x10 227 #define CPU_TIMER0 0x14 228 229 /* 230 * SATA 231 */ 232 #define SATA_CHAN_NUM 2 233 234 #define EDMA_REGISTERS_OFFSET 0x2000 235 #define EDMA_REGISTERS_SIZE 0x2000 236 #define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 237 ((ch) * EDMA_REGISTERS_SIZE)) 238 239 /* SATAHC registers */ 240 #define SATA_CR 0x000 /* Configuration Reg. */ 241 #define SATA_CR_NODMABS (1 << 8) 242 #define SATA_CR_NOEDMABS (1 << 9) 243 #define SATA_CR_NOPRDPBS (1 << 10) 244 #define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 245 246 /* Interrupt Coalescing Threshold Reg. */ 247 #define SATA_ICTR 0x00C 248 #define SATA_ICTR_MAX ((1 << 8) - 1) 249 250 /* Interrupt Time Threshold Reg. */ 251 #define SATA_ITTR 0x010 252 #define SATA_ITTR_MAX ((1 << 24) - 1) 253 254 #define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 255 #define SATA_ICR_DMADONE(ch) (1 << (ch)) 256 #define SATA_ICR_COAL (1 << 4) 257 #define SATA_ICR_DEV(ch) (1 << (8 + ch)) 258 259 #define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 260 #define SATA_MICR_ERR(ch) (1 << (2 * ch)) 261 #define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 262 #define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 263 #define SATA_MICR_COAL (1 << 8) 264 265 #define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 266 267 /* Shadow registers */ 268 #define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 269 #define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 270 271 /* SATA registers */ 272 #define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 273 #define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 274 #define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 275 #define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 276 277 /* EDMA registers */ 278 #define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 279 #define SATA_EDMA_CFG_QL128 (1 << 19) 280 #define SATA_EDMA_CFG_HQCACHE (1 << 22) 281 282 #define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 283 284 #define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 285 #define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 286 #define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 287 #define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 288 #define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 289 #define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 290 #define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 291 292 #define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 293 #define SATA_EDMA_CMD_ENABLE (1 << 0) 294 #define SATA_EDMA_CMD_DISABLE (1 << 1) 295 #define SATA_EDMA_CMD_RESET (1 << 2) 296 297 #define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 298 #define SATA_EDMA_STATUS_IDLE (1 << 7) 299 300 /* Offset to extract input slot from REQIPR register */ 301 #define SATA_EDMA_REQIS_OFS 5 302 303 /* Offset to extract input slot from RESOPR register */ 304 #define SATA_EDMA_RESOS_OFS 3 305 306 /* 307 * GPIO 308 */ 309 #define GPIO_DATA_OUT 0x00 310 #define GPIO_DATA_OUT_EN_CTRL 0x04 311 #define GPIO_BLINK_EN 0x08 312 #define GPIO_DATA_IN_POLAR 0x0c 313 #define GPIO_DATA_IN 0x10 314 #define GPIO_INT_CAUSE 0x14 315 #define GPIO_INT_EDGE_MASK 0x18 316 #define GPIO_INT_LEV_MASK 0x1c 317 318 #define GPIO_HI_DATA_OUT 0x40 319 #define GPIO_HI_DATA_OUT_EN_CTRL 0x44 320 #define GPIO_HI_BLINK_EN 0x48 321 #define GPIO_HI_DATA_IN_POLAR 0x4c 322 #define GPIO_HI_DATA_IN 0x50 323 #define GPIO_HI_INT_CAUSE 0x54 324 #define GPIO_HI_INT_EDGE_MASK 0x58 325 #define GPIO_HI_INT_LEV_MASK 0x5c 326 327 #define GPIO(n) (1 << (n)) 328 #define MV_GPIO_MAX_NPINS 64 329 330 #define MV_GPIO_IN_NONE 0x0 331 #define MV_GPIO_IN_POL_LOW (1 << 16) 332 #define MV_GPIO_IN_IRQ_EDGE (2 << 16) 333 #define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 334 #define MV_GPIO_OUT_NONE 0x0 335 #define MV_GPIO_OUT_BLINK 0x1 336 #define MV_GPIO_OUT_OPEN_DRAIN 0x2 337 #define MV_GPIO_OUT_OPEN_SRC 0x4 338 339 #define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 340 #define GPIO2IRQ(gpio) ((gpio) + NIRQ) 341 #define IRQ2GPIO(irq) ((irq) - NIRQ) 342 343 #if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 344 #define SAMPLE_AT_RESET 0x10 345 #elif defined(SOC_MV_KIRKWOOD) 346 #define SAMPLE_AT_RESET 0x30 347 #elif defined(SOC_MV_FREY) 348 #define SAMPLE_AT_RESET 0x100 349 #endif 350 #if defined(SOC_MV_DISCOVERY) 351 #define SAMPLE_AT_RESET_LO 0x30 352 #define SAMPLE_AT_RESET_HI 0x34 353 #elif defined(SOC_MV_DOVE) 354 #define SAMPLE_AT_RESET_LO 0x14 355 #define SAMPLE_AT_RESET_HI 0x18 356 #elif defined(SOC_MV_ARMADAXP) 357 #define SAMPLE_AT_RESET_LO 0x30 358 #define SAMPLE_AT_RESET_HI 0x34 359 #endif 360 361 /* 362 * Clocks 363 */ 364 #if defined(SOC_MV_ORION) 365 #define TCLK_MASK 0x00000300 366 #define TCLK_SHIFT 0x08 367 #elif defined(SOC_MV_DISCOVERY) 368 #define TCLK_MASK 0x00000180 369 #define TCLK_SHIFT 0x07 370 #elif defined(SOC_MV_LOKIPLUS) 371 #define TCLK_MASK 0x0000F000 372 #define TCLK_SHIFT 0x0C 373 #endif 374 375 #define TCLK_100MHZ 100000000 376 #define TCLK_125MHZ 125000000 377 #define TCLK_133MHZ 133333333 378 #define TCLK_150MHZ 150000000 379 #define TCLK_166MHZ 166666667 380 #define TCLK_200MHZ 200000000 381 #define TCLK_250MHZ 250000000 382 #define TCLK_300MHZ 300000000 383 #define TCLK_667MHZ 667000000 384 385 /* 386 * CPU Cache Configuration 387 */ 388 389 #define CPU_CONFIG 0x00000000 390 #define CPU_CONFIG_IC_PREF 0x00010000 391 #define CPU_CONFIG_DC_PREF 0x00020000 392 #define CPU_CONTROL 0x00000004 393 #define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 394 #define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 395 #define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 396 #define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 397 398 /* 399 * PCI Express port control (CPU Control registers) 400 */ 401 #define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 402 403 /* 404 * Vendor ID 405 */ 406 #define PCI_VENDORID_MRVL 0x11AB 407 #define PCI_VENDORID_MRVL2 0x1B4B 408 409 /* 410 * Chip ID 411 */ 412 #define MV_DEV_88F5181 0x5181 413 #define MV_DEV_88F5182 0x5182 414 #define MV_DEV_88F5281 0x5281 415 #define MV_DEV_88F6281 0x6281 416 #define MV_DEV_88F6282 0x6282 417 #define MV_DEV_88F6781 0x6781 418 #define MV_DEV_MV78100_Z0 0x6381 419 #define MV_DEV_MV78100 0x7810 420 #define MV_DEV_MV78130 0x7813 421 #define MV_DEV_MV78160 0x7816 422 #define MV_DEV_MV78230 0x7823 423 #define MV_DEV_MV78260 0x7826 424 #define MV_DEV_MV78460 0x7846 425 #define MV_DEV_88RC8180 0x8180 426 #define MV_DEV_88RC9480 0x9480 427 #define MV_DEV_88RC9580 0x9580 428 429 #define MV_DEV_FAMILY_MASK 0xff00 430 #define MV_DEV_DISCOVERY 0x7800 431 432 /* 433 * Doorbell register control 434 */ 435 #define MV_DRBL_PCIE_TO_CPU 0 436 #define MV_DRBL_CPU_TO_PCIE 1 437 438 #if defined(SOC_MV_FREY) 439 #define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 440 #define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 441 #define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 442 #else 443 #define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 444 #define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 445 #define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 446 #endif 447 #endif /* _MVREG_H_ */ 448