1ef2ee5d0SMichal Meloun /*- 2ef2ee5d0SMichal Meloun * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3ef2ee5d0SMichal Meloun * All rights reserved. 4ef2ee5d0SMichal Meloun * 5ef2ee5d0SMichal Meloun * Redistribution and use in source and binary forms, with or without 6ef2ee5d0SMichal Meloun * modification, are permitted provided that the following conditions 7ef2ee5d0SMichal Meloun * are met: 8ef2ee5d0SMichal Meloun * 1. Redistributions of source code must retain the above copyright 9ef2ee5d0SMichal Meloun * notice, this list of conditions and the following disclaimer. 10ef2ee5d0SMichal Meloun * 2. Redistributions in binary form must reproduce the above copyright 11ef2ee5d0SMichal Meloun * notice, this list of conditions and the following disclaimer in the 12ef2ee5d0SMichal Meloun * documentation and/or other materials provided with the distribution. 13ef2ee5d0SMichal Meloun * 14ef2ee5d0SMichal Meloun * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15ef2ee5d0SMichal Meloun * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16ef2ee5d0SMichal Meloun * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17ef2ee5d0SMichal Meloun * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18ef2ee5d0SMichal Meloun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19ef2ee5d0SMichal Meloun * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20ef2ee5d0SMichal Meloun * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21ef2ee5d0SMichal Meloun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22ef2ee5d0SMichal Meloun * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23ef2ee5d0SMichal Meloun * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24ef2ee5d0SMichal Meloun * SUCH DAMAGE. 25ef2ee5d0SMichal Meloun */ 26ef2ee5d0SMichal Meloun 27ef2ee5d0SMichal Meloun #ifndef _TEGRA124_CAR_ 28ef2ee5d0SMichal Meloun #define _TEGRA124_CAR_ 29ef2ee5d0SMichal Meloun 30ef2ee5d0SMichal Meloun #include "clkdev_if.h" 31ef2ee5d0SMichal Meloun 32ef2ee5d0SMichal Meloun #define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val) 33ef2ee5d0SMichal Meloun #define WR4(sc, reg, val) CLKDEV_WRITE_4((sc)->clkdev, reg, val) 34ef2ee5d0SMichal Meloun #define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set) 35ef2ee5d0SMichal Meloun #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) 36ef2ee5d0SMichal Meloun #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) 37ef2ee5d0SMichal Meloun 38ef2ee5d0SMichal Meloun #define RST_DEVICES_L 0x004 39ef2ee5d0SMichal Meloun #define RST_DEVICES_H 0x008 40ef2ee5d0SMichal Meloun #define RST_DEVICES_U 0x00C 41ef2ee5d0SMichal Meloun #define CLK_OUT_ENB_L 0x010 42ef2ee5d0SMichal Meloun #define CLK_OUT_ENB_H 0x014 43ef2ee5d0SMichal Meloun #define CLK_OUT_ENB_U 0x018 44ef2ee5d0SMichal Meloun #define CCLK_BURST_POLICY 0x020 45ef2ee5d0SMichal Meloun #define SUPER_CCLK_DIVIDER 0x024 46ef2ee5d0SMichal Meloun #define SCLK_BURST_POLICY 0x028 47ef2ee5d0SMichal Meloun #define SUPER_SCLK_DIVIDER 0x02c 48ef2ee5d0SMichal Meloun #define CLK_SYSTEM_RATE 0x030 49ef2ee5d0SMichal Meloun 50ef2ee5d0SMichal Meloun #define OSC_CTRL 0x050 51ef2ee5d0SMichal Meloun #define OSC_CTRL_OSC_FREQ_SHIFT 28 52ef2ee5d0SMichal Meloun #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 53ef2ee5d0SMichal Meloun 54ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL 0x068 55ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_SSCINCINTRV_MASK (0x3f << 24) 56ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_SSCINCINTRV_VAL (0x20 << 24) 57ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_SSCINC_MASK (0xff << 16) 58ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_SSCINC_VAL (0x1 << 16) 59ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_SSCINVERT (1 << 15) 60ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_SSCCENTER (1 << 14) 61ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_SSCBYP (1 << 12) 62ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 63ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 64ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_SSCMAX_MASK 0x1ff 65ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_SSCMAX_VAL 0x25 66ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_DISABLE (PLLE_SS_CNTL_BYPASS_SS | \ 67ef2ee5d0SMichal Meloun PLLE_SS_CNTL_INTERP_RESET | \ 68ef2ee5d0SMichal Meloun PLLE_SS_CNTL_SSCBYP) 69ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_COEFFICIENTS_MASK (PLLE_SS_CNTL_SSCMAX_MASK | \ 70ef2ee5d0SMichal Meloun PLLE_SS_CNTL_SSCINC_MASK | \ 71ef2ee5d0SMichal Meloun PLLE_SS_CNTL_SSCINCINTRV_MASK) 72ef2ee5d0SMichal Meloun #define PLLE_SS_CNTL_COEFFICIENTS_VAL (PLLE_SS_CNTL_SSCMAX_VAL | \ 73ef2ee5d0SMichal Meloun PLLE_SS_CNTL_SSCINC_VAL | \ 74ef2ee5d0SMichal Meloun PLLE_SS_CNTL_SSCINCINTRV_VAL) 75ef2ee5d0SMichal Meloun 76ef2ee5d0SMichal Meloun #define PLLC_BASE 0x080 77ef2ee5d0SMichal Meloun #define PLLC_OUT 0x084 78ef2ee5d0SMichal Meloun #define PLLC_MISC2 0x088 79ef2ee5d0SMichal Meloun #define PLLC_MISC 0x08c 80ef2ee5d0SMichal Meloun #define PLLM_BASE 0x090 81ef2ee5d0SMichal Meloun #define PLLM_OUT 0x094 82ef2ee5d0SMichal Meloun #define PLLM_MISC 0x09c 83ef2ee5d0SMichal Meloun #define PLLP_BASE 0x0a0 84ef2ee5d0SMichal Meloun #define PLLP_MISC 0x0ac 85ef2ee5d0SMichal Meloun #define PLLP_OUTA 0x0a4 86ef2ee5d0SMichal Meloun #define PLLP_OUTB 0x0a8 87ef2ee5d0SMichal Meloun #define PLLA_BASE 0x0b0 88ef2ee5d0SMichal Meloun #define PLLA_OUT 0x0b4 89ef2ee5d0SMichal Meloun #define PLLA_MISC 0x0bc 90ef2ee5d0SMichal Meloun #define PLLU_BASE 0x0c0 91ef2ee5d0SMichal Meloun #define PLLU_MISC 0x0cc 92ef2ee5d0SMichal Meloun #define PLLD_BASE 0x0d0 93ef2ee5d0SMichal Meloun #define PLLD_MISC 0x0dc 94ef2ee5d0SMichal Meloun #define PLLX_BASE 0x0e0 95ef2ee5d0SMichal Meloun #define PLLX_MISC 0x0e4 96ef2ee5d0SMichal Meloun #define PLLE_BASE 0x0e8 97ef2ee5d0SMichal Meloun #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) 98ef2ee5d0SMichal Meloun #define PLLE_BASE_DIVCML_SHIFT 24 99ef2ee5d0SMichal Meloun #define PLLE_BASE_DIVCML_MASK 0xf 100ef2ee5d0SMichal Meloun 101ef2ee5d0SMichal Meloun #define PLLE_MISC 0x0ec 102ef2ee5d0SMichal Meloun #define PLLE_MISC_SETUP_BASE_SHIFT 16 103ef2ee5d0SMichal Meloun #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 104ef2ee5d0SMichal Meloun #define PLLE_MISC_READY (1 << 15) 105ef2ee5d0SMichal Meloun #define PLLE_MISC_IDDQ_SWCTL (1 << 14) 106ef2ee5d0SMichal Meloun #define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13) 107ef2ee5d0SMichal Meloun #define PLLE_MISC_LOCK (1 << 11) 108ef2ee5d0SMichal Meloun #define PLLE_MISC_REF_ENABLE (1 << 10) 109ef2ee5d0SMichal Meloun #define PLLE_MISC_LOCK_ENABLE (1 << 9) 110ef2ee5d0SMichal Meloun #define PLLE_MISC_PTS (1 << 8) 111ef2ee5d0SMichal Meloun #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 112ef2ee5d0SMichal Meloun #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 113ef2ee5d0SMichal Meloun #define PLLE_MISC_VREG_CTRL_SHIFT 2 114ef2ee5d0SMichal Meloun #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 115ef2ee5d0SMichal Meloun 116ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2S1 0x100 117ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2S2 0x104 118ef2ee5d0SMichal Meloun #define CLK_SOURCE_SPDIF_OUT 0x108 119ef2ee5d0SMichal Meloun #define CLK_SOURCE_SPDIF_IN 0x10c 120ef2ee5d0SMichal Meloun #define CLK_SOURCE_PWM 0x110 121ef2ee5d0SMichal Meloun #define CLK_SOURCE_SPI2 0x118 122ef2ee5d0SMichal Meloun #define CLK_SOURCE_SPI3 0x11c 123ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2C1 0x124 124ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2C5 0x128 125ef2ee5d0SMichal Meloun #define CLK_SOURCE_SPI1 0x134 126ef2ee5d0SMichal Meloun #define CLK_SOURCE_DISP1 0x138 127ef2ee5d0SMichal Meloun #define CLK_SOURCE_DISP2 0x13c 128ef2ee5d0SMichal Meloun #define CLK_SOURCE_ISP 0x144 129ef2ee5d0SMichal Meloun #define CLK_SOURCE_VI 0x148 130ef2ee5d0SMichal Meloun #define CLK_SOURCE_SDMMC1 0x150 131ef2ee5d0SMichal Meloun #define CLK_SOURCE_SDMMC2 0x154 132ef2ee5d0SMichal Meloun #define CLK_SOURCE_SDMMC4 0x164 133ef2ee5d0SMichal Meloun #define CLK_SOURCE_VFIR 0x168 134ef2ee5d0SMichal Meloun #define CLK_SOURCE_HSI 0x174 135ef2ee5d0SMichal Meloun #define CLK_SOURCE_UARTA 0x178 136ef2ee5d0SMichal Meloun #define CLK_SOURCE_UARTB 0x17c 137ef2ee5d0SMichal Meloun #define CLK_SOURCE_HOST1X 0x180 138ef2ee5d0SMichal Meloun #define CLK_SOURCE_HDMI 0x18c 139ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2C2 0x198 140ef2ee5d0SMichal Meloun #define CLK_SOURCE_EMC 0x19c 141ef2ee5d0SMichal Meloun #define CLK_SOURCE_UARTC 0x1a0 142ef2ee5d0SMichal Meloun #define CLK_SOURCE_VI_SENSOR 0x1a8 143ef2ee5d0SMichal Meloun #define CLK_SOURCE_SPI4 0x1b4 144ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2C3 0x1b8 145ef2ee5d0SMichal Meloun #define CLK_SOURCE_SDMMC3 0x1bc 146ef2ee5d0SMichal Meloun #define CLK_SOURCE_UARTD 0x1c0 147ef2ee5d0SMichal Meloun #define CLK_SOURCE_VDE 0x1c8 148ef2ee5d0SMichal Meloun #define CLK_SOURCE_OWR 0x1cc 149ef2ee5d0SMichal Meloun #define CLK_SOURCE_NOR 0x1d0 150ef2ee5d0SMichal Meloun #define CLK_SOURCE_CSITE 0x1d4 151ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2S0 0x1d8 152ef2ee5d0SMichal Meloun #define CLK_SOURCE_DTV 0x1dc 153ef2ee5d0SMichal Meloun #define CLK_SOURCE_MSENC 0x1f0 154ef2ee5d0SMichal Meloun #define CLK_SOURCE_TSEC 0x1f4 155ef2ee5d0SMichal Meloun #define CLK_SOURCE_SPARE2 0x1f8 156ef2ee5d0SMichal Meloun 157ef2ee5d0SMichal Meloun #define CLK_OUT_ENB_X 0x280 158ef2ee5d0SMichal Meloun #define RST_DEVICES_X 0x28C 159ef2ee5d0SMichal Meloun 160ef2ee5d0SMichal Meloun #define RST_DEVICES_V 0x358 161ef2ee5d0SMichal Meloun #define RST_DEVICES_W 0x35C 162ef2ee5d0SMichal Meloun #define CLK_OUT_ENB_V 0x360 163ef2ee5d0SMichal Meloun #define CLK_OUT_ENB_W 0x364 164ef2ee5d0SMichal Meloun #define CCLKG_BURST_POLICY 0x368 165ef2ee5d0SMichal Meloun #define SUPER_CCLKG_DIVIDER 0x36C 166ef2ee5d0SMichal Meloun #define CCLKLP_BURST_POLICY 0x370 167ef2ee5d0SMichal Meloun #define SUPER_CCLKLP_DIVIDER 0x374 168ef2ee5d0SMichal Meloun 169ef2ee5d0SMichal Meloun #define CLK_SOURCE_MSELECT 0x3b4 170ef2ee5d0SMichal Meloun #define CLK_SOURCE_TSENSOR 0x3b8 171ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2S3 0x3bc 172ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2S4 0x3c0 173ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2C4 0x3c4 174ef2ee5d0SMichal Meloun #define CLK_SOURCE_SPI5 0x3c8 175ef2ee5d0SMichal Meloun #define CLK_SOURCE_SPI6 0x3cc 176ef2ee5d0SMichal Meloun #define CLK_SOURCE_AUDIO 0x3d0 177ef2ee5d0SMichal Meloun #define CLK_SOURCE_DAM0 0x3d8 178ef2ee5d0SMichal Meloun #define CLK_SOURCE_DAM1 0x3dc 179ef2ee5d0SMichal Meloun #define CLK_SOURCE_DAM2 0x3e0 180ef2ee5d0SMichal Meloun #define CLK_SOURCE_HDA2CODEC_2X 0x3e4 181ef2ee5d0SMichal Meloun #define CLK_SOURCE_ACTMON 0x3e8 182ef2ee5d0SMichal Meloun #define CLK_SOURCE_EXTPERIPH1 0x3ec 183ef2ee5d0SMichal Meloun #define CLK_SOURCE_EXTPERIPH2 0x3f0 184ef2ee5d0SMichal Meloun #define CLK_SOURCE_EXTPERIPH3 0x3f4 185ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2C_SLOW 0x3fc 186ef2ee5d0SMichal Meloun 187ef2ee5d0SMichal Meloun #define CLK_SOURCE_SYS 0x400 188ef2ee5d0SMichal Meloun #define CLK_SOURCE_SOR0 0x414 189ef2ee5d0SMichal Meloun #define CLK_SOURCE_SATA_OOB 0x420 190ef2ee5d0SMichal Meloun #define CLK_SOURCE_SATA 0x424 191ef2ee5d0SMichal Meloun #define CLK_SOURCE_HDA 0x428 192ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG0 0x480 193ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG1 0x484 194ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17) 195ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) 196ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15) 197ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) 198ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) 199ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 200ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 201ef2ee5d0SMichal Meloun 202ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG2 0x488 203ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 204ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 205ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) 206ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) 207ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) 208ef2ee5d0SMichal Meloun 209ef2ee5d0SMichal Meloun #define PLLE_AUX 0x48c 210ef2ee5d0SMichal Meloun #define PLLE_AUX_PLLRE_SEL (1 << 28) 211ef2ee5d0SMichal Meloun #define PLLE_AUX_SEQ_START_STATE (1 << 25) 212ef2ee5d0SMichal Meloun #define PLLE_AUX_SEQ_ENABLE (1 << 24) 213ef2ee5d0SMichal Meloun #define PLLE_AUX_SS_SWCTL (1 << 6) 214ef2ee5d0SMichal Meloun #define PLLE_AUX_ENABLE_SWCTL (1 << 4) 215ef2ee5d0SMichal Meloun #define PLLE_AUX_USE_LOCKDET (1 << 3) 216ef2ee5d0SMichal Meloun #define PLLE_AUX_PLLP_SEL (1 << 2) 217ef2ee5d0SMichal Meloun 218ef2ee5d0SMichal Meloun #define SATA_PLL_CFG0 0x490 219ef2ee5d0SMichal Meloun #define SATA_PLL_CFG0_SEQ_START_STATE (1 << 25) 220ef2ee5d0SMichal Meloun #define SATA_PLL_CFG0_SEQ_ENABLE (1 << 24) 221ef2ee5d0SMichal Meloun #define SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE (1 << 7) 222ef2ee5d0SMichal Meloun #define SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE (1 << 6) 223ef2ee5d0SMichal Meloun #define SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5) 224ef2ee5d0SMichal Meloun #define SATA_PLL_CFG0_SEQ_IN_SWCTL (1 << 4) 225ef2ee5d0SMichal Meloun #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 2) 226ef2ee5d0SMichal Meloun #define SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE (1 << 1) 227ef2ee5d0SMichal Meloun #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) 228ef2ee5d0SMichal Meloun 229ef2ee5d0SMichal Meloun #define SATA_PLL_CFG1 0x494 230ef2ee5d0SMichal Meloun #define PCIE_PLL_CFG0 0x498 231ef2ee5d0SMichal Meloun #define PCIE_PLL_CFG0_SEQ_START_STATE (1 << 25) 232ef2ee5d0SMichal Meloun #define PCIE_PLL_CFG0_SEQ_ENABLE (1 << 24) 233ef2ee5d0SMichal Meloun 234ef2ee5d0SMichal Meloun #define PLLD2_BASE 0x4b8 235ef2ee5d0SMichal Meloun #define PLLD2_MISC 0x4bc 236ef2ee5d0SMichal Meloun #define UTMIP_PLL_CFG3 0x4c0 237ef2ee5d0SMichal Meloun #define PLLRE_BASE 0x4c4 238ef2ee5d0SMichal Meloun #define PLLRE_MISC 0x4c8 239ef2ee5d0SMichal Meloun #define PLLC2_BASE 0x4e8 240ef2ee5d0SMichal Meloun #define PLLC2_MISC 0x4ec 241ef2ee5d0SMichal Meloun #define PLLC3_BASE 0x4fc 242ef2ee5d0SMichal Meloun 243ef2ee5d0SMichal Meloun #define PLLC3_MISC 0x500 244ef2ee5d0SMichal Meloun #define PLLX_MISC2 0x514 245ef2ee5d0SMichal Meloun #define PLLX_MISC2 0x514 246ef2ee5d0SMichal Meloun #define PLLX_MISC3 0x518 247ef2ee5d0SMichal Meloun #define PLLX_MISC3_DYNRAMP_STEPB_MASK 0xFF 248ef2ee5d0SMichal Meloun #define PLLX_MISC3_DYNRAMP_STEPB_SHIFT 24 249ef2ee5d0SMichal Meloun #define PLLX_MISC3_DYNRAMP_STEPA_MASK 0xFF 250ef2ee5d0SMichal Meloun #define PLLX_MISC3_DYNRAMP_STEPA_SHIFT 16 251ef2ee5d0SMichal Meloun #define PLLX_MISC3_NDIV_NEW_MASK 0xFF 252ef2ee5d0SMichal Meloun #define PLLX_MISC3_NDIV_NEW_SHIFT 8 253ef2ee5d0SMichal Meloun #define PLLX_MISC3_EN_FSTLCK (1 << 5) 254ef2ee5d0SMichal Meloun #define PLLX_MISC3_LOCK_OVERRIDE (1 << 4) 255ef2ee5d0SMichal Meloun #define PLLX_MISC3_PLL_FREQLOCK (1 << 3) 256ef2ee5d0SMichal Meloun #define PLLX_MISC3_DYNRAMP_DONE (1 << 2) 257ef2ee5d0SMichal Meloun #define PLLX_MISC3_CLAMP_NDIV (1 << 1) 258ef2ee5d0SMichal Meloun #define PLLX_MISC3_EN_DYNRAMP (1 << 0) 259ef2ee5d0SMichal Meloun #define XUSBIO_PLL_CFG0 0x51c 260ef2ee5d0SMichal Meloun #define XUSBIO_PLL_CFG0_SEQ_START_STATE (1 << 25) 261ef2ee5d0SMichal Meloun #define XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24) 262ef2ee5d0SMichal Meloun #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6) 263ef2ee5d0SMichal Meloun #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2) 264ef2ee5d0SMichal Meloun #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) 265ef2ee5d0SMichal Meloun 266ef2ee5d0SMichal Meloun #define PLLP_RESHIFT 0x528 267ef2ee5d0SMichal Meloun #define UTMIPLL_HW_PWRDN_CFG0 0x52c 268ef2ee5d0SMichal Meloun #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1 << 25) 269ef2ee5d0SMichal Meloun #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1 << 24) 270ef2ee5d0SMichal Meloun #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1 << 6) 271ef2ee5d0SMichal Meloun #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5) 272ef2ee5d0SMichal Meloun #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1 << 4) 273ef2ee5d0SMichal Meloun #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1 << 2) 274ef2ee5d0SMichal Meloun #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1 << 1) 275ef2ee5d0SMichal Meloun #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1 << 0) 276ef2ee5d0SMichal Meloun 277ef2ee5d0SMichal Meloun #define PLLDP_BASE 0x590 278ef2ee5d0SMichal Meloun #define PLLDP_MISC 0x594 279ef2ee5d0SMichal Meloun #define PLLC4_BASE 0x5a4 280ef2ee5d0SMichal Meloun #define PLLC4_MISC 0x5a8 281ef2ee5d0SMichal Meloun 282ef2ee5d0SMichal Meloun #define CLK_SOURCE_XUSB_CORE_HOST 0x600 283ef2ee5d0SMichal Meloun #define CLK_SOURCE_XUSB_FALCON 0x604 284ef2ee5d0SMichal Meloun #define CLK_SOURCE_XUSB_FS 0x608 285ef2ee5d0SMichal Meloun #define CLK_SOURCE_XUSB_CORE_DEV 0x60c 286ef2ee5d0SMichal Meloun #define CLK_SOURCE_XUSB_SS 0x610 287ef2ee5d0SMichal Meloun #define CLK_SOURCE_CILAB 0x614 288ef2ee5d0SMichal Meloun #define CLK_SOURCE_CILCD 0x618 289ef2ee5d0SMichal Meloun #define CLK_SOURCE_CILE 0x61c 290ef2ee5d0SMichal Meloun #define CLK_SOURCE_DSIA_LP 0x620 291ef2ee5d0SMichal Meloun #define CLK_SOURCE_DSIB_LP 0x624 292ef2ee5d0SMichal Meloun #define CLK_SOURCE_ENTROPY 0x628 293ef2ee5d0SMichal Meloun #define CLK_SOURCE_DVFS_REF 0x62c 294ef2ee5d0SMichal Meloun #define CLK_SOURCE_DVFS_SOC 0x630 295ef2ee5d0SMichal Meloun #define CLK_SOURCE_TRACECLKIN 0x634 296ef2ee5d0SMichal Meloun #define CLK_SOURCE_ADX 0x638 297ef2ee5d0SMichal Meloun #define CLK_SOURCE_AMX 0x63c 298ef2ee5d0SMichal Meloun #define CLK_SOURCE_EMC_LATENCY 0x640 299ef2ee5d0SMichal Meloun #define CLK_SOURCE_SOC_THERM 0x644 300ef2ee5d0SMichal Meloun #define CLK_SOURCE_VI_SENSOR2 0x658 301ef2ee5d0SMichal Meloun #define CLK_SOURCE_I2C6 0x65c 302ef2ee5d0SMichal Meloun #define CLK_SOURCE_EMC_DLL 0x664 303ef2ee5d0SMichal Meloun #define CLK_SOURCE_HDMI_AUDIO 0x668 304ef2ee5d0SMichal Meloun #define CLK_SOURCE_CLK72MHZ 0x66c 305ef2ee5d0SMichal Meloun #define CLK_SOURCE_ADX1 0x670 306ef2ee5d0SMichal Meloun #define CLK_SOURCE_AMX1 0x674 307ef2ee5d0SMichal Meloun #define CLK_SOURCE_VIC 0x678 308ef2ee5d0SMichal Meloun #define PLLP_OUTC 0x67c 309ef2ee5d0SMichal Meloun #define PLLP_MISC1 0x680 310ef2ee5d0SMichal Meloun 311ef2ee5d0SMichal Meloun struct tegra124_car_softc { 312ef2ee5d0SMichal Meloun device_t dev; 313ef2ee5d0SMichal Meloun struct resource * mem_res; 314ef2ee5d0SMichal Meloun struct mtx mtx; 315ef2ee5d0SMichal Meloun struct clkdom *clkdom; 316ef2ee5d0SMichal Meloun int type; 317ef2ee5d0SMichal Meloun }; 318ef2ee5d0SMichal Meloun 319ef2ee5d0SMichal Meloun struct tegra124_init_item { 320ef2ee5d0SMichal Meloun char *name; 321ef2ee5d0SMichal Meloun char *parent; 322ef2ee5d0SMichal Meloun uint64_t frequency; 323ef2ee5d0SMichal Meloun int enable; 324ef2ee5d0SMichal Meloun }; 325ef2ee5d0SMichal Meloun 326ef2ee5d0SMichal Meloun void tegra124_init_plls(struct tegra124_car_softc *sc); 327ef2ee5d0SMichal Meloun 328ef2ee5d0SMichal Meloun void tegra124_periph_clock(struct tegra124_car_softc *sc); 329ef2ee5d0SMichal Meloun void tegra124_super_mux_clock(struct tegra124_car_softc *sc); 330ef2ee5d0SMichal Meloun 331ef2ee5d0SMichal Meloun int tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, 332ef2ee5d0SMichal Meloun bool reset); 333ef2ee5d0SMichal Meloun 334ef2ee5d0SMichal Meloun #endif /*_TEGRA124_CAR_*/ 335