1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/lock.h> 33 #include <sys/malloc.h> 34 #include <sys/module.h> 35 #include <sys/mutex.h> 36 #include <sys/rman.h> 37 #include <sys/systm.h> 38 39 #include <machine/bus.h> 40 41 #include <dev/extres/clk/clk.h> 42 #include <dev/extres/hwreset/hwreset.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 46 #include <arm/nvidia/tegra_pmc.h> 47 48 #define PMC_CNTRL 0x000 49 #define PMC_CNTRL_CPUPWRGOOD_SEL_MASK (0x3 << 20) 50 #define PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT 20 51 #define PMC_CNTRL_CPUPWRGOOD_EN (1 << 19) 52 #define PMC_CNTRL_FUSE_OVERRIDE (1 << 18) 53 #define PMC_CNTRL_INTR_POLARITY (1 << 17) 54 #define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) 55 #define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) 56 #define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) 57 #define PMC_CNTRL_AOINIT (1 << 13) 58 #define PMC_CNTRL_PWRGATE_DIS (1 << 12) 59 #define PMC_CNTRL_SYSCLK_OE (1 << 11) 60 #define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) 61 #define PMC_CNTRL_PWRREQ_OE (1 << 9) 62 #define PMC_CNTRL_PWRREQ_POLARITY (1 << 8) 63 #define PMC_CNTRL_BLINK_EN (1 << 7) 64 #define PMC_CNTRL_GLITCHDET_DIS (1 << 6) 65 #define PMC_CNTRL_LATCHWAKE_EN (1 << 5) 66 #define PMC_CNTRL_MAIN_RST (1 << 4) 67 #define PMC_CNTRL_KBC_RST (1 << 3) 68 #define PMC_CNTRL_RTC_RST (1 << 2) 69 #define PMC_CNTRL_RTC_CLK_DIS (1 << 1) 70 #define PMC_CNTRL_KBC_CLK_DIS (1 << 0) 71 72 #define PMC_DPD_SAMPLE 0x020 73 74 #define PMC_CLAMP_STATUS 0x02C 75 #define PMC_CLAMP_STATUS_PARTID(x) (1 << ((x) & 0x1F)) 76 77 #define PMC_PWRGATE_TOGGLE 0x030 78 #define PMC_PWRGATE_TOGGLE_START (1 << 8) 79 #define PMC_PWRGATE_TOGGLE_PARTID(x) (((x) & 0x1F) << 0) 80 81 #define PMC_REMOVE_CLAMPING_CMD 0x034 82 #define PMC_REMOVE_CLAMPING_CMD_PARTID(x) (1 << ((x) & 0x1F)) 83 84 #define PMC_PWRGATE_STATUS 0x038 85 #define PMC_PWRGATE_STATUS_PARTID(x) (1 << ((x) & 0x1F)) 86 87 #define PMC_SCRATCH0 0x050 88 #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31) 89 #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30) 90 #define PMC_SCRATCH0_MODE_RCM (1 << 1) 91 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 92 PMC_SCRATCH0_MODE_BOOTLOADER | \ 93 PMC_SCRATCH0_MODE_RCM) 94 95 #define PMC_CPUPWRGOOD_TIMER 0x0c8 96 #define PMC_CPUPWROFF_TIMER 0x0cc 97 98 #define PMC_SCRATCH41 0x140 99 100 #define PMC_SENSOR_CTRL 0x1b0 101 #define PMC_SENSOR_CTRL_BLOCK_SCRATCH_WRITE (1 << 2) 102 #define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1) 103 #define PMC_SENSOR_CTRL_ENABLE_PG (1 << 0) 104 105 #define PMC_IO_DPD_REQ 0x1b8 106 #define PMC_IO_DPD_REQ_CODE_IDLE (0 << 30) 107 #define PMC_IO_DPD_REQ_CODE_OFF (1 << 30) 108 #define PMC_IO_DPD_REQ_CODE_ON (2 << 30) 109 #define PMC_IO_DPD_REQ_CODE_MASK (3 << 30) 110 111 #define PMC_IO_DPD_STATUS 0x1bc 112 #define PMC_IO_DPD_STATUS_HDMI (1 << 28) 113 #define PMC_IO_DPD2_REQ 0x1c0 114 #define PMC_IO_DPD2_STATUS 0x1c4 115 #define PMC_IO_DPD2_STATUS_HV (1 << 6) 116 #define PMC_SEL_DPD_TIM 0x1c8 117 118 #define PMC_SCRATCH54 0x258 119 #define PMC_SCRATCH54_DATA_SHIFT 8 120 #define PMC_SCRATCH54_ADDR_SHIFT 0 121 122 #define PMC_SCRATCH55 0x25c 123 #define PMC_SCRATCH55_RST_ENABLE (1 << 31) 124 #define PMC_SCRATCH55_CNTRL_TYPE (1 << 30) 125 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 126 #define PMC_SCRATCH55_CNTRL_ID_MASK 0x07 127 #define PMC_SCRATCH55_PINMUX_SHIFT 24 128 #define PMC_SCRATCH55_PINMUX_MASK 0x07 129 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 130 #define PMC_SCRATCH55_CHECKSUM_MASK 0xFF 131 #define PMC_SCRATCH55_16BITOP (1 << 15) 132 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 133 #define PMC_SCRATCH55_I2CSLV1_MASK 0x7F 134 135 #define PMC_GPU_RG_CNTRL 0x2d4 136 137 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 138 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 139 140 #define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx) 141 #define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 142 #define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \ 143 device_get_nameunit(_sc->dev), "tegra124_pmc", MTX_DEF) 144 #define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx); 145 #define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED); 146 #define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED); 147 148 struct tegra124_pmc_softc { 149 device_t dev; 150 struct resource *mem_res; 151 clk_t clk; 152 struct mtx mtx; 153 154 uint32_t rate; 155 enum tegra_suspend_mode suspend_mode; 156 uint32_t cpu_good_time; 157 uint32_t cpu_off_time; 158 uint32_t core_osc_time; 159 uint32_t core_pmu_time; 160 uint32_t core_off_time; 161 int corereq_high; 162 int sysclkreq_high; 163 int combined_req; 164 int cpu_pwr_good_en; 165 uint32_t lp0_vec_phys; 166 uint32_t lp0_vec_size; 167 }; 168 169 static struct ofw_compat_data compat_data[] = { 170 {"nvidia,tegra124-pmc", 1}, 171 {NULL, 0}, 172 }; 173 174 static struct tegra124_pmc_softc *pmc_sc; 175 176 static inline struct tegra124_pmc_softc * 177 tegra124_pmc_get_sc(void) 178 { 179 if (pmc_sc == NULL) 180 panic("To early call to Tegra PMC driver.\n"); 181 return (pmc_sc); 182 } 183 184 static int 185 tegra124_pmc_set_powergate(struct tegra124_pmc_softc *sc, 186 enum tegra_powergate_id id, int ena) 187 { 188 uint32_t reg; 189 int i; 190 191 PMC_LOCK(sc); 192 193 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id); 194 if (((reg != 0) && ena) || ((reg == 0) && !ena)) { 195 PMC_UNLOCK(sc); 196 return (0); 197 } 198 199 for (i = 100; i > 0; i--) { 200 reg = RD4(sc, PMC_PWRGATE_TOGGLE); 201 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0) 202 break; 203 DELAY(1); 204 } 205 if (i <= 0) 206 device_printf(sc->dev, 207 "Timeout when waiting for TOGGLE_START\n"); 208 209 WR4(sc, PMC_PWRGATE_TOGGLE, 210 PMC_PWRGATE_TOGGLE_START | PMC_PWRGATE_TOGGLE_PARTID(id)); 211 212 for (i = 100; i > 0; i--) { 213 reg = RD4(sc, PMC_PWRGATE_TOGGLE); 214 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0) 215 break; 216 DELAY(1); 217 } 218 if (i <= 0) 219 device_printf(sc->dev, 220 "Timeout when waiting for TOGGLE_START\n"); 221 PMC_UNLOCK(sc); 222 return (0); 223 } 224 225 int 226 tegra_powergate_remove_clamping(enum tegra_powergate_id id) 227 { 228 struct tegra124_pmc_softc *sc; 229 uint32_t reg; 230 enum tegra_powergate_id swid; 231 int i; 232 233 sc = tegra124_pmc_get_sc(); 234 235 if (id == TEGRA_POWERGATE_3D) { 236 WR4(sc, PMC_GPU_RG_CNTRL, 0); 237 return (0); 238 } 239 240 reg = RD4(sc, PMC_PWRGATE_STATUS); 241 if ((reg & PMC_PWRGATE_STATUS_PARTID(id)) == 0) 242 panic("Attempt to remove clamping for unpowered partition.\n"); 243 244 if (id == TEGRA_POWERGATE_PCX) 245 swid = TEGRA_POWERGATE_VDE; 246 else if (id == TEGRA_POWERGATE_VDE) 247 swid = TEGRA_POWERGATE_PCX; 248 else 249 swid = id; 250 WR4(sc, PMC_REMOVE_CLAMPING_CMD, PMC_REMOVE_CLAMPING_CMD_PARTID(swid)); 251 252 for (i = 100; i > 0; i--) { 253 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD); 254 if ((reg & PMC_REMOVE_CLAMPING_CMD_PARTID(swid)) == 0) 255 break; 256 DELAY(1); 257 } 258 if (i <= 0) 259 device_printf(sc->dev, "Timeout when remove clamping\n"); 260 261 reg = RD4(sc, PMC_CLAMP_STATUS); 262 if ((reg & PMC_CLAMP_STATUS_PARTID(id)) != 0) 263 panic("Cannot remove clamping\n"); 264 265 return (0); 266 } 267 268 int 269 tegra_powergate_is_powered(enum tegra_powergate_id id) 270 { 271 struct tegra124_pmc_softc *sc; 272 uint32_t reg; 273 274 sc = tegra124_pmc_get_sc(); 275 276 reg = RD4(sc, PMC_PWRGATE_STATUS); 277 return ((reg & PMC_PWRGATE_STATUS_PARTID(id)) ? 1 : 0); 278 } 279 280 int 281 tegra_powergate_power_on(enum tegra_powergate_id id) 282 { 283 struct tegra124_pmc_softc *sc; 284 int rv, i; 285 286 sc = tegra124_pmc_get_sc(); 287 288 rv = tegra124_pmc_set_powergate(sc, id, 1); 289 if (rv != 0) { 290 device_printf(sc->dev, "Cannot set powergate: %d\n", id); 291 return (rv); 292 } 293 294 for (i = 100; i > 0; i--) { 295 if (tegra_powergate_is_powered(id)) 296 break; 297 DELAY(1); 298 } 299 if (i <= 0) 300 device_printf(sc->dev, "Timeout when waiting on power up\n"); 301 302 return (rv); 303 } 304 305 int 306 tegra_powergate_power_off(enum tegra_powergate_id id) 307 { 308 struct tegra124_pmc_softc *sc; 309 int rv, i; 310 311 sc = tegra124_pmc_get_sc(); 312 313 rv = tegra124_pmc_set_powergate(sc, id, 0); 314 if (rv != 0) { 315 device_printf(sc->dev, "Cannot set powergate: %d\n", id); 316 return (rv); 317 } 318 for (i = 100; i > 0; i--) { 319 if (!tegra_powergate_is_powered(id)) 320 break; 321 DELAY(1); 322 } 323 if (i <= 0) 324 device_printf(sc->dev, "Timeout when waiting on power off\n"); 325 326 return (rv); 327 } 328 329 int 330 tegra_powergate_sequence_power_up(enum tegra_powergate_id id, clk_t clk, 331 hwreset_t rst) 332 { 333 struct tegra124_pmc_softc *sc; 334 int rv; 335 336 sc = tegra124_pmc_get_sc(); 337 338 rv = hwreset_assert(rst); 339 if (rv != 0) { 340 device_printf(sc->dev, "Cannot assert reset\n"); 341 return (rv); 342 } 343 344 rv = clk_stop(clk); 345 if (rv != 0) { 346 device_printf(sc->dev, "Cannot stop clock\n"); 347 goto clk_fail; 348 } 349 350 rv = tegra_powergate_power_on(id); 351 if (rv != 0) { 352 device_printf(sc->dev, "Cannot power on powergate\n"); 353 goto clk_fail; 354 } 355 356 rv = clk_enable(clk); 357 if (rv != 0) { 358 device_printf(sc->dev, "Cannot enable clock\n"); 359 goto clk_fail; 360 } 361 DELAY(20); 362 363 rv = tegra_powergate_remove_clamping(id); 364 if (rv != 0) { 365 device_printf(sc->dev, "Cannot remove clamping\n"); 366 goto fail; 367 } 368 rv = hwreset_deassert(rst); 369 if (rv != 0) { 370 device_printf(sc->dev, "Cannot unreset reset\n"); 371 goto fail; 372 } 373 return 0; 374 375 fail: 376 clk_disable(clk); 377 clk_fail: 378 hwreset_assert(rst); 379 tegra_powergate_power_off(id); 380 return (rv); 381 } 382 383 static int 384 tegra124_pmc_parse_fdt(struct tegra124_pmc_softc *sc, phandle_t node) 385 { 386 int rv; 387 uint32_t tmp; 388 uint32_t tmparr[2]; 389 390 rv = OF_getencprop(node, "nvidia,suspend-mode", &tmp, sizeof(tmp)); 391 if (rv > 0) { 392 switch (tmp) { 393 case 0: 394 sc->suspend_mode = TEGRA_SUSPEND_LP0; 395 break; 396 397 case 1: 398 sc->suspend_mode = TEGRA_SUSPEND_LP1; 399 break; 400 401 case 2: 402 sc->suspend_mode = TEGRA_SUSPEND_LP2; 403 break; 404 405 default: 406 sc->suspend_mode = TEGRA_SUSPEND_NONE; 407 break; 408 } 409 } 410 411 rv = OF_getencprop(node, "nvidia,cpu-pwr-good-time", &tmp, sizeof(tmp)); 412 if (rv > 0) { 413 sc->cpu_good_time = tmp; 414 sc->suspend_mode = TEGRA_SUSPEND_NONE; 415 } 416 417 rv = OF_getencprop(node, "nvidia,cpu-pwr-off-time", &tmp, sizeof(tmp)); 418 if (rv > 0) { 419 sc->cpu_off_time = tmp; 420 sc->suspend_mode = TEGRA_SUSPEND_NONE; 421 } 422 423 rv = OF_getencprop(node, "nvidia,core-pwr-good-time", tmparr, 424 sizeof(tmparr)); 425 if (rv == sizeof(tmparr)) { 426 sc->core_osc_time = tmparr[0]; 427 sc->core_pmu_time = tmparr[1]; 428 sc->suspend_mode = TEGRA_SUSPEND_NONE; 429 } 430 431 rv = OF_getencprop(node, "nvidia,core-pwr-off-time", &tmp, sizeof(tmp)); 432 if (rv > 0) { 433 sc->core_off_time = tmp; 434 sc->suspend_mode = TEGRA_SUSPEND_NONE; 435 } 436 437 sc->corereq_high = 438 OF_hasprop(node, "nvidia,core-power-req-active-high"); 439 sc->sysclkreq_high = 440 OF_hasprop(node, "nvidia,sys-clock-req-active-high"); 441 sc->combined_req = 442 OF_hasprop(node, "nvidia,combined-power-req"); 443 sc->cpu_pwr_good_en = 444 OF_hasprop(node, "nvidia,cpu-pwr-good-en"); 445 446 rv = OF_getencprop(node, "nvidia,lp0-vec", tmparr, sizeof(tmparr)); 447 if (rv == sizeof(tmparr)) { 448 sc->lp0_vec_phys = tmparr[0]; 449 sc->core_pmu_time = tmparr[1]; 450 sc->lp0_vec_size = TEGRA_SUSPEND_NONE; 451 if (sc->suspend_mode == TEGRA_SUSPEND_LP0) 452 sc->suspend_mode = TEGRA_SUSPEND_LP1; 453 } 454 return 0; 455 } 456 457 static int 458 tegra124_pmc_probe(device_t dev) 459 { 460 461 if (!ofw_bus_status_okay(dev)) 462 return (ENXIO); 463 464 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 465 return (ENXIO); 466 467 device_set_desc(dev, "Tegra PMC"); 468 return (BUS_PROBE_DEFAULT); 469 } 470 471 static int 472 tegra124_pmc_detach(device_t dev) 473 { 474 475 /* This device is always present. */ 476 return (EBUSY); 477 } 478 479 static int 480 tegra124_pmc_attach(device_t dev) 481 { 482 struct tegra124_pmc_softc *sc; 483 int rid, rv; 484 uint32_t reg; 485 phandle_t node; 486 487 sc = device_get_softc(dev); 488 sc->dev = dev; 489 node = ofw_bus_get_node(dev); 490 491 rv = tegra124_pmc_parse_fdt(sc, node); 492 if (rv != 0) { 493 device_printf(sc->dev, "Cannot parse FDT data\n"); 494 return (rv); 495 } 496 497 rv = clk_get_by_ofw_name(sc->dev, 0, "pclk", &sc->clk); 498 if (rv != 0) { 499 device_printf(sc->dev, "Cannot get \"pclk\" clock\n"); 500 return (ENXIO); 501 } 502 503 rid = 0; 504 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 505 RF_ACTIVE); 506 if (sc->mem_res == NULL) { 507 device_printf(dev, "Cannot allocate memory resources\n"); 508 return (ENXIO); 509 } 510 511 PMC_LOCK_INIT(sc); 512 513 /* Enable CPU power request. */ 514 reg = RD4(sc, PMC_CNTRL); 515 reg |= PMC_CNTRL_CPU_PWRREQ_OE; 516 WR4(sc, PMC_CNTRL, reg); 517 518 /* Set sysclk output polarity */ 519 reg = RD4(sc, PMC_CNTRL); 520 if (sc->sysclkreq_high) 521 reg &= ~PMC_CNTRL_SYSCLK_POLARITY; 522 else 523 reg |= PMC_CNTRL_SYSCLK_POLARITY; 524 WR4(sc, PMC_CNTRL, reg); 525 526 /* Enable sysclk request. */ 527 reg = RD4(sc, PMC_CNTRL); 528 reg |= PMC_CNTRL_SYSCLK_OE; 529 WR4(sc, PMC_CNTRL, reg); 530 531 /* 532 * Remove HDMI from deep power down mode. 533 * XXX mote this to HDMI driver 534 */ 535 reg = RD4(sc, PMC_IO_DPD_STATUS); 536 reg &= ~ PMC_IO_DPD_STATUS_HDMI; 537 WR4(sc, PMC_IO_DPD_STATUS, reg); 538 539 reg = RD4(sc, PMC_IO_DPD2_STATUS); 540 reg &= ~ PMC_IO_DPD2_STATUS_HV; 541 WR4(sc, PMC_IO_DPD2_STATUS, reg); 542 543 if (pmc_sc != NULL) 544 panic("tegra124_pmc: double driver attach"); 545 pmc_sc = sc; 546 return (0); 547 } 548 549 static device_method_t tegra124_pmc_methods[] = { 550 /* Device interface */ 551 DEVMETHOD(device_probe, tegra124_pmc_probe), 552 DEVMETHOD(device_attach, tegra124_pmc_attach), 553 DEVMETHOD(device_detach, tegra124_pmc_detach), 554 555 DEVMETHOD_END 556 }; 557 558 static DEFINE_CLASS_0(pmc, tegra124_pmc_driver, tegra124_pmc_methods, 559 sizeof(struct tegra124_pmc_softc)); 560 EARLY_DRIVER_MODULE(tegra124_pmc, simplebus, tegra124_pmc_driver, NULL, NULL, 561 70); 562