1 /*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2003 Peter Wemm 9 * All rights reserved. 10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 11 * All rights reserved. 12 * Copyright (c) 2014 Andrew Turner 13 * All rights reserved. 14 * Copyright (c) 2014-2016 The FreeBSD Foundation 15 * All rights reserved. 16 * 17 * This code is derived from software contributed to Berkeley by 18 * the Systems Programming Group of the University of Utah Computer 19 * Science Department and William Jolitz of UUNET Technologies Inc. 20 * 21 * This software was developed by Andrew Turner under sponsorship from 22 * the FreeBSD Foundation. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by the University of 35 * California, Berkeley and its contributors. 36 * 4. Neither the name of the University nor the names of its contributors 37 * may be used to endorse or promote products derived from this software 38 * without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 * 52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 53 */ 54 /*- 55 * Copyright (c) 2003 Networks Associates Technology, Inc. 56 * All rights reserved. 57 * 58 * This software was developed for the FreeBSD Project by Jake Burkholder, 59 * Safeport Network Services, and Network Associates Laboratories, the 60 * Security Research Division of Network Associates, Inc. under 61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 62 * CHATS research program. 63 * 64 * Redistribution and use in source and binary forms, with or without 65 * modification, are permitted provided that the following conditions 66 * are met: 67 * 1. Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * 2. Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in the 71 * documentation and/or other materials provided with the distribution. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 83 * SUCH DAMAGE. 84 */ 85 86 #include <sys/cdefs.h> 87 __FBSDID("$FreeBSD$"); 88 89 /* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is 93 * also stored by the logical address mapping module, 94 * this module may throw away valid virtual-to-physical 95 * mappings at almost any time. However, invalidations 96 * of virtual-to-physical mappings must be done as 97 * requested. 98 * 99 * In order to cope with hardware architectures which 100 * make virtual-to-physical map invalidates expensive, 101 * this module may delay invalidate or reduced protection 102 * operations until such time as they are actually 103 * necessary. This module is given full information as 104 * to which processors are currently using which maps, 105 * and to when physical maps must be made correct. 106 */ 107 108 #include "opt_vm.h" 109 110 #include <sys/param.h> 111 #include <sys/bitstring.h> 112 #include <sys/bus.h> 113 #include <sys/systm.h> 114 #include <sys/kernel.h> 115 #include <sys/ktr.h> 116 #include <sys/limits.h> 117 #include <sys/lock.h> 118 #include <sys/malloc.h> 119 #include <sys/mman.h> 120 #include <sys/msgbuf.h> 121 #include <sys/mutex.h> 122 #include <sys/physmem.h> 123 #include <sys/proc.h> 124 #include <sys/rwlock.h> 125 #include <sys/sbuf.h> 126 #include <sys/sx.h> 127 #include <sys/vmem.h> 128 #include <sys/vmmeter.h> 129 #include <sys/sched.h> 130 #include <sys/sysctl.h> 131 #include <sys/_unrhdr.h> 132 #include <sys/smp.h> 133 134 #include <vm/vm.h> 135 #include <vm/vm_param.h> 136 #include <vm/vm_kern.h> 137 #include <vm/vm_page.h> 138 #include <vm/vm_map.h> 139 #include <vm/vm_object.h> 140 #include <vm/vm_extern.h> 141 #include <vm/vm_pageout.h> 142 #include <vm/vm_pager.h> 143 #include <vm/vm_phys.h> 144 #include <vm/vm_radix.h> 145 #include <vm/vm_reserv.h> 146 #include <vm/vm_dumpset.h> 147 #include <vm/uma.h> 148 149 #include <machine/machdep.h> 150 #include <machine/md_var.h> 151 #include <machine/pcb.h> 152 153 #ifdef NUMA 154 #define PMAP_MEMDOM MAXMEMDOM 155 #else 156 #define PMAP_MEMDOM 1 157 #endif 158 159 #define PMAP_ASSERT_STAGE1(pmap) MPASS((pmap)->pm_stage == PM_STAGE1) 160 #define PMAP_ASSERT_STAGE2(pmap) MPASS((pmap)->pm_stage == PM_STAGE2) 161 162 #define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t))) 163 #define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t))) 164 #define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t))) 165 #define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t))) 166 167 #define NUL0E L0_ENTRIES 168 #define NUL1E (NUL0E * NL1PG) 169 #define NUL2E (NUL1E * NL2PG) 170 171 #if !defined(DIAGNOSTIC) 172 #ifdef __GNUC_GNU_INLINE__ 173 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline 174 #else 175 #define PMAP_INLINE extern inline 176 #endif 177 #else 178 #define PMAP_INLINE 179 #endif 180 181 #ifdef PV_STATS 182 #define PV_STAT(x) do { x ; } while (0) 183 #else 184 #define PV_STAT(x) do { } while (0) 185 #endif 186 187 #define pmap_l0_pindex(v) (NUL2E + NUL1E + ((v) >> L0_SHIFT)) 188 #define pmap_l1_pindex(v) (NUL2E + ((v) >> L1_SHIFT)) 189 #define pmap_l2_pindex(v) ((v) >> L2_SHIFT) 190 191 static struct md_page * 192 pa_to_pvh(vm_paddr_t pa) 193 { 194 struct vm_phys_seg *seg; 195 int segind; 196 197 for (segind = 0; segind < vm_phys_nsegs; segind++) { 198 seg = &vm_phys_segs[segind]; 199 if (pa >= seg->start && pa < seg->end) 200 return ((struct md_page *)seg->md_first + 201 pmap_l2_pindex(pa) - pmap_l2_pindex(seg->start)); 202 } 203 panic("pa 0x%jx not within vm_phys_segs", (uintmax_t)pa); 204 } 205 206 static struct md_page * 207 page_to_pvh(vm_page_t m) 208 { 209 struct vm_phys_seg *seg; 210 211 seg = &vm_phys_segs[m->segind]; 212 return ((struct md_page *)seg->md_first + 213 pmap_l2_pindex(VM_PAGE_TO_PHYS(m)) - pmap_l2_pindex(seg->start)); 214 } 215 216 #define NPV_LIST_LOCKS MAXCPU 217 218 #define PHYS_TO_PV_LIST_LOCK(pa) \ 219 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS]) 220 221 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \ 222 struct rwlock **_lockp = (lockp); \ 223 struct rwlock *_new_lock; \ 224 \ 225 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \ 226 if (_new_lock != *_lockp) { \ 227 if (*_lockp != NULL) \ 228 rw_wunlock(*_lockp); \ 229 *_lockp = _new_lock; \ 230 rw_wlock(*_lockp); \ 231 } \ 232 } while (0) 233 234 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \ 235 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m)) 236 237 #define RELEASE_PV_LIST_LOCK(lockp) do { \ 238 struct rwlock **_lockp = (lockp); \ 239 \ 240 if (*_lockp != NULL) { \ 241 rw_wunlock(*_lockp); \ 242 *_lockp = NULL; \ 243 } \ 244 } while (0) 245 246 #define VM_PAGE_TO_PV_LIST_LOCK(m) \ 247 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m)) 248 249 /* 250 * The presence of this flag indicates that the mapping is writeable. 251 * If the ATTR_S1_AP_RO bit is also set, then the mapping is clean, otherwise 252 * it is dirty. This flag may only be set on managed mappings. 253 * 254 * The DBM bit is reserved on ARMv8.0 but it seems we can safely treat it 255 * as a software managed bit. 256 */ 257 #define ATTR_SW_DBM ATTR_DBM 258 259 struct pmap kernel_pmap_store; 260 261 /* Used for mapping ACPI memory before VM is initialized */ 262 #define PMAP_PREINIT_MAPPING_COUNT 32 263 #define PMAP_PREINIT_MAPPING_SIZE (PMAP_PREINIT_MAPPING_COUNT * L2_SIZE) 264 static vm_offset_t preinit_map_va; /* Start VA of pre-init mapping space */ 265 static int vm_initialized = 0; /* No need to use pre-init maps when set */ 266 267 /* 268 * Reserve a few L2 blocks starting from 'preinit_map_va' pointer. 269 * Always map entire L2 block for simplicity. 270 * VA of L2 block = preinit_map_va + i * L2_SIZE 271 */ 272 static struct pmap_preinit_mapping { 273 vm_paddr_t pa; 274 vm_offset_t va; 275 vm_size_t size; 276 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT]; 277 278 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 279 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 280 vm_offset_t kernel_vm_end = 0; 281 282 /* 283 * Data for the pv entry allocation mechanism. 284 */ 285 #ifdef NUMA 286 static __inline int 287 pc_to_domain(struct pv_chunk *pc) 288 { 289 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc))); 290 } 291 #else 292 static __inline int 293 pc_to_domain(struct pv_chunk *pc __unused) 294 { 295 return (0); 296 } 297 #endif 298 299 struct pv_chunks_list { 300 struct mtx pvc_lock; 301 TAILQ_HEAD(pch, pv_chunk) pvc_list; 302 int active_reclaims; 303 } __aligned(CACHE_LINE_SIZE); 304 305 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM]; 306 307 static struct rwlock pv_list_locks[NPV_LIST_LOCKS]; 308 static struct md_page *pv_table; 309 static struct md_page pv_dummy; 310 311 vm_paddr_t dmap_phys_base; /* The start of the dmap region */ 312 vm_paddr_t dmap_phys_max; /* The limit of the dmap region */ 313 vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */ 314 315 extern pt_entry_t pagetable_l0_ttbr1[]; 316 317 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 318 static vm_paddr_t physmap[PHYSMAP_SIZE]; 319 static u_int physmap_idx; 320 321 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 322 "VM/pmap parameters"); 323 324 #if PAGE_SIZE == PAGE_SIZE_4K 325 #define L1_BLOCKS_SUPPORTED 1 326 #else 327 /* TODO: Make this dynamic when we support FEAT_LPA2 (TCR_EL1.DS == 1) */ 328 #define L1_BLOCKS_SUPPORTED 0 329 #endif 330 331 #define PMAP_ASSERT_L1_BLOCKS_SUPPORTED MPASS(L1_BLOCKS_SUPPORTED) 332 333 /* 334 * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs 335 * that it has currently allocated to a pmap, a cursor ("asid_next") to 336 * optimize its search for a free ASID in the bit vector, and an epoch number 337 * ("asid_epoch") to indicate when it has reclaimed all previously allocated 338 * ASIDs that are not currently active on a processor. 339 * 340 * The current epoch number is always in the range [0, INT_MAX). Negative 341 * numbers and INT_MAX are reserved for special cases that are described 342 * below. 343 */ 344 struct asid_set { 345 int asid_bits; 346 bitstr_t *asid_set; 347 int asid_set_size; 348 int asid_next; 349 int asid_epoch; 350 struct mtx asid_set_mutex; 351 }; 352 353 static struct asid_set asids; 354 static struct asid_set vmids; 355 356 static SYSCTL_NODE(_vm_pmap, OID_AUTO, asid, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 357 "ASID allocator"); 358 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, bits, CTLFLAG_RD, &asids.asid_bits, 0, 359 "The number of bits in an ASID"); 360 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, next, CTLFLAG_RD, &asids.asid_next, 0, 361 "The last allocated ASID plus one"); 362 SYSCTL_INT(_vm_pmap_asid, OID_AUTO, epoch, CTLFLAG_RD, &asids.asid_epoch, 0, 363 "The current epoch number"); 364 365 static SYSCTL_NODE(_vm_pmap, OID_AUTO, vmid, CTLFLAG_RD, 0, "VMID allocator"); 366 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, bits, CTLFLAG_RD, &vmids.asid_bits, 0, 367 "The number of bits in an VMID"); 368 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, next, CTLFLAG_RD, &vmids.asid_next, 0, 369 "The last allocated VMID plus one"); 370 SYSCTL_INT(_vm_pmap_vmid, OID_AUTO, epoch, CTLFLAG_RD, &vmids.asid_epoch, 0, 371 "The current epoch number"); 372 373 void (*pmap_clean_stage2_tlbi)(void); 374 void (*pmap_invalidate_vpipt_icache)(void); 375 376 /* 377 * A pmap's cookie encodes an ASID and epoch number. Cookies for reserved 378 * ASIDs have a negative epoch number, specifically, INT_MIN. Cookies for 379 * dynamically allocated ASIDs have a non-negative epoch number. 380 * 381 * An invalid ASID is represented by -1. 382 * 383 * There are two special-case cookie values: (1) COOKIE_FROM(-1, INT_MIN), 384 * which indicates that an ASID should never be allocated to the pmap, and 385 * (2) COOKIE_FROM(-1, INT_MAX), which indicates that an ASID should be 386 * allocated when the pmap is next activated. 387 */ 388 #define COOKIE_FROM(asid, epoch) ((long)((u_int)(asid) | \ 389 ((u_long)(epoch) << 32))) 390 #define COOKIE_TO_ASID(cookie) ((int)(cookie)) 391 #define COOKIE_TO_EPOCH(cookie) ((int)((u_long)(cookie) >> 32)) 392 393 #define TLBI_VA_SHIFT 12 394 #define TLBI_VA_MASK ((1ul << 44) - 1) 395 #define TLBI_VA(addr) (((addr) >> TLBI_VA_SHIFT) & TLBI_VA_MASK) 396 #define TLBI_VA_L3_INCR (L3_SIZE >> TLBI_VA_SHIFT) 397 398 static int superpages_enabled = 1; 399 SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled, 400 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0, 401 "Are large page mappings enabled?"); 402 403 /* 404 * Internal flags for pmap_enter()'s helper functions. 405 */ 406 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */ 407 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */ 408 409 TAILQ_HEAD(pv_chunklist, pv_chunk); 410 411 static void free_pv_chunk(struct pv_chunk *pc); 412 static void free_pv_chunk_batch(struct pv_chunklist *batch); 413 static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 414 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp); 415 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp); 416 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 417 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 418 vm_offset_t va); 419 420 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte); 421 static bool pmap_activate_int(pmap_t pmap); 422 static void pmap_alloc_asid(pmap_t pmap); 423 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size, 424 vm_prot_t prot, int mode, bool skip_unmapped); 425 static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va); 426 static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, 427 vm_offset_t va, struct rwlock **lockp); 428 static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va); 429 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 430 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp); 431 static int pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, 432 u_int flags, vm_page_t m, struct rwlock **lockp); 433 static int pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, 434 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp); 435 static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva, 436 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp); 437 static void pmap_reset_asid_set(pmap_t pmap); 438 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 439 vm_page_t m, struct rwlock **lockp); 440 441 static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, 442 struct rwlock **lockp); 443 444 static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, 445 struct spglist *free); 446 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *); 447 static __inline vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va); 448 449 /* 450 * These load the old table data and store the new value. 451 * They need to be atomic as the System MMU may write to the table at 452 * the same time as the CPU. 453 */ 454 #define pmap_clear(table) atomic_store_64(table, 0) 455 #define pmap_clear_bits(table, bits) atomic_clear_64(table, bits) 456 #define pmap_load(table) (*table) 457 #define pmap_load_clear(table) atomic_swap_64(table, 0) 458 #define pmap_load_store(table, entry) atomic_swap_64(table, entry) 459 #define pmap_set_bits(table, bits) atomic_set_64(table, bits) 460 #define pmap_store(table, entry) atomic_store_64(table, entry) 461 462 /********************/ 463 /* Inline functions */ 464 /********************/ 465 466 static __inline void 467 pagecopy(void *s, void *d) 468 { 469 470 memcpy(d, s, PAGE_SIZE); 471 } 472 473 static __inline pd_entry_t * 474 pmap_l0(pmap_t pmap, vm_offset_t va) 475 { 476 477 return (&pmap->pm_l0[pmap_l0_index(va)]); 478 } 479 480 static __inline pd_entry_t * 481 pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va) 482 { 483 pd_entry_t *l1; 484 485 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK); 486 return (&l1[pmap_l1_index(va)]); 487 } 488 489 static __inline pd_entry_t * 490 pmap_l1(pmap_t pmap, vm_offset_t va) 491 { 492 pd_entry_t *l0; 493 494 l0 = pmap_l0(pmap, va); 495 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE) 496 return (NULL); 497 498 return (pmap_l0_to_l1(l0, va)); 499 } 500 501 static __inline pd_entry_t * 502 pmap_l1_to_l2(pd_entry_t *l1p, vm_offset_t va) 503 { 504 pd_entry_t l1, *l2p; 505 506 l1 = pmap_load(l1p); 507 508 KASSERT(ADDR_IS_CANONICAL(va), 509 ("%s: Address not in canonical form: %lx", __func__, va)); 510 /* 511 * The valid bit may be clear if pmap_update_entry() is concurrently 512 * modifying the entry, so for KVA only the entry type may be checked. 513 */ 514 KASSERT(ADDR_IS_KERNEL(va) || (l1 & ATTR_DESCR_VALID) != 0, 515 ("%s: L1 entry %#lx for %#lx is invalid", __func__, l1, va)); 516 KASSERT((l1 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE, 517 ("%s: L1 entry %#lx for %#lx is a leaf", __func__, l1, va)); 518 l2p = (pd_entry_t *)PHYS_TO_DMAP(l1 & ~ATTR_MASK); 519 return (&l2p[pmap_l2_index(va)]); 520 } 521 522 static __inline pd_entry_t * 523 pmap_l2(pmap_t pmap, vm_offset_t va) 524 { 525 pd_entry_t *l1; 526 527 l1 = pmap_l1(pmap, va); 528 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE) 529 return (NULL); 530 531 return (pmap_l1_to_l2(l1, va)); 532 } 533 534 static __inline pt_entry_t * 535 pmap_l2_to_l3(pd_entry_t *l2p, vm_offset_t va) 536 { 537 pd_entry_t l2; 538 pt_entry_t *l3p; 539 540 l2 = pmap_load(l2p); 541 542 KASSERT(ADDR_IS_CANONICAL(va), 543 ("%s: Address not in canonical form: %lx", __func__, va)); 544 /* 545 * The valid bit may be clear if pmap_update_entry() is concurrently 546 * modifying the entry, so for KVA only the entry type may be checked. 547 */ 548 KASSERT(ADDR_IS_KERNEL(va) || (l2 & ATTR_DESCR_VALID) != 0, 549 ("%s: L2 entry %#lx for %#lx is invalid", __func__, l2, va)); 550 KASSERT((l2 & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_TABLE, 551 ("%s: L2 entry %#lx for %#lx is a leaf", __func__, l2, va)); 552 l3p = (pt_entry_t *)PHYS_TO_DMAP(l2 & ~ATTR_MASK); 553 return (&l3p[pmap_l3_index(va)]); 554 } 555 556 /* 557 * Returns the lowest valid pde for a given virtual address. 558 * The next level may or may not point to a valid page or block. 559 */ 560 static __inline pd_entry_t * 561 pmap_pde(pmap_t pmap, vm_offset_t va, int *level) 562 { 563 pd_entry_t *l0, *l1, *l2, desc; 564 565 l0 = pmap_l0(pmap, va); 566 desc = pmap_load(l0) & ATTR_DESCR_MASK; 567 if (desc != L0_TABLE) { 568 *level = -1; 569 return (NULL); 570 } 571 572 l1 = pmap_l0_to_l1(l0, va); 573 desc = pmap_load(l1) & ATTR_DESCR_MASK; 574 if (desc != L1_TABLE) { 575 *level = 0; 576 return (l0); 577 } 578 579 l2 = pmap_l1_to_l2(l1, va); 580 desc = pmap_load(l2) & ATTR_DESCR_MASK; 581 if (desc != L2_TABLE) { 582 *level = 1; 583 return (l1); 584 } 585 586 *level = 2; 587 return (l2); 588 } 589 590 /* 591 * Returns the lowest valid pte block or table entry for a given virtual 592 * address. If there are no valid entries return NULL and set the level to 593 * the first invalid level. 594 */ 595 static __inline pt_entry_t * 596 pmap_pte(pmap_t pmap, vm_offset_t va, int *level) 597 { 598 pd_entry_t *l1, *l2, desc; 599 pt_entry_t *l3; 600 601 l1 = pmap_l1(pmap, va); 602 if (l1 == NULL) { 603 *level = 0; 604 return (NULL); 605 } 606 desc = pmap_load(l1) & ATTR_DESCR_MASK; 607 if (desc == L1_BLOCK) { 608 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 609 *level = 1; 610 return (l1); 611 } 612 613 if (desc != L1_TABLE) { 614 *level = 1; 615 return (NULL); 616 } 617 618 l2 = pmap_l1_to_l2(l1, va); 619 desc = pmap_load(l2) & ATTR_DESCR_MASK; 620 if (desc == L2_BLOCK) { 621 *level = 2; 622 return (l2); 623 } 624 625 if (desc != L2_TABLE) { 626 *level = 2; 627 return (NULL); 628 } 629 630 *level = 3; 631 l3 = pmap_l2_to_l3(l2, va); 632 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE) 633 return (NULL); 634 635 return (l3); 636 } 637 638 /* 639 * If the given pmap has an L{1,2}_BLOCK or L3_PAGE entry at the specified 640 * level that maps the specified virtual address, then a pointer to that entry 641 * is returned. Otherwise, NULL is returned, unless INVARIANTS are enabled 642 * and a diagnostic message is provided, in which case this function panics. 643 */ 644 static __always_inline pt_entry_t * 645 pmap_pte_exists(pmap_t pmap, vm_offset_t va, int level, const char *diag) 646 { 647 pd_entry_t *l0p, *l1p, *l2p; 648 pt_entry_t desc, *l3p; 649 int walk_level __diagused; 650 651 KASSERT(level >= 0 && level < 4, 652 ("%s: %s passed an out-of-range level (%d)", __func__, diag, 653 level)); 654 l0p = pmap_l0(pmap, va); 655 desc = pmap_load(l0p) & ATTR_DESCR_MASK; 656 if (desc == L0_TABLE && level > 0) { 657 l1p = pmap_l0_to_l1(l0p, va); 658 desc = pmap_load(l1p) & ATTR_DESCR_MASK; 659 if (desc == L1_BLOCK && level == 1) { 660 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 661 return (l1p); 662 } 663 if (desc == L1_TABLE && level > 1) { 664 l2p = pmap_l1_to_l2(l1p, va); 665 desc = pmap_load(l2p) & ATTR_DESCR_MASK; 666 if (desc == L2_BLOCK && level == 2) 667 return (l2p); 668 else if (desc == L2_TABLE && level > 2) { 669 l3p = pmap_l2_to_l3(l2p, va); 670 desc = pmap_load(l3p) & ATTR_DESCR_MASK; 671 if (desc == L3_PAGE && level == 3) 672 return (l3p); 673 else 674 walk_level = 3; 675 } else 676 walk_level = 2; 677 } else 678 walk_level = 1; 679 } else 680 walk_level = 0; 681 KASSERT(diag == NULL, 682 ("%s: va %#lx not mapped at level %d, desc %ld at level %d", 683 diag, va, level, desc, walk_level)); 684 return (NULL); 685 } 686 687 bool 688 pmap_ps_enabled(pmap_t pmap __unused) 689 { 690 691 return (superpages_enabled != 0); 692 } 693 694 bool 695 pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1, 696 pd_entry_t **l2, pt_entry_t **l3) 697 { 698 pd_entry_t *l0p, *l1p, *l2p; 699 700 if (pmap->pm_l0 == NULL) 701 return (false); 702 703 l0p = pmap_l0(pmap, va); 704 *l0 = l0p; 705 706 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE) 707 return (false); 708 709 l1p = pmap_l0_to_l1(l0p, va); 710 *l1 = l1p; 711 712 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) { 713 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 714 *l2 = NULL; 715 *l3 = NULL; 716 return (true); 717 } 718 719 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE) 720 return (false); 721 722 l2p = pmap_l1_to_l2(l1p, va); 723 *l2 = l2p; 724 725 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) { 726 *l3 = NULL; 727 return (true); 728 } 729 730 if ((pmap_load(l2p) & ATTR_DESCR_MASK) != L2_TABLE) 731 return (false); 732 733 *l3 = pmap_l2_to_l3(l2p, va); 734 735 return (true); 736 } 737 738 static __inline int 739 pmap_l3_valid(pt_entry_t l3) 740 { 741 742 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE); 743 } 744 745 CTASSERT(L1_BLOCK == L2_BLOCK); 746 747 static pt_entry_t 748 pmap_pte_memattr(pmap_t pmap, vm_memattr_t memattr) 749 { 750 pt_entry_t val; 751 752 if (pmap->pm_stage == PM_STAGE1) { 753 val = ATTR_S1_IDX(memattr); 754 if (memattr == VM_MEMATTR_DEVICE) 755 val |= ATTR_S1_XN; 756 return (val); 757 } 758 759 val = 0; 760 761 switch (memattr) { 762 case VM_MEMATTR_DEVICE: 763 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_DEVICE_nGnRnE) | 764 ATTR_S2_XN(ATTR_S2_XN_ALL)); 765 case VM_MEMATTR_UNCACHEABLE: 766 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_NC)); 767 case VM_MEMATTR_WRITE_BACK: 768 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WB)); 769 case VM_MEMATTR_WRITE_THROUGH: 770 return (ATTR_S2_MEMATTR(ATTR_S2_MEMATTR_WT)); 771 default: 772 panic("%s: invalid memory attribute %x", __func__, memattr); 773 } 774 } 775 776 static pt_entry_t 777 pmap_pte_prot(pmap_t pmap, vm_prot_t prot) 778 { 779 pt_entry_t val; 780 781 val = 0; 782 if (pmap->pm_stage == PM_STAGE1) { 783 if ((prot & VM_PROT_EXECUTE) == 0) 784 val |= ATTR_S1_XN; 785 if ((prot & VM_PROT_WRITE) == 0) 786 val |= ATTR_S1_AP(ATTR_S1_AP_RO); 787 } else { 788 if ((prot & VM_PROT_WRITE) != 0) 789 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE); 790 if ((prot & VM_PROT_READ) != 0) 791 val |= ATTR_S2_S2AP(ATTR_S2_S2AP_READ); 792 if ((prot & VM_PROT_EXECUTE) == 0) 793 val |= ATTR_S2_XN(ATTR_S2_XN_ALL); 794 } 795 796 return (val); 797 } 798 799 /* 800 * Checks if the PTE is dirty. 801 */ 802 static inline int 803 pmap_pte_dirty(pmap_t pmap, pt_entry_t pte) 804 { 805 806 KASSERT((pte & ATTR_SW_MANAGED) != 0, ("pte %#lx is unmanaged", pte)); 807 808 if (pmap->pm_stage == PM_STAGE1) { 809 KASSERT((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 0, 810 ("pte %#lx is writeable and missing ATTR_SW_DBM", pte)); 811 812 return ((pte & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == 813 (ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_SW_DBM)); 814 } 815 816 return ((pte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) == 817 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)); 818 } 819 820 static __inline void 821 pmap_resident_count_inc(pmap_t pmap, int count) 822 { 823 824 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 825 pmap->pm_stats.resident_count += count; 826 } 827 828 static __inline void 829 pmap_resident_count_dec(pmap_t pmap, int count) 830 { 831 832 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 833 KASSERT(pmap->pm_stats.resident_count >= count, 834 ("pmap %p resident count underflow %ld %d", pmap, 835 pmap->pm_stats.resident_count, count)); 836 pmap->pm_stats.resident_count -= count; 837 } 838 839 static vm_paddr_t 840 pmap_early_vtophys(vm_offset_t va) 841 { 842 vm_paddr_t pa_page; 843 844 pa_page = arm64_address_translate_s1e1r(va) & PAR_PA_MASK; 845 return (pa_page | (va & PAR_LOW_MASK)); 846 } 847 848 /* State of the bootstrapped DMAP page tables */ 849 struct pmap_bootstrap_state { 850 pt_entry_t *l1; 851 pt_entry_t *l2; 852 pt_entry_t *l3; 853 vm_offset_t freemempos; 854 vm_offset_t va; 855 vm_paddr_t pa; 856 pt_entry_t table_attrs; 857 u_int l0_slot; 858 u_int l1_slot; 859 u_int l2_slot; 860 bool dmap_valid; 861 }; 862 863 /* The bootstrap state */ 864 static struct pmap_bootstrap_state bs_state = { 865 .l1 = NULL, 866 .l2 = NULL, 867 .l3 = NULL, 868 .table_attrs = TATTR_PXN_TABLE, 869 .l0_slot = L0_ENTRIES, 870 .l1_slot = Ln_ENTRIES, 871 .l2_slot = Ln_ENTRIES, 872 .dmap_valid = false, 873 }; 874 875 static void 876 pmap_bootstrap_l0_table(struct pmap_bootstrap_state *state) 877 { 878 vm_paddr_t l1_pa; 879 pd_entry_t l0e; 880 u_int l0_slot; 881 882 /* Link the level 0 table to a level 1 table */ 883 l0_slot = pmap_l0_index(state->va); 884 if (l0_slot != state->l0_slot) { 885 /* 886 * Make sure we move from a low address to high address 887 * before the DMAP region is ready. This ensures we never 888 * modify an existing mapping until we can map from a 889 * physical address to a virtual address. 890 */ 891 MPASS(state->l0_slot < l0_slot || 892 state->l0_slot == L0_ENTRIES || 893 state->dmap_valid); 894 895 /* Reset lower levels */ 896 state->l2 = NULL; 897 state->l3 = NULL; 898 state->l1_slot = Ln_ENTRIES; 899 state->l2_slot = Ln_ENTRIES; 900 901 /* Check the existing L0 entry */ 902 state->l0_slot = l0_slot; 903 if (state->dmap_valid) { 904 l0e = pagetable_l0_ttbr1[l0_slot]; 905 if ((l0e & ATTR_DESCR_VALID) != 0) { 906 MPASS((l0e & ATTR_DESCR_MASK) == L0_TABLE); 907 l1_pa = l0e & ~ATTR_MASK; 908 state->l1 = (pt_entry_t *)PHYS_TO_DMAP(l1_pa); 909 return; 910 } 911 } 912 913 /* Create a new L0 table entry */ 914 state->l1 = (pt_entry_t *)state->freemempos; 915 memset(state->l1, 0, PAGE_SIZE); 916 state->freemempos += PAGE_SIZE; 917 918 l1_pa = pmap_early_vtophys((vm_offset_t)state->l1); 919 MPASS((l1_pa & Ln_TABLE_MASK) == 0); 920 MPASS(pagetable_l0_ttbr1[l0_slot] == 0); 921 pmap_store(&pagetable_l0_ttbr1[l0_slot], l1_pa | 922 TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0 | L0_TABLE); 923 } 924 KASSERT(state->l1 != NULL, ("%s: NULL l1", __func__)); 925 } 926 927 static void 928 pmap_bootstrap_l1_table(struct pmap_bootstrap_state *state) 929 { 930 vm_paddr_t l2_pa; 931 pd_entry_t l1e; 932 u_int l1_slot; 933 934 /* Make sure there is a valid L0 -> L1 table */ 935 pmap_bootstrap_l0_table(state); 936 937 /* Link the level 1 table to a level 2 table */ 938 l1_slot = pmap_l1_index(state->va); 939 if (l1_slot != state->l1_slot) { 940 /* See pmap_bootstrap_l0_table for a description */ 941 MPASS(state->l1_slot < l1_slot || 942 state->l1_slot == Ln_ENTRIES || 943 state->dmap_valid); 944 945 /* Reset lower levels */ 946 state->l3 = NULL; 947 state->l2_slot = Ln_ENTRIES; 948 949 /* Check the existing L1 entry */ 950 state->l1_slot = l1_slot; 951 if (state->dmap_valid) { 952 l1e = state->l1[l1_slot]; 953 if ((l1e & ATTR_DESCR_VALID) != 0) { 954 MPASS((l1e & ATTR_DESCR_MASK) == L1_TABLE); 955 l2_pa = l1e & ~ATTR_MASK; 956 state->l2 = (pt_entry_t *)PHYS_TO_DMAP(l2_pa); 957 return; 958 } 959 } 960 961 /* Create a new L1 table entry */ 962 state->l2 = (pt_entry_t *)state->freemempos; 963 memset(state->l2, 0, PAGE_SIZE); 964 state->freemempos += PAGE_SIZE; 965 966 l2_pa = pmap_early_vtophys((vm_offset_t)state->l2); 967 MPASS((l2_pa & Ln_TABLE_MASK) == 0); 968 MPASS(state->l1[l1_slot] == 0); 969 pmap_store(&state->l1[l1_slot], l2_pa | state->table_attrs | 970 L1_TABLE); 971 } 972 KASSERT(state->l2 != NULL, ("%s: NULL l2", __func__)); 973 } 974 975 static void 976 pmap_bootstrap_l2_table(struct pmap_bootstrap_state *state) 977 { 978 vm_paddr_t l3_pa; 979 pd_entry_t l2e; 980 u_int l2_slot; 981 982 /* Make sure there is a valid L1 -> L2 table */ 983 pmap_bootstrap_l1_table(state); 984 985 /* Link the level 2 table to a level 3 table */ 986 l2_slot = pmap_l2_index(state->va); 987 if (l2_slot != state->l2_slot) { 988 /* See pmap_bootstrap_l0_table for a description */ 989 MPASS(state->l2_slot < l2_slot || 990 state->l2_slot == Ln_ENTRIES || 991 state->dmap_valid); 992 993 /* Check the existing L2 entry */ 994 state->l2_slot = l2_slot; 995 if (state->dmap_valid) { 996 l2e = state->l2[l2_slot]; 997 if ((l2e & ATTR_DESCR_VALID) != 0) { 998 MPASS((l2e & ATTR_DESCR_MASK) == L2_TABLE); 999 l3_pa = l2e & ~ATTR_MASK; 1000 state->l3 = (pt_entry_t *)PHYS_TO_DMAP(l3_pa); 1001 return; 1002 } 1003 } 1004 1005 /* Create a new L2 table entry */ 1006 state->l3 = (pt_entry_t *)state->freemempos; 1007 memset(state->l3, 0, PAGE_SIZE); 1008 state->freemempos += PAGE_SIZE; 1009 1010 l3_pa = pmap_early_vtophys((vm_offset_t)state->l3); 1011 MPASS((l3_pa & Ln_TABLE_MASK) == 0); 1012 MPASS(state->l2[l2_slot] == 0); 1013 pmap_store(&state->l2[l2_slot], l3_pa | state->table_attrs | 1014 L2_TABLE); 1015 } 1016 KASSERT(state->l3 != NULL, ("%s: NULL l3", __func__)); 1017 } 1018 1019 static void 1020 pmap_bootstrap_l2_block(struct pmap_bootstrap_state *state, int i) 1021 { 1022 u_int l2_slot; 1023 bool first; 1024 1025 if ((physmap[i + 1] - state->pa) < L2_SIZE) 1026 return; 1027 1028 /* Make sure there is a valid L1 table */ 1029 pmap_bootstrap_l1_table(state); 1030 1031 MPASS((state->va & L2_OFFSET) == 0); 1032 for (first = true; 1033 state->va < DMAP_MAX_ADDRESS && 1034 (physmap[i + 1] - state->pa) >= L2_SIZE; 1035 state->va += L2_SIZE, state->pa += L2_SIZE) { 1036 /* 1037 * Stop if we are about to walk off the end of what the 1038 * current L1 slot can address. 1039 */ 1040 if (!first && (state->pa & L1_OFFSET) == 0) 1041 break; 1042 1043 first = false; 1044 l2_slot = pmap_l2_index(state->va); 1045 MPASS((state->pa & L2_OFFSET) == 0); 1046 MPASS(state->l2[l2_slot] == 0); 1047 pmap_store(&state->l2[l2_slot], state->pa | ATTR_DEFAULT | 1048 ATTR_S1_XN | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | 1049 L2_BLOCK); 1050 } 1051 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS)); 1052 } 1053 1054 static void 1055 pmap_bootstrap_l3_page(struct pmap_bootstrap_state *state, int i) 1056 { 1057 u_int l3_slot; 1058 bool first; 1059 1060 if ((physmap[i + 1] - state->pa) < L3_SIZE) 1061 return; 1062 1063 /* Make sure there is a valid L2 table */ 1064 pmap_bootstrap_l2_table(state); 1065 1066 MPASS((state->va & L3_OFFSET) == 0); 1067 for (first = true; 1068 state->va < DMAP_MAX_ADDRESS && 1069 (physmap[i + 1] - state->pa) >= L3_SIZE; 1070 state->va += L3_SIZE, state->pa += L3_SIZE) { 1071 /* 1072 * Stop if we are about to walk off the end of what the 1073 * current L2 slot can address. 1074 */ 1075 if (!first && (state->pa & L2_OFFSET) == 0) 1076 break; 1077 1078 first = false; 1079 l3_slot = pmap_l3_index(state->va); 1080 MPASS((state->pa & L3_OFFSET) == 0); 1081 MPASS(state->l3[l3_slot] == 0); 1082 pmap_store(&state->l3[l3_slot], state->pa | ATTR_DEFAULT | 1083 ATTR_S1_XN | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | 1084 L3_PAGE); 1085 } 1086 MPASS(state->va == (state->pa - dmap_phys_base + DMAP_MIN_ADDRESS)); 1087 } 1088 1089 static void 1090 pmap_bootstrap_dmap(vm_paddr_t min_pa) 1091 { 1092 int i; 1093 1094 dmap_phys_base = min_pa & ~L1_OFFSET; 1095 dmap_phys_max = 0; 1096 dmap_max_addr = 0; 1097 1098 for (i = 0; i < (physmap_idx * 2); i += 2) { 1099 bs_state.pa = physmap[i] & ~L3_OFFSET; 1100 bs_state.va = bs_state.pa - dmap_phys_base + DMAP_MIN_ADDRESS; 1101 1102 /* Create L3 mappings at the start of the region */ 1103 if ((bs_state.pa & L2_OFFSET) != 0) 1104 pmap_bootstrap_l3_page(&bs_state, i); 1105 MPASS(bs_state.pa <= physmap[i + 1]); 1106 1107 if (L1_BLOCKS_SUPPORTED) { 1108 /* Create L2 mappings at the start of the region */ 1109 if ((bs_state.pa & L1_OFFSET) != 0) 1110 pmap_bootstrap_l2_block(&bs_state, i); 1111 MPASS(bs_state.pa <= physmap[i + 1]); 1112 1113 /* Create the main L1 block mappings */ 1114 for (; bs_state.va < DMAP_MAX_ADDRESS && 1115 (physmap[i + 1] - bs_state.pa) >= L1_SIZE; 1116 bs_state.va += L1_SIZE, bs_state.pa += L1_SIZE) { 1117 /* Make sure there is a valid L1 table */ 1118 pmap_bootstrap_l0_table(&bs_state); 1119 MPASS((bs_state.pa & L1_OFFSET) == 0); 1120 pmap_store( 1121 &bs_state.l1[pmap_l1_index(bs_state.va)], 1122 bs_state.pa | ATTR_DEFAULT | ATTR_S1_XN | 1123 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | 1124 L1_BLOCK); 1125 } 1126 MPASS(bs_state.pa <= physmap[i + 1]); 1127 1128 /* Create L2 mappings at the end of the region */ 1129 pmap_bootstrap_l2_block(&bs_state, i); 1130 } else { 1131 while (bs_state.va < DMAP_MAX_ADDRESS && 1132 (physmap[i + 1] - bs_state.pa) >= L2_SIZE) { 1133 pmap_bootstrap_l2_block(&bs_state, i); 1134 } 1135 } 1136 MPASS(bs_state.pa <= physmap[i + 1]); 1137 1138 /* Create L3 mappings at the end of the region */ 1139 pmap_bootstrap_l3_page(&bs_state, i); 1140 MPASS(bs_state.pa == physmap[i + 1]); 1141 1142 if (bs_state.pa > dmap_phys_max) { 1143 dmap_phys_max = bs_state.pa; 1144 dmap_max_addr = bs_state.va; 1145 } 1146 } 1147 1148 cpu_tlb_flushID(); 1149 } 1150 1151 static void 1152 pmap_bootstrap_l2(vm_offset_t va) 1153 { 1154 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address")); 1155 1156 /* Leave bs_state.pa as it's only needed to bootstrap blocks and pages*/ 1157 bs_state.va = va; 1158 1159 for (; bs_state.va < VM_MAX_KERNEL_ADDRESS; bs_state.va += L1_SIZE) 1160 pmap_bootstrap_l1_table(&bs_state); 1161 } 1162 1163 static void 1164 pmap_bootstrap_l3(vm_offset_t va) 1165 { 1166 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address")); 1167 1168 /* Leave bs_state.pa as it's only needed to bootstrap blocks and pages*/ 1169 bs_state.va = va; 1170 1171 for (; bs_state.va < VM_MAX_KERNEL_ADDRESS; bs_state.va += L2_SIZE) 1172 pmap_bootstrap_l2_table(&bs_state); 1173 } 1174 1175 /* 1176 * Bootstrap the system enough to run with virtual memory. 1177 */ 1178 void 1179 pmap_bootstrap(vm_paddr_t kernstart, vm_size_t kernlen) 1180 { 1181 vm_offset_t dpcpu, msgbufpv; 1182 vm_paddr_t start_pa, pa, min_pa; 1183 uint64_t kern_delta; 1184 int i; 1185 1186 /* Verify that the ASID is set through TTBR0. */ 1187 KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0, 1188 ("pmap_bootstrap: TCR_EL1.A1 != 0")); 1189 1190 kern_delta = KERNBASE - kernstart; 1191 1192 printf("pmap_bootstrap %lx %lx\n", kernstart, kernlen); 1193 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK); 1194 1195 /* Set this early so we can use the pagetable walking functions */ 1196 kernel_pmap_store.pm_l0 = pagetable_l0_ttbr1; 1197 PMAP_LOCK_INIT(kernel_pmap); 1198 kernel_pmap->pm_l0_paddr = 1199 pmap_early_vtophys((vm_offset_t)kernel_pmap_store.pm_l0); 1200 kernel_pmap->pm_cookie = COOKIE_FROM(-1, INT_MIN); 1201 kernel_pmap->pm_stage = PM_STAGE1; 1202 kernel_pmap->pm_levels = 4; 1203 kernel_pmap->pm_ttbr = kernel_pmap->pm_l0_paddr; 1204 kernel_pmap->pm_asid_set = &asids; 1205 1206 /* Assume the address we were loaded to is a valid physical address */ 1207 min_pa = KERNBASE - kern_delta; 1208 1209 physmap_idx = physmem_avail(physmap, nitems(physmap)); 1210 physmap_idx /= 2; 1211 1212 /* 1213 * Find the minimum physical address. physmap is sorted, 1214 * but may contain empty ranges. 1215 */ 1216 for (i = 0; i < physmap_idx * 2; i += 2) { 1217 if (physmap[i] == physmap[i + 1]) 1218 continue; 1219 if (physmap[i] <= min_pa) 1220 min_pa = physmap[i]; 1221 } 1222 1223 bs_state.freemempos = KERNBASE + kernlen; 1224 bs_state.freemempos = roundup2(bs_state.freemempos, PAGE_SIZE); 1225 1226 /* Create a direct map region early so we can use it for pa -> va */ 1227 pmap_bootstrap_dmap(min_pa); 1228 bs_state.dmap_valid = true; 1229 /* 1230 * We only use PXN when we know nothing will be executed from it, e.g. 1231 * the DMAP region. 1232 */ 1233 bs_state.table_attrs &= ~TATTR_PXN_TABLE; 1234 1235 start_pa = pa = KERNBASE - kern_delta; 1236 1237 /* 1238 * Create the l2 tables up to VM_MAX_KERNEL_ADDRESS. We assume that the 1239 * loader allocated the first and only l2 page table page used to map 1240 * the kernel, preloaded files and module metadata. 1241 */ 1242 pmap_bootstrap_l2(KERNBASE + L1_SIZE); 1243 /* And the l3 tables for the early devmap */ 1244 pmap_bootstrap_l3(VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE)); 1245 1246 cpu_tlb_flushID(); 1247 1248 #define alloc_pages(var, np) \ 1249 (var) = bs_state.freemempos; \ 1250 bs_state.freemempos += (np * PAGE_SIZE); \ 1251 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 1252 1253 /* Allocate dynamic per-cpu area. */ 1254 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 1255 dpcpu_init((void *)dpcpu, 0); 1256 1257 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */ 1258 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 1259 msgbufp = (void *)msgbufpv; 1260 1261 /* Reserve some VA space for early BIOS/ACPI mapping */ 1262 preinit_map_va = roundup2(bs_state.freemempos, L2_SIZE); 1263 1264 virtual_avail = preinit_map_va + PMAP_PREINIT_MAPPING_SIZE; 1265 virtual_avail = roundup2(virtual_avail, L1_SIZE); 1266 virtual_end = VM_MAX_KERNEL_ADDRESS - (PMAP_MAPDEV_EARLY_SIZE); 1267 kernel_vm_end = virtual_avail; 1268 1269 pa = pmap_early_vtophys(bs_state.freemempos); 1270 1271 physmem_exclude_region(start_pa, pa - start_pa, EXFLAG_NOALLOC); 1272 1273 cpu_tlb_flushID(); 1274 } 1275 1276 /* 1277 * Initialize a vm_page's machine-dependent fields. 1278 */ 1279 void 1280 pmap_page_init(vm_page_t m) 1281 { 1282 1283 TAILQ_INIT(&m->md.pv_list); 1284 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK; 1285 } 1286 1287 static void 1288 pmap_init_asids(struct asid_set *set, int bits) 1289 { 1290 int i; 1291 1292 set->asid_bits = bits; 1293 1294 /* 1295 * We may be too early in the overall initialization process to use 1296 * bit_alloc(). 1297 */ 1298 set->asid_set_size = 1 << set->asid_bits; 1299 set->asid_set = kmem_malloc(bitstr_size(set->asid_set_size), 1300 M_WAITOK | M_ZERO); 1301 for (i = 0; i < ASID_FIRST_AVAILABLE; i++) 1302 bit_set(set->asid_set, i); 1303 set->asid_next = ASID_FIRST_AVAILABLE; 1304 mtx_init(&set->asid_set_mutex, "asid set", NULL, MTX_SPIN); 1305 } 1306 1307 /* 1308 * Initialize the pmap module. 1309 * Called by vm_init, to initialize any structures that the pmap 1310 * system needs to map virtual memory. 1311 */ 1312 void 1313 pmap_init(void) 1314 { 1315 struct vm_phys_seg *seg, *next_seg; 1316 struct md_page *pvh; 1317 vm_size_t s; 1318 uint64_t mmfr1; 1319 int i, pv_npg, vmid_bits; 1320 1321 /* 1322 * Are large page mappings enabled? 1323 */ 1324 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled); 1325 if (superpages_enabled) { 1326 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 1327 ("pmap_init: can't assign to pagesizes[1]")); 1328 pagesizes[1] = L2_SIZE; 1329 if (L1_BLOCKS_SUPPORTED) { 1330 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0, 1331 ("pmap_init: can't assign to pagesizes[2]")); 1332 pagesizes[2] = L1_SIZE; 1333 } 1334 } 1335 1336 /* 1337 * Initialize the ASID allocator. 1338 */ 1339 pmap_init_asids(&asids, 1340 (READ_SPECIALREG(tcr_el1) & TCR_ASID_16) != 0 ? 16 : 8); 1341 1342 if (has_hyp()) { 1343 mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1); 1344 vmid_bits = 8; 1345 1346 if (ID_AA64MMFR1_VMIDBits_VAL(mmfr1) == 1347 ID_AA64MMFR1_VMIDBits_16) 1348 vmid_bits = 16; 1349 pmap_init_asids(&vmids, vmid_bits); 1350 } 1351 1352 /* 1353 * Initialize pv chunk lists. 1354 */ 1355 for (i = 0; i < PMAP_MEMDOM; i++) { 1356 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, 1357 MTX_DEF); 1358 TAILQ_INIT(&pv_chunks[i].pvc_list); 1359 } 1360 1361 /* 1362 * Initialize the pool of pv list locks. 1363 */ 1364 for (i = 0; i < NPV_LIST_LOCKS; i++) 1365 rw_init(&pv_list_locks[i], "pmap pv list"); 1366 1367 /* 1368 * Calculate the size of the pv head table for superpages. 1369 */ 1370 pv_npg = 0; 1371 for (i = 0; i < vm_phys_nsegs; i++) { 1372 seg = &vm_phys_segs[i]; 1373 pv_npg += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1374 pmap_l2_pindex(seg->start); 1375 } 1376 1377 /* 1378 * Allocate memory for the pv head table for superpages. 1379 */ 1380 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 1381 s = round_page(s); 1382 pv_table = kmem_malloc(s, M_WAITOK | M_ZERO); 1383 for (i = 0; i < pv_npg; i++) 1384 TAILQ_INIT(&pv_table[i].pv_list); 1385 TAILQ_INIT(&pv_dummy.pv_list); 1386 1387 /* 1388 * Set pointers from vm_phys_segs to pv_table. 1389 */ 1390 for (i = 0, pvh = pv_table; i < vm_phys_nsegs; i++) { 1391 seg = &vm_phys_segs[i]; 1392 seg->md_first = pvh; 1393 pvh += pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1394 pmap_l2_pindex(seg->start); 1395 1396 /* 1397 * If there is a following segment, and the final 1398 * superpage of this segment and the initial superpage 1399 * of the next segment are the same then adjust the 1400 * pv_table entry for that next segment down by one so 1401 * that the pv_table entries will be shared. 1402 */ 1403 if (i + 1 < vm_phys_nsegs) { 1404 next_seg = &vm_phys_segs[i + 1]; 1405 if (pmap_l2_pindex(roundup2(seg->end, L2_SIZE)) - 1 == 1406 pmap_l2_pindex(next_seg->start)) { 1407 pvh--; 1408 } 1409 } 1410 } 1411 1412 vm_initialized = 1; 1413 } 1414 1415 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 1416 "2MB page mapping counters"); 1417 1418 static u_long pmap_l2_demotions; 1419 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD, 1420 &pmap_l2_demotions, 0, "2MB page demotions"); 1421 1422 static u_long pmap_l2_mappings; 1423 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, mappings, CTLFLAG_RD, 1424 &pmap_l2_mappings, 0, "2MB page mappings"); 1425 1426 static u_long pmap_l2_p_failures; 1427 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD, 1428 &pmap_l2_p_failures, 0, "2MB page promotion failures"); 1429 1430 static u_long pmap_l2_promotions; 1431 SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD, 1432 &pmap_l2_promotions, 0, "2MB page promotions"); 1433 1434 /* 1435 * If the given value for "final_only" is false, then any cached intermediate- 1436 * level entries, i.e., L{0,1,2}_TABLE entries, are invalidated in addition to 1437 * any cached final-level entry, i.e., either an L{1,2}_BLOCK or L3_PAGE entry. 1438 * Otherwise, just the cached final-level entry is invalidated. 1439 */ 1440 static __inline void 1441 pmap_invalidate_kernel(uint64_t r, bool final_only) 1442 { 1443 if (final_only) 1444 __asm __volatile("tlbi vaale1is, %0" : : "r" (r)); 1445 else 1446 __asm __volatile("tlbi vaae1is, %0" : : "r" (r)); 1447 } 1448 1449 static __inline void 1450 pmap_invalidate_user(uint64_t r, bool final_only) 1451 { 1452 if (final_only) 1453 __asm __volatile("tlbi vale1is, %0" : : "r" (r)); 1454 else 1455 __asm __volatile("tlbi vae1is, %0" : : "r" (r)); 1456 } 1457 1458 /* 1459 * Invalidates any cached final- and optionally intermediate-level TLB entries 1460 * for the specified virtual address in the given virtual address space. 1461 */ 1462 static __inline void 1463 pmap_invalidate_page(pmap_t pmap, vm_offset_t va, bool final_only) 1464 { 1465 uint64_t r; 1466 1467 PMAP_ASSERT_STAGE1(pmap); 1468 1469 dsb(ishst); 1470 r = TLBI_VA(va); 1471 if (pmap == kernel_pmap) { 1472 pmap_invalidate_kernel(r, final_only); 1473 } else { 1474 r |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)); 1475 pmap_invalidate_user(r, final_only); 1476 } 1477 dsb(ish); 1478 isb(); 1479 } 1480 1481 /* 1482 * Invalidates any cached final- and optionally intermediate-level TLB entries 1483 * for the specified virtual address range in the given virtual address space. 1484 */ 1485 static __inline void 1486 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1487 bool final_only) 1488 { 1489 uint64_t end, r, start; 1490 1491 PMAP_ASSERT_STAGE1(pmap); 1492 1493 dsb(ishst); 1494 if (pmap == kernel_pmap) { 1495 start = TLBI_VA(sva); 1496 end = TLBI_VA(eva); 1497 for (r = start; r < end; r += TLBI_VA_L3_INCR) 1498 pmap_invalidate_kernel(r, final_only); 1499 } else { 1500 start = end = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)); 1501 start |= TLBI_VA(sva); 1502 end |= TLBI_VA(eva); 1503 for (r = start; r < end; r += TLBI_VA_L3_INCR) 1504 pmap_invalidate_user(r, final_only); 1505 } 1506 dsb(ish); 1507 isb(); 1508 } 1509 1510 /* 1511 * Invalidates all cached intermediate- and final-level TLB entries for the 1512 * given virtual address space. 1513 */ 1514 static __inline void 1515 pmap_invalidate_all(pmap_t pmap) 1516 { 1517 uint64_t r; 1518 1519 PMAP_ASSERT_STAGE1(pmap); 1520 1521 dsb(ishst); 1522 if (pmap == kernel_pmap) { 1523 __asm __volatile("tlbi vmalle1is"); 1524 } else { 1525 r = ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)); 1526 __asm __volatile("tlbi aside1is, %0" : : "r" (r)); 1527 } 1528 dsb(ish); 1529 isb(); 1530 } 1531 1532 /* 1533 * Routine: pmap_extract 1534 * Function: 1535 * Extract the physical page address associated 1536 * with the given map/virtual_address pair. 1537 */ 1538 vm_paddr_t 1539 pmap_extract(pmap_t pmap, vm_offset_t va) 1540 { 1541 pt_entry_t *pte, tpte; 1542 vm_paddr_t pa; 1543 int lvl; 1544 1545 pa = 0; 1546 PMAP_LOCK(pmap); 1547 /* 1548 * Find the block or page map for this virtual address. pmap_pte 1549 * will return either a valid block/page entry, or NULL. 1550 */ 1551 pte = pmap_pte(pmap, va, &lvl); 1552 if (pte != NULL) { 1553 tpte = pmap_load(pte); 1554 pa = tpte & ~ATTR_MASK; 1555 switch(lvl) { 1556 case 1: 1557 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 1558 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK, 1559 ("pmap_extract: Invalid L1 pte found: %lx", 1560 tpte & ATTR_DESCR_MASK)); 1561 pa |= (va & L1_OFFSET); 1562 break; 1563 case 2: 1564 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK, 1565 ("pmap_extract: Invalid L2 pte found: %lx", 1566 tpte & ATTR_DESCR_MASK)); 1567 pa |= (va & L2_OFFSET); 1568 break; 1569 case 3: 1570 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE, 1571 ("pmap_extract: Invalid L3 pte found: %lx", 1572 tpte & ATTR_DESCR_MASK)); 1573 pa |= (va & L3_OFFSET); 1574 break; 1575 } 1576 } 1577 PMAP_UNLOCK(pmap); 1578 return (pa); 1579 } 1580 1581 /* 1582 * Routine: pmap_extract_and_hold 1583 * Function: 1584 * Atomically extract and hold the physical page 1585 * with the given pmap and virtual address pair 1586 * if that mapping permits the given protection. 1587 */ 1588 vm_page_t 1589 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1590 { 1591 pt_entry_t *pte, tpte; 1592 vm_offset_t off; 1593 vm_page_t m; 1594 int lvl; 1595 bool use; 1596 1597 m = NULL; 1598 PMAP_LOCK(pmap); 1599 pte = pmap_pte(pmap, va, &lvl); 1600 if (pte != NULL) { 1601 tpte = pmap_load(pte); 1602 1603 KASSERT(lvl > 0 && lvl <= 3, 1604 ("pmap_extract_and_hold: Invalid level %d", lvl)); 1605 /* 1606 * Check that the pte is either a L3 page, or a L1 or L2 block 1607 * entry. We can assume L1_BLOCK == L2_BLOCK. 1608 */ 1609 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) || 1610 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK), 1611 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl, 1612 tpte & ATTR_DESCR_MASK)); 1613 1614 use = false; 1615 if ((prot & VM_PROT_WRITE) == 0) 1616 use = true; 1617 else if (pmap->pm_stage == PM_STAGE1 && 1618 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW)) 1619 use = true; 1620 else if (pmap->pm_stage == PM_STAGE2 && 1621 ((tpte & ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE)) == 1622 ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE))) 1623 use = true; 1624 1625 if (use) { 1626 switch (lvl) { 1627 case 1: 1628 off = va & L1_OFFSET; 1629 break; 1630 case 2: 1631 off = va & L2_OFFSET; 1632 break; 1633 case 3: 1634 default: 1635 off = 0; 1636 } 1637 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off); 1638 if (m != NULL && !vm_page_wire_mapped(m)) 1639 m = NULL; 1640 } 1641 } 1642 PMAP_UNLOCK(pmap); 1643 return (m); 1644 } 1645 1646 /* 1647 * Walks the page tables to translate a kernel virtual address to a 1648 * physical address. Returns true if the kva is valid and stores the 1649 * physical address in pa if it is not NULL. 1650 */ 1651 bool 1652 pmap_klookup(vm_offset_t va, vm_paddr_t *pa) 1653 { 1654 pt_entry_t *pte, tpte; 1655 register_t intr; 1656 uint64_t par; 1657 1658 /* 1659 * Disable interrupts so we don't get interrupted between asking 1660 * for address translation, and getting the result back. 1661 */ 1662 intr = intr_disable(); 1663 par = arm64_address_translate_s1e1r(va); 1664 intr_restore(intr); 1665 1666 if (PAR_SUCCESS(par)) { 1667 if (pa != NULL) 1668 *pa = (par & PAR_PA_MASK) | (va & PAR_LOW_MASK); 1669 return (true); 1670 } 1671 1672 /* 1673 * Fall back to walking the page table. The address translation 1674 * instruction may fail when the page is in a break-before-make 1675 * sequence. As we only clear the valid bit in said sequence we 1676 * can walk the page table to find the physical address. 1677 */ 1678 1679 pte = pmap_l1(kernel_pmap, va); 1680 if (pte == NULL) 1681 return (false); 1682 1683 /* 1684 * A concurrent pmap_update_entry() will clear the entry's valid bit 1685 * but leave the rest of the entry unchanged. Therefore, we treat a 1686 * non-zero entry as being valid, and we ignore the valid bit when 1687 * determining whether the entry maps a block, page, or table. 1688 */ 1689 tpte = pmap_load(pte); 1690 if (tpte == 0) 1691 return (false); 1692 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) { 1693 if (pa != NULL) 1694 *pa = (tpte & ~ATTR_MASK) | (va & L1_OFFSET); 1695 return (true); 1696 } 1697 pte = pmap_l1_to_l2(&tpte, va); 1698 tpte = pmap_load(pte); 1699 if (tpte == 0) 1700 return (false); 1701 if ((tpte & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) { 1702 if (pa != NULL) 1703 *pa = (tpte & ~ATTR_MASK) | (va & L2_OFFSET); 1704 return (true); 1705 } 1706 pte = pmap_l2_to_l3(&tpte, va); 1707 tpte = pmap_load(pte); 1708 if (tpte == 0) 1709 return (false); 1710 if (pa != NULL) 1711 *pa = (tpte & ~ATTR_MASK) | (va & L3_OFFSET); 1712 return (true); 1713 } 1714 1715 vm_paddr_t 1716 pmap_kextract(vm_offset_t va) 1717 { 1718 vm_paddr_t pa; 1719 1720 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) 1721 return (DMAP_TO_PHYS(va)); 1722 1723 if (pmap_klookup(va, &pa) == false) 1724 return (0); 1725 return (pa); 1726 } 1727 1728 /*************************************************** 1729 * Low level mapping routines..... 1730 ***************************************************/ 1731 1732 void 1733 pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode) 1734 { 1735 pd_entry_t *pde; 1736 pt_entry_t *pte, attr; 1737 vm_offset_t va; 1738 int lvl; 1739 1740 KASSERT((pa & L3_OFFSET) == 0, 1741 ("pmap_kenter: Invalid physical address")); 1742 KASSERT((sva & L3_OFFSET) == 0, 1743 ("pmap_kenter: Invalid virtual address")); 1744 KASSERT((size & PAGE_MASK) == 0, 1745 ("pmap_kenter: Mapping is not page-sized")); 1746 1747 attr = ATTR_DEFAULT | ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN | 1748 ATTR_S1_IDX(mode) | L3_PAGE; 1749 va = sva; 1750 while (size != 0) { 1751 pde = pmap_pde(kernel_pmap, va, &lvl); 1752 KASSERT(pde != NULL, 1753 ("pmap_kenter: Invalid page entry, va: 0x%lx", va)); 1754 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl)); 1755 1756 pte = pmap_l2_to_l3(pde, va); 1757 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr); 1758 1759 va += PAGE_SIZE; 1760 pa += PAGE_SIZE; 1761 size -= PAGE_SIZE; 1762 } 1763 pmap_invalidate_range(kernel_pmap, sva, va, true); 1764 } 1765 1766 void 1767 pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa) 1768 { 1769 1770 pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE); 1771 } 1772 1773 /* 1774 * Remove a page from the kernel pagetables. 1775 */ 1776 PMAP_INLINE void 1777 pmap_kremove(vm_offset_t va) 1778 { 1779 pt_entry_t *pte; 1780 1781 pte = pmap_pte_exists(kernel_pmap, va, 3, __func__); 1782 pmap_clear(pte); 1783 pmap_invalidate_page(kernel_pmap, va, true); 1784 } 1785 1786 void 1787 pmap_kremove_device(vm_offset_t sva, vm_size_t size) 1788 { 1789 pt_entry_t *pte; 1790 vm_offset_t va; 1791 1792 KASSERT((sva & L3_OFFSET) == 0, 1793 ("pmap_kremove_device: Invalid virtual address")); 1794 KASSERT((size & PAGE_MASK) == 0, 1795 ("pmap_kremove_device: Mapping is not page-sized")); 1796 1797 va = sva; 1798 while (size != 0) { 1799 pte = pmap_pte_exists(kernel_pmap, va, 3, __func__); 1800 pmap_clear(pte); 1801 1802 va += PAGE_SIZE; 1803 size -= PAGE_SIZE; 1804 } 1805 pmap_invalidate_range(kernel_pmap, sva, va, true); 1806 } 1807 1808 /* 1809 * Used to map a range of physical addresses into kernel 1810 * virtual address space. 1811 * 1812 * The value passed in '*virt' is a suggested virtual address for 1813 * the mapping. Architectures which can support a direct-mapped 1814 * physical to virtual region can return the appropriate address 1815 * within that region, leaving '*virt' unchanged. Other 1816 * architectures should map the pages starting at '*virt' and 1817 * update '*virt' with the first usable address after the mapped 1818 * region. 1819 */ 1820 vm_offset_t 1821 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1822 { 1823 return PHYS_TO_DMAP(start); 1824 } 1825 1826 /* 1827 * Add a list of wired pages to the kva 1828 * this routine is only used for temporary 1829 * kernel mappings that do not need to have 1830 * page modification or references recorded. 1831 * Note that old mappings are simply written 1832 * over. The page *must* be wired. 1833 * Note: SMP coherent. Uses a ranged shootdown IPI. 1834 */ 1835 void 1836 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1837 { 1838 pd_entry_t *pde; 1839 pt_entry_t *pte, pa; 1840 vm_offset_t va; 1841 vm_page_t m; 1842 int i, lvl; 1843 1844 va = sva; 1845 for (i = 0; i < count; i++) { 1846 pde = pmap_pde(kernel_pmap, va, &lvl); 1847 KASSERT(pde != NULL, 1848 ("pmap_qenter: Invalid page entry, va: 0x%lx", va)); 1849 KASSERT(lvl == 2, 1850 ("pmap_qenter: Invalid level %d", lvl)); 1851 1852 m = ma[i]; 1853 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | 1854 ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_XN | 1855 ATTR_S1_IDX(m->md.pv_memattr) | L3_PAGE; 1856 pte = pmap_l2_to_l3(pde, va); 1857 pmap_load_store(pte, pa); 1858 1859 va += L3_SIZE; 1860 } 1861 pmap_invalidate_range(kernel_pmap, sva, va, true); 1862 } 1863 1864 /* 1865 * This routine tears out page mappings from the 1866 * kernel -- it is meant only for temporary mappings. 1867 */ 1868 void 1869 pmap_qremove(vm_offset_t sva, int count) 1870 { 1871 pt_entry_t *pte; 1872 vm_offset_t va; 1873 1874 KASSERT(ADDR_IS_CANONICAL(sva), 1875 ("%s: Address not in canonical form: %lx", __func__, sva)); 1876 KASSERT(ADDR_IS_KERNEL(sva), ("usermode va %lx", sva)); 1877 1878 va = sva; 1879 while (count-- > 0) { 1880 pte = pmap_pte_exists(kernel_pmap, va, 3, NULL); 1881 if (pte != NULL) { 1882 pmap_clear(pte); 1883 } 1884 1885 va += PAGE_SIZE; 1886 } 1887 pmap_invalidate_range(kernel_pmap, sva, va, true); 1888 } 1889 1890 /*************************************************** 1891 * Page table page management routines..... 1892 ***************************************************/ 1893 /* 1894 * Schedule the specified unused page table page to be freed. Specifically, 1895 * add the page to the specified list of pages that will be released to the 1896 * physical memory manager after the TLB has been updated. 1897 */ 1898 static __inline void 1899 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, 1900 boolean_t set_PG_ZERO) 1901 { 1902 1903 if (set_PG_ZERO) 1904 m->flags |= PG_ZERO; 1905 else 1906 m->flags &= ~PG_ZERO; 1907 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 1908 } 1909 1910 /* 1911 * Decrements a page table page's reference count, which is used to record the 1912 * number of valid page table entries within the page. If the reference count 1913 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1914 * page table page was unmapped and FALSE otherwise. 1915 */ 1916 static inline boolean_t 1917 pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 1918 { 1919 1920 --m->ref_count; 1921 if (m->ref_count == 0) { 1922 _pmap_unwire_l3(pmap, va, m, free); 1923 return (TRUE); 1924 } else 1925 return (FALSE); 1926 } 1927 1928 static void 1929 _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 1930 { 1931 1932 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1933 /* 1934 * unmap the page table page 1935 */ 1936 if (m->pindex >= (NUL2E + NUL1E)) { 1937 /* l1 page */ 1938 pd_entry_t *l0; 1939 1940 l0 = pmap_l0(pmap, va); 1941 pmap_clear(l0); 1942 } else if (m->pindex >= NUL2E) { 1943 /* l2 page */ 1944 pd_entry_t *l1; 1945 1946 l1 = pmap_l1(pmap, va); 1947 pmap_clear(l1); 1948 } else { 1949 /* l3 page */ 1950 pd_entry_t *l2; 1951 1952 l2 = pmap_l2(pmap, va); 1953 pmap_clear(l2); 1954 } 1955 pmap_resident_count_dec(pmap, 1); 1956 if (m->pindex < NUL2E) { 1957 /* We just released an l3, unhold the matching l2 */ 1958 pd_entry_t *l1, tl1; 1959 vm_page_t l2pg; 1960 1961 l1 = pmap_l1(pmap, va); 1962 tl1 = pmap_load(l1); 1963 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK); 1964 pmap_unwire_l3(pmap, va, l2pg, free); 1965 } else if (m->pindex < (NUL2E + NUL1E)) { 1966 /* We just released an l2, unhold the matching l1 */ 1967 pd_entry_t *l0, tl0; 1968 vm_page_t l1pg; 1969 1970 l0 = pmap_l0(pmap, va); 1971 tl0 = pmap_load(l0); 1972 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK); 1973 pmap_unwire_l3(pmap, va, l1pg, free); 1974 } 1975 pmap_invalidate_page(pmap, va, false); 1976 1977 /* 1978 * Put page on a list so that it is released after 1979 * *ALL* TLB shootdown is done 1980 */ 1981 pmap_add_delayed_free_list(m, free, TRUE); 1982 } 1983 1984 /* 1985 * After removing a page table entry, this routine is used to 1986 * conditionally free the page, and manage the reference count. 1987 */ 1988 static int 1989 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde, 1990 struct spglist *free) 1991 { 1992 vm_page_t mpte; 1993 1994 KASSERT(ADDR_IS_CANONICAL(va), 1995 ("%s: Address not in canonical form: %lx", __func__, va)); 1996 if (ADDR_IS_KERNEL(va)) 1997 return (0); 1998 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0")); 1999 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK); 2000 return (pmap_unwire_l3(pmap, va, mpte, free)); 2001 } 2002 2003 /* 2004 * Release a page table page reference after a failed attempt to create a 2005 * mapping. 2006 */ 2007 static void 2008 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 2009 { 2010 struct spglist free; 2011 2012 SLIST_INIT(&free); 2013 if (pmap_unwire_l3(pmap, va, mpte, &free)) 2014 vm_page_free_pages_toq(&free, true); 2015 } 2016 2017 void 2018 pmap_pinit0(pmap_t pmap) 2019 { 2020 2021 PMAP_LOCK_INIT(pmap); 2022 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 2023 pmap->pm_l0_paddr = READ_SPECIALREG(ttbr0_el1); 2024 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr); 2025 vm_radix_init(&pmap->pm_root); 2026 pmap->pm_cookie = COOKIE_FROM(ASID_RESERVED_FOR_PID_0, INT_MIN); 2027 pmap->pm_stage = PM_STAGE1; 2028 pmap->pm_levels = 4; 2029 pmap->pm_ttbr = pmap->pm_l0_paddr; 2030 pmap->pm_asid_set = &asids; 2031 2032 PCPU_SET(curpmap, pmap); 2033 } 2034 2035 int 2036 pmap_pinit_stage(pmap_t pmap, enum pmap_stage stage, int levels) 2037 { 2038 vm_page_t m; 2039 2040 /* 2041 * allocate the l0 page 2042 */ 2043 m = vm_page_alloc_noobj(VM_ALLOC_WAITOK | VM_ALLOC_WIRED | 2044 VM_ALLOC_ZERO); 2045 pmap->pm_l0_paddr = VM_PAGE_TO_PHYS(m); 2046 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(pmap->pm_l0_paddr); 2047 2048 vm_radix_init(&pmap->pm_root); 2049 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 2050 pmap->pm_cookie = COOKIE_FROM(-1, INT_MAX); 2051 2052 MPASS(levels == 3 || levels == 4); 2053 pmap->pm_levels = levels; 2054 pmap->pm_stage = stage; 2055 switch (stage) { 2056 case PM_STAGE1: 2057 pmap->pm_asid_set = &asids; 2058 break; 2059 case PM_STAGE2: 2060 pmap->pm_asid_set = &vmids; 2061 break; 2062 default: 2063 panic("%s: Invalid pmap type %d", __func__, stage); 2064 break; 2065 } 2066 2067 /* XXX Temporarily disable deferred ASID allocation. */ 2068 pmap_alloc_asid(pmap); 2069 2070 /* 2071 * Allocate the level 1 entry to use as the root. This will increase 2072 * the refcount on the level 1 page so it won't be removed until 2073 * pmap_release() is called. 2074 */ 2075 if (pmap->pm_levels == 3) { 2076 PMAP_LOCK(pmap); 2077 m = _pmap_alloc_l3(pmap, NUL2E + NUL1E, NULL); 2078 PMAP_UNLOCK(pmap); 2079 } 2080 pmap->pm_ttbr = VM_PAGE_TO_PHYS(m); 2081 2082 return (1); 2083 } 2084 2085 int 2086 pmap_pinit(pmap_t pmap) 2087 { 2088 2089 return (pmap_pinit_stage(pmap, PM_STAGE1, 4)); 2090 } 2091 2092 /* 2093 * This routine is called if the desired page table page does not exist. 2094 * 2095 * If page table page allocation fails, this routine may sleep before 2096 * returning NULL. It sleeps only if a lock pointer was given. 2097 * 2098 * Note: If a page allocation fails at page table level two or three, 2099 * one or two pages may be held during the wait, only to be released 2100 * afterwards. This conservative approach is easily argued to avoid 2101 * race conditions. 2102 */ 2103 static vm_page_t 2104 _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp) 2105 { 2106 vm_page_t m, l1pg, l2pg; 2107 2108 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2109 2110 /* 2111 * Allocate a page table page. 2112 */ 2113 if ((m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 2114 if (lockp != NULL) { 2115 RELEASE_PV_LIST_LOCK(lockp); 2116 PMAP_UNLOCK(pmap); 2117 vm_wait(NULL); 2118 PMAP_LOCK(pmap); 2119 } 2120 2121 /* 2122 * Indicate the need to retry. While waiting, the page table 2123 * page may have been allocated. 2124 */ 2125 return (NULL); 2126 } 2127 m->pindex = ptepindex; 2128 2129 /* 2130 * Because of AArch64's weak memory consistency model, we must have a 2131 * barrier here to ensure that the stores for zeroing "m", whether by 2132 * pmap_zero_page() or an earlier function, are visible before adding 2133 * "m" to the page table. Otherwise, a page table walk by another 2134 * processor's MMU could see the mapping to "m" and a stale, non-zero 2135 * PTE within "m". 2136 */ 2137 dmb(ishst); 2138 2139 /* 2140 * Map the pagetable page into the process address space, if 2141 * it isn't already there. 2142 */ 2143 2144 if (ptepindex >= (NUL2E + NUL1E)) { 2145 pd_entry_t *l0p, l0e; 2146 vm_pindex_t l0index; 2147 2148 l0index = ptepindex - (NUL2E + NUL1E); 2149 l0p = &pmap->pm_l0[l0index]; 2150 KASSERT((pmap_load(l0p) & ATTR_DESCR_VALID) == 0, 2151 ("%s: L0 entry %#lx is valid", __func__, pmap_load(l0p))); 2152 l0e = VM_PAGE_TO_PHYS(m) | L0_TABLE; 2153 2154 /* 2155 * Mark all kernel memory as not accessible from userspace 2156 * and userspace memory as not executable from the kernel. 2157 * This has been done for the bootstrap L0 entries in 2158 * locore.S. 2159 */ 2160 if (pmap == kernel_pmap) 2161 l0e |= TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0; 2162 else 2163 l0e |= TATTR_PXN_TABLE; 2164 pmap_store(l0p, l0e); 2165 } else if (ptepindex >= NUL2E) { 2166 vm_pindex_t l0index, l1index; 2167 pd_entry_t *l0, *l1; 2168 pd_entry_t tl0; 2169 2170 l1index = ptepindex - NUL2E; 2171 l0index = l1index >> Ln_ENTRIES_SHIFT; 2172 2173 l0 = &pmap->pm_l0[l0index]; 2174 tl0 = pmap_load(l0); 2175 if (tl0 == 0) { 2176 /* recurse for allocating page dir */ 2177 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index, 2178 lockp) == NULL) { 2179 vm_page_unwire_noq(m); 2180 vm_page_free_zero(m); 2181 return (NULL); 2182 } 2183 } else { 2184 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK); 2185 l1pg->ref_count++; 2186 } 2187 2188 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK); 2189 l1 = &l1[ptepindex & Ln_ADDR_MASK]; 2190 KASSERT((pmap_load(l1) & ATTR_DESCR_VALID) == 0, 2191 ("%s: L1 entry %#lx is valid", __func__, pmap_load(l1))); 2192 pmap_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE); 2193 } else { 2194 vm_pindex_t l0index, l1index; 2195 pd_entry_t *l0, *l1, *l2; 2196 pd_entry_t tl0, tl1; 2197 2198 l1index = ptepindex >> Ln_ENTRIES_SHIFT; 2199 l0index = l1index >> Ln_ENTRIES_SHIFT; 2200 2201 l0 = &pmap->pm_l0[l0index]; 2202 tl0 = pmap_load(l0); 2203 if (tl0 == 0) { 2204 /* recurse for allocating page dir */ 2205 if (_pmap_alloc_l3(pmap, NUL2E + l1index, 2206 lockp) == NULL) { 2207 vm_page_unwire_noq(m); 2208 vm_page_free_zero(m); 2209 return (NULL); 2210 } 2211 tl0 = pmap_load(l0); 2212 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK); 2213 l1 = &l1[l1index & Ln_ADDR_MASK]; 2214 } else { 2215 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK); 2216 l1 = &l1[l1index & Ln_ADDR_MASK]; 2217 tl1 = pmap_load(l1); 2218 if (tl1 == 0) { 2219 /* recurse for allocating page dir */ 2220 if (_pmap_alloc_l3(pmap, NUL2E + l1index, 2221 lockp) == NULL) { 2222 vm_page_unwire_noq(m); 2223 vm_page_free_zero(m); 2224 return (NULL); 2225 } 2226 } else { 2227 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK); 2228 l2pg->ref_count++; 2229 } 2230 } 2231 2232 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK); 2233 l2 = &l2[ptepindex & Ln_ADDR_MASK]; 2234 KASSERT((pmap_load(l2) & ATTR_DESCR_VALID) == 0, 2235 ("%s: L2 entry %#lx is valid", __func__, pmap_load(l2))); 2236 pmap_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE); 2237 } 2238 2239 pmap_resident_count_inc(pmap, 1); 2240 2241 return (m); 2242 } 2243 2244 static pd_entry_t * 2245 pmap_alloc_l2(pmap_t pmap, vm_offset_t va, vm_page_t *l2pgp, 2246 struct rwlock **lockp) 2247 { 2248 pd_entry_t *l1, *l2; 2249 vm_page_t l2pg; 2250 vm_pindex_t l2pindex; 2251 2252 KASSERT(ADDR_IS_CANONICAL(va), 2253 ("%s: Address not in canonical form: %lx", __func__, va)); 2254 2255 retry: 2256 l1 = pmap_l1(pmap, va); 2257 if (l1 != NULL && (pmap_load(l1) & ATTR_DESCR_MASK) == L1_TABLE) { 2258 l2 = pmap_l1_to_l2(l1, va); 2259 if (!ADDR_IS_KERNEL(va)) { 2260 /* Add a reference to the L2 page. */ 2261 l2pg = PHYS_TO_VM_PAGE(pmap_load(l1) & ~ATTR_MASK); 2262 l2pg->ref_count++; 2263 } else 2264 l2pg = NULL; 2265 } else if (!ADDR_IS_KERNEL(va)) { 2266 /* Allocate a L2 page. */ 2267 l2pindex = pmap_l2_pindex(va) >> Ln_ENTRIES_SHIFT; 2268 l2pg = _pmap_alloc_l3(pmap, NUL2E + l2pindex, lockp); 2269 if (l2pg == NULL) { 2270 if (lockp != NULL) 2271 goto retry; 2272 else 2273 return (NULL); 2274 } 2275 l2 = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(l2pg)); 2276 l2 = &l2[pmap_l2_index(va)]; 2277 } else 2278 panic("pmap_alloc_l2: missing page table page for va %#lx", 2279 va); 2280 *l2pgp = l2pg; 2281 return (l2); 2282 } 2283 2284 static vm_page_t 2285 pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp) 2286 { 2287 vm_pindex_t ptepindex; 2288 pd_entry_t *pde, tpde; 2289 #ifdef INVARIANTS 2290 pt_entry_t *pte; 2291 #endif 2292 vm_page_t m; 2293 int lvl; 2294 2295 /* 2296 * Calculate pagetable page index 2297 */ 2298 ptepindex = pmap_l2_pindex(va); 2299 retry: 2300 /* 2301 * Get the page directory entry 2302 */ 2303 pde = pmap_pde(pmap, va, &lvl); 2304 2305 /* 2306 * If the page table page is mapped, we just increment the hold count, 2307 * and activate it. If we get a level 2 pde it will point to a level 3 2308 * table. 2309 */ 2310 switch (lvl) { 2311 case -1: 2312 break; 2313 case 0: 2314 #ifdef INVARIANTS 2315 pte = pmap_l0_to_l1(pde, va); 2316 KASSERT(pmap_load(pte) == 0, 2317 ("pmap_alloc_l3: TODO: l0 superpages")); 2318 #endif 2319 break; 2320 case 1: 2321 #ifdef INVARIANTS 2322 pte = pmap_l1_to_l2(pde, va); 2323 KASSERT(pmap_load(pte) == 0, 2324 ("pmap_alloc_l3: TODO: l1 superpages")); 2325 #endif 2326 break; 2327 case 2: 2328 tpde = pmap_load(pde); 2329 if (tpde != 0) { 2330 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK); 2331 m->ref_count++; 2332 return (m); 2333 } 2334 break; 2335 default: 2336 panic("pmap_alloc_l3: Invalid level %d", lvl); 2337 } 2338 2339 /* 2340 * Here if the pte page isn't mapped, or if it has been deallocated. 2341 */ 2342 m = _pmap_alloc_l3(pmap, ptepindex, lockp); 2343 if (m == NULL && lockp != NULL) 2344 goto retry; 2345 2346 return (m); 2347 } 2348 2349 /*************************************************** 2350 * Pmap allocation/deallocation routines. 2351 ***************************************************/ 2352 2353 /* 2354 * Release any resources held by the given physical map. 2355 * Called when a pmap initialized by pmap_pinit is being released. 2356 * Should only be called if the map contains no valid mappings. 2357 */ 2358 void 2359 pmap_release(pmap_t pmap) 2360 { 2361 boolean_t rv __diagused; 2362 struct spglist free; 2363 struct asid_set *set; 2364 vm_page_t m; 2365 int asid; 2366 2367 if (pmap->pm_levels != 4) { 2368 PMAP_ASSERT_STAGE2(pmap); 2369 KASSERT(pmap->pm_stats.resident_count == 1, 2370 ("pmap_release: pmap resident count %ld != 0", 2371 pmap->pm_stats.resident_count)); 2372 KASSERT((pmap->pm_l0[0] & ATTR_DESCR_VALID) == ATTR_DESCR_VALID, 2373 ("pmap_release: Invalid l0 entry: %lx", pmap->pm_l0[0])); 2374 2375 SLIST_INIT(&free); 2376 m = PHYS_TO_VM_PAGE(pmap->pm_ttbr); 2377 PMAP_LOCK(pmap); 2378 rv = pmap_unwire_l3(pmap, 0, m, &free); 2379 PMAP_UNLOCK(pmap); 2380 MPASS(rv == TRUE); 2381 vm_page_free_pages_toq(&free, true); 2382 } 2383 2384 KASSERT(pmap->pm_stats.resident_count == 0, 2385 ("pmap_release: pmap resident count %ld != 0", 2386 pmap->pm_stats.resident_count)); 2387 KASSERT(vm_radix_is_empty(&pmap->pm_root), 2388 ("pmap_release: pmap has reserved page table page(s)")); 2389 2390 set = pmap->pm_asid_set; 2391 KASSERT(set != NULL, ("%s: NULL asid set", __func__)); 2392 2393 /* 2394 * Allow the ASID to be reused. In stage 2 VMIDs we don't invalidate 2395 * the entries when removing them so rely on a later tlb invalidation. 2396 * this will happen when updating the VMID generation. Because of this 2397 * we don't reuse VMIDs within a generation. 2398 */ 2399 if (pmap->pm_stage == PM_STAGE1) { 2400 mtx_lock_spin(&set->asid_set_mutex); 2401 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) { 2402 asid = COOKIE_TO_ASID(pmap->pm_cookie); 2403 KASSERT(asid >= ASID_FIRST_AVAILABLE && 2404 asid < set->asid_set_size, 2405 ("pmap_release: pmap cookie has out-of-range asid")); 2406 bit_clear(set->asid_set, asid); 2407 } 2408 mtx_unlock_spin(&set->asid_set_mutex); 2409 } 2410 2411 m = PHYS_TO_VM_PAGE(pmap->pm_l0_paddr); 2412 vm_page_unwire_noq(m); 2413 vm_page_free_zero(m); 2414 } 2415 2416 static int 2417 kvm_size(SYSCTL_HANDLER_ARGS) 2418 { 2419 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS; 2420 2421 return sysctl_handle_long(oidp, &ksize, 0, req); 2422 } 2423 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE, 2424 0, 0, kvm_size, "LU", 2425 "Size of KVM"); 2426 2427 static int 2428 kvm_free(SYSCTL_HANDLER_ARGS) 2429 { 2430 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2431 2432 return sysctl_handle_long(oidp, &kfree, 0, req); 2433 } 2434 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE, 2435 0, 0, kvm_free, "LU", 2436 "Amount of KVM free"); 2437 2438 /* 2439 * grow the number of kernel page table entries, if needed 2440 */ 2441 void 2442 pmap_growkernel(vm_offset_t addr) 2443 { 2444 vm_paddr_t paddr; 2445 vm_page_t nkpg; 2446 pd_entry_t *l0, *l1, *l2; 2447 2448 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2449 2450 addr = roundup2(addr, L2_SIZE); 2451 if (addr - 1 >= vm_map_max(kernel_map)) 2452 addr = vm_map_max(kernel_map); 2453 while (kernel_vm_end < addr) { 2454 l0 = pmap_l0(kernel_pmap, kernel_vm_end); 2455 KASSERT(pmap_load(l0) != 0, 2456 ("pmap_growkernel: No level 0 kernel entry")); 2457 2458 l1 = pmap_l0_to_l1(l0, kernel_vm_end); 2459 if (pmap_load(l1) == 0) { 2460 /* We need a new PDP entry */ 2461 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | 2462 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 2463 if (nkpg == NULL) 2464 panic("pmap_growkernel: no memory to grow kernel"); 2465 nkpg->pindex = kernel_vm_end >> L1_SHIFT; 2466 /* See the dmb() in _pmap_alloc_l3(). */ 2467 dmb(ishst); 2468 paddr = VM_PAGE_TO_PHYS(nkpg); 2469 pmap_store(l1, paddr | L1_TABLE); 2470 continue; /* try again */ 2471 } 2472 l2 = pmap_l1_to_l2(l1, kernel_vm_end); 2473 if (pmap_load(l2) != 0) { 2474 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET; 2475 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) { 2476 kernel_vm_end = vm_map_max(kernel_map); 2477 break; 2478 } 2479 continue; 2480 } 2481 2482 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED | 2483 VM_ALLOC_ZERO); 2484 if (nkpg == NULL) 2485 panic("pmap_growkernel: no memory to grow kernel"); 2486 nkpg->pindex = kernel_vm_end >> L2_SHIFT; 2487 /* See the dmb() in _pmap_alloc_l3(). */ 2488 dmb(ishst); 2489 paddr = VM_PAGE_TO_PHYS(nkpg); 2490 pmap_store(l2, paddr | L2_TABLE); 2491 2492 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET; 2493 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) { 2494 kernel_vm_end = vm_map_max(kernel_map); 2495 break; 2496 } 2497 } 2498 } 2499 2500 /*************************************************** 2501 * page management routines. 2502 ***************************************************/ 2503 2504 static const uint64_t pc_freemask[_NPCM] = { 2505 [0 ... _NPCM - 2] = PC_FREEN, 2506 [_NPCM - 1] = PC_FREEL 2507 }; 2508 2509 #ifdef PV_STATS 2510 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2511 2512 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2513 "Current number of pv entry chunks"); 2514 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2515 "Current number of pv entry chunks allocated"); 2516 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2517 "Current number of pv entry chunks frees"); 2518 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2519 "Number of times tried to get a chunk page but failed."); 2520 2521 static long pv_entry_frees, pv_entry_allocs, pv_entry_count; 2522 static int pv_entry_spare; 2523 2524 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2525 "Current number of pv entry frees"); 2526 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2527 "Current number of pv entry allocs"); 2528 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2529 "Current number of pv entries"); 2530 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2531 "Current number of spare pv entries"); 2532 #endif 2533 2534 /* 2535 * We are in a serious low memory condition. Resort to 2536 * drastic measures to free some pages so we can allocate 2537 * another pv entry chunk. 2538 * 2539 * Returns NULL if PV entries were reclaimed from the specified pmap. 2540 * 2541 * We do not, however, unmap 2mpages because subsequent accesses will 2542 * allocate per-page pv entries until repromotion occurs, thereby 2543 * exacerbating the shortage of free pv entries. 2544 */ 2545 static vm_page_t 2546 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain) 2547 { 2548 struct pv_chunks_list *pvc; 2549 struct pv_chunk *pc, *pc_marker, *pc_marker_end; 2550 struct pv_chunk_header pc_marker_b, pc_marker_end_b; 2551 struct md_page *pvh; 2552 pd_entry_t *pde; 2553 pmap_t next_pmap, pmap; 2554 pt_entry_t *pte, tpte; 2555 pv_entry_t pv; 2556 vm_offset_t va; 2557 vm_page_t m, m_pc; 2558 struct spglist free; 2559 uint64_t inuse; 2560 int bit, field, freed, lvl; 2561 2562 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 2563 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL")); 2564 2565 pmap = NULL; 2566 m_pc = NULL; 2567 SLIST_INIT(&free); 2568 bzero(&pc_marker_b, sizeof(pc_marker_b)); 2569 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b)); 2570 pc_marker = (struct pv_chunk *)&pc_marker_b; 2571 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b; 2572 2573 pvc = &pv_chunks[domain]; 2574 mtx_lock(&pvc->pvc_lock); 2575 pvc->active_reclaims++; 2576 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru); 2577 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru); 2578 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end && 2579 SLIST_EMPTY(&free)) { 2580 next_pmap = pc->pc_pmap; 2581 if (next_pmap == NULL) { 2582 /* 2583 * The next chunk is a marker. However, it is 2584 * not our marker, so active_reclaims must be 2585 * > 1. Consequently, the next_chunk code 2586 * will not rotate the pv_chunks list. 2587 */ 2588 goto next_chunk; 2589 } 2590 mtx_unlock(&pvc->pvc_lock); 2591 2592 /* 2593 * A pv_chunk can only be removed from the pc_lru list 2594 * when both pvc->pvc_lock is owned and the 2595 * corresponding pmap is locked. 2596 */ 2597 if (pmap != next_pmap) { 2598 if (pmap != NULL && pmap != locked_pmap) 2599 PMAP_UNLOCK(pmap); 2600 pmap = next_pmap; 2601 /* Avoid deadlock and lock recursion. */ 2602 if (pmap > locked_pmap) { 2603 RELEASE_PV_LIST_LOCK(lockp); 2604 PMAP_LOCK(pmap); 2605 mtx_lock(&pvc->pvc_lock); 2606 continue; 2607 } else if (pmap != locked_pmap) { 2608 if (PMAP_TRYLOCK(pmap)) { 2609 mtx_lock(&pvc->pvc_lock); 2610 continue; 2611 } else { 2612 pmap = NULL; /* pmap is not locked */ 2613 mtx_lock(&pvc->pvc_lock); 2614 pc = TAILQ_NEXT(pc_marker, pc_lru); 2615 if (pc == NULL || 2616 pc->pc_pmap != next_pmap) 2617 continue; 2618 goto next_chunk; 2619 } 2620 } 2621 } 2622 2623 /* 2624 * Destroy every non-wired, 4 KB page mapping in the chunk. 2625 */ 2626 freed = 0; 2627 for (field = 0; field < _NPCM; field++) { 2628 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2629 inuse != 0; inuse &= ~(1UL << bit)) { 2630 bit = ffsl(inuse) - 1; 2631 pv = &pc->pc_pventry[field * 64 + bit]; 2632 va = pv->pv_va; 2633 pde = pmap_pde(pmap, va, &lvl); 2634 if (lvl != 2) 2635 continue; 2636 pte = pmap_l2_to_l3(pde, va); 2637 tpte = pmap_load(pte); 2638 if ((tpte & ATTR_SW_WIRED) != 0) 2639 continue; 2640 tpte = pmap_load_clear(pte); 2641 m = PHYS_TO_VM_PAGE(tpte & ~ATTR_MASK); 2642 if (pmap_pte_dirty(pmap, tpte)) 2643 vm_page_dirty(m); 2644 if ((tpte & ATTR_AF) != 0) { 2645 pmap_invalidate_page(pmap, va, true); 2646 vm_page_aflag_set(m, PGA_REFERENCED); 2647 } 2648 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 2649 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2650 m->md.pv_gen++; 2651 if (TAILQ_EMPTY(&m->md.pv_list) && 2652 (m->flags & PG_FICTITIOUS) == 0) { 2653 pvh = page_to_pvh(m); 2654 if (TAILQ_EMPTY(&pvh->pv_list)) { 2655 vm_page_aflag_clear(m, 2656 PGA_WRITEABLE); 2657 } 2658 } 2659 pc->pc_map[field] |= 1UL << bit; 2660 pmap_unuse_pt(pmap, va, pmap_load(pde), &free); 2661 freed++; 2662 } 2663 } 2664 if (freed == 0) { 2665 mtx_lock(&pvc->pvc_lock); 2666 goto next_chunk; 2667 } 2668 /* Every freed mapping is for a 4 KB page. */ 2669 pmap_resident_count_dec(pmap, freed); 2670 PV_STAT(atomic_add_long(&pv_entry_frees, freed)); 2671 PV_STAT(atomic_add_int(&pv_entry_spare, freed)); 2672 PV_STAT(atomic_subtract_long(&pv_entry_count, freed)); 2673 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2674 if (pc_is_free(pc)) { 2675 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV)); 2676 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1)); 2677 PV_STAT(atomic_add_int(&pc_chunk_frees, 1)); 2678 /* Entire chunk is free; return it. */ 2679 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 2680 dump_drop_page(m_pc->phys_addr); 2681 mtx_lock(&pvc->pvc_lock); 2682 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 2683 break; 2684 } 2685 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2686 mtx_lock(&pvc->pvc_lock); 2687 /* One freed pv entry in locked_pmap is sufficient. */ 2688 if (pmap == locked_pmap) 2689 break; 2690 2691 next_chunk: 2692 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru); 2693 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru); 2694 if (pvc->active_reclaims == 1 && pmap != NULL) { 2695 /* 2696 * Rotate the pv chunks list so that we do not 2697 * scan the same pv chunks that could not be 2698 * freed (because they contained a wired 2699 * and/or superpage mapping) on every 2700 * invocation of reclaim_pv_chunk(). 2701 */ 2702 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker){ 2703 MPASS(pc->pc_pmap != NULL); 2704 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 2705 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru); 2706 } 2707 } 2708 } 2709 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru); 2710 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru); 2711 pvc->active_reclaims--; 2712 mtx_unlock(&pvc->pvc_lock); 2713 if (pmap != NULL && pmap != locked_pmap) 2714 PMAP_UNLOCK(pmap); 2715 if (m_pc == NULL && !SLIST_EMPTY(&free)) { 2716 m_pc = SLIST_FIRST(&free); 2717 SLIST_REMOVE_HEAD(&free, plinks.s.ss); 2718 /* Recycle a freed page table page. */ 2719 m_pc->ref_count = 1; 2720 } 2721 vm_page_free_pages_toq(&free, true); 2722 return (m_pc); 2723 } 2724 2725 static vm_page_t 2726 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp) 2727 { 2728 vm_page_t m; 2729 int i, domain; 2730 2731 domain = PCPU_GET(domain); 2732 for (i = 0; i < vm_ndomains; i++) { 2733 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain); 2734 if (m != NULL) 2735 break; 2736 domain = (domain + 1) % vm_ndomains; 2737 } 2738 2739 return (m); 2740 } 2741 2742 /* 2743 * free the pv_entry back to the free list 2744 */ 2745 static void 2746 free_pv_entry(pmap_t pmap, pv_entry_t pv) 2747 { 2748 struct pv_chunk *pc; 2749 int idx, field, bit; 2750 2751 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2752 PV_STAT(atomic_add_long(&pv_entry_frees, 1)); 2753 PV_STAT(atomic_add_int(&pv_entry_spare, 1)); 2754 PV_STAT(atomic_subtract_long(&pv_entry_count, 1)); 2755 pc = pv_to_chunk(pv); 2756 idx = pv - &pc->pc_pventry[0]; 2757 field = idx / 64; 2758 bit = idx % 64; 2759 pc->pc_map[field] |= 1ul << bit; 2760 if (!pc_is_free(pc)) { 2761 /* 98% of the time, pc is already at the head of the list. */ 2762 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) { 2763 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2764 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2765 } 2766 return; 2767 } 2768 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2769 free_pv_chunk(pc); 2770 } 2771 2772 static void 2773 free_pv_chunk_dequeued(struct pv_chunk *pc) 2774 { 2775 vm_page_t m; 2776 2777 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV)); 2778 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1)); 2779 PV_STAT(atomic_add_int(&pc_chunk_frees, 1)); 2780 /* entire chunk is free, return it */ 2781 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 2782 dump_drop_page(m->phys_addr); 2783 vm_page_unwire_noq(m); 2784 vm_page_free(m); 2785 } 2786 2787 static void 2788 free_pv_chunk(struct pv_chunk *pc) 2789 { 2790 struct pv_chunks_list *pvc; 2791 2792 pvc = &pv_chunks[pc_to_domain(pc)]; 2793 mtx_lock(&pvc->pvc_lock); 2794 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 2795 mtx_unlock(&pvc->pvc_lock); 2796 free_pv_chunk_dequeued(pc); 2797 } 2798 2799 static void 2800 free_pv_chunk_batch(struct pv_chunklist *batch) 2801 { 2802 struct pv_chunks_list *pvc; 2803 struct pv_chunk *pc, *npc; 2804 int i; 2805 2806 for (i = 0; i < vm_ndomains; i++) { 2807 if (TAILQ_EMPTY(&batch[i])) 2808 continue; 2809 pvc = &pv_chunks[i]; 2810 mtx_lock(&pvc->pvc_lock); 2811 TAILQ_FOREACH(pc, &batch[i], pc_list) { 2812 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru); 2813 } 2814 mtx_unlock(&pvc->pvc_lock); 2815 } 2816 2817 for (i = 0; i < vm_ndomains; i++) { 2818 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) { 2819 free_pv_chunk_dequeued(pc); 2820 } 2821 } 2822 } 2823 2824 /* 2825 * Returns a new PV entry, allocating a new PV chunk from the system when 2826 * needed. If this PV chunk allocation fails and a PV list lock pointer was 2827 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is 2828 * returned. 2829 * 2830 * The given PV list lock may be released. 2831 */ 2832 static pv_entry_t 2833 get_pv_entry(pmap_t pmap, struct rwlock **lockp) 2834 { 2835 struct pv_chunks_list *pvc; 2836 int bit, field; 2837 pv_entry_t pv; 2838 struct pv_chunk *pc; 2839 vm_page_t m; 2840 2841 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2842 PV_STAT(atomic_add_long(&pv_entry_allocs, 1)); 2843 retry: 2844 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2845 if (pc != NULL) { 2846 for (field = 0; field < _NPCM; field++) { 2847 if (pc->pc_map[field]) { 2848 bit = ffsl(pc->pc_map[field]) - 1; 2849 break; 2850 } 2851 } 2852 if (field < _NPCM) { 2853 pv = &pc->pc_pventry[field * 64 + bit]; 2854 pc->pc_map[field] &= ~(1ul << bit); 2855 /* If this was the last item, move it to tail */ 2856 if (pc_is_full(pc)) { 2857 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2858 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, 2859 pc_list); 2860 } 2861 PV_STAT(atomic_add_long(&pv_entry_count, 1)); 2862 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1)); 2863 return (pv); 2864 } 2865 } 2866 /* No free items, allocate another chunk */ 2867 m = vm_page_alloc_noobj(VM_ALLOC_WIRED); 2868 if (m == NULL) { 2869 if (lockp == NULL) { 2870 PV_STAT(pc_chunk_tryfail++); 2871 return (NULL); 2872 } 2873 m = reclaim_pv_chunk(pmap, lockp); 2874 if (m == NULL) 2875 goto retry; 2876 } 2877 PV_STAT(atomic_add_int(&pc_chunk_count, 1)); 2878 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1)); 2879 dump_add_page(m->phys_addr); 2880 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 2881 pc->pc_pmap = pmap; 2882 memcpy(pc->pc_map, pc_freemask, sizeof(pc_freemask)); 2883 pc->pc_map[0] &= ~1ul; /* preallocated bit 0 */ 2884 pvc = &pv_chunks[vm_page_domain(m)]; 2885 mtx_lock(&pvc->pvc_lock); 2886 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru); 2887 mtx_unlock(&pvc->pvc_lock); 2888 pv = &pc->pc_pventry[0]; 2889 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2890 PV_STAT(atomic_add_long(&pv_entry_count, 1)); 2891 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1)); 2892 return (pv); 2893 } 2894 2895 /* 2896 * Ensure that the number of spare PV entries in the specified pmap meets or 2897 * exceeds the given count, "needed". 2898 * 2899 * The given PV list lock may be released. 2900 */ 2901 static void 2902 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp) 2903 { 2904 struct pv_chunks_list *pvc; 2905 struct pch new_tail[PMAP_MEMDOM]; 2906 struct pv_chunk *pc; 2907 vm_page_t m; 2908 int avail, free, i; 2909 bool reclaimed; 2910 2911 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2912 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL")); 2913 2914 /* 2915 * Newly allocated PV chunks must be stored in a private list until 2916 * the required number of PV chunks have been allocated. Otherwise, 2917 * reclaim_pv_chunk() could recycle one of these chunks. In 2918 * contrast, these chunks must be added to the pmap upon allocation. 2919 */ 2920 for (i = 0; i < PMAP_MEMDOM; i++) 2921 TAILQ_INIT(&new_tail[i]); 2922 retry: 2923 avail = 0; 2924 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) { 2925 bit_count((bitstr_t *)pc->pc_map, 0, 2926 sizeof(pc->pc_map) * NBBY, &free); 2927 if (free == 0) 2928 break; 2929 avail += free; 2930 if (avail >= needed) 2931 break; 2932 } 2933 for (reclaimed = false; avail < needed; avail += _NPCPV) { 2934 m = vm_page_alloc_noobj(VM_ALLOC_WIRED); 2935 if (m == NULL) { 2936 m = reclaim_pv_chunk(pmap, lockp); 2937 if (m == NULL) 2938 goto retry; 2939 reclaimed = true; 2940 } 2941 PV_STAT(atomic_add_int(&pc_chunk_count, 1)); 2942 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1)); 2943 dump_add_page(m->phys_addr); 2944 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 2945 pc->pc_pmap = pmap; 2946 memcpy(pc->pc_map, pc_freemask, sizeof(pc_freemask)); 2947 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2948 TAILQ_INSERT_TAIL(&new_tail[vm_page_domain(m)], pc, pc_lru); 2949 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV)); 2950 2951 /* 2952 * The reclaim might have freed a chunk from the current pmap. 2953 * If that chunk contained available entries, we need to 2954 * re-count the number of available entries. 2955 */ 2956 if (reclaimed) 2957 goto retry; 2958 } 2959 for (i = 0; i < vm_ndomains; i++) { 2960 if (TAILQ_EMPTY(&new_tail[i])) 2961 continue; 2962 pvc = &pv_chunks[i]; 2963 mtx_lock(&pvc->pvc_lock); 2964 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru); 2965 mtx_unlock(&pvc->pvc_lock); 2966 } 2967 } 2968 2969 /* 2970 * First find and then remove the pv entry for the specified pmap and virtual 2971 * address from the specified pv list. Returns the pv entry if found and NULL 2972 * otherwise. This operation can be performed on pv lists for either 4KB or 2973 * 2MB page mappings. 2974 */ 2975 static __inline pv_entry_t 2976 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2977 { 2978 pv_entry_t pv; 2979 2980 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2981 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2982 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2983 pvh->pv_gen++; 2984 break; 2985 } 2986 } 2987 return (pv); 2988 } 2989 2990 /* 2991 * After demotion from a 2MB page mapping to 512 4KB page mappings, 2992 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv 2993 * entries for each of the 4KB page mappings. 2994 */ 2995 static void 2996 pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 2997 struct rwlock **lockp) 2998 { 2999 struct md_page *pvh; 3000 struct pv_chunk *pc; 3001 pv_entry_t pv; 3002 vm_offset_t va_last; 3003 vm_page_t m; 3004 int bit, field; 3005 3006 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3007 KASSERT((va & L2_OFFSET) == 0, 3008 ("pmap_pv_demote_l2: va is not 2mpage aligned")); 3009 KASSERT((pa & L2_OFFSET) == 0, 3010 ("pmap_pv_demote_l2: pa is not 2mpage aligned")); 3011 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 3012 3013 /* 3014 * Transfer the 2mpage's pv entry for this mapping to the first 3015 * page's pv list. Once this transfer begins, the pv list lock 3016 * must not be released until the last pv entry is reinstantiated. 3017 */ 3018 pvh = pa_to_pvh(pa); 3019 pv = pmap_pvh_remove(pvh, pmap, va); 3020 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found")); 3021 m = PHYS_TO_VM_PAGE(pa); 3022 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3023 m->md.pv_gen++; 3024 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */ 3025 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1)); 3026 va_last = va + L2_SIZE - PAGE_SIZE; 3027 for (;;) { 3028 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 3029 KASSERT(!pc_is_full(pc), ("pmap_pv_demote_l2: missing spare")); 3030 for (field = 0; field < _NPCM; field++) { 3031 while (pc->pc_map[field]) { 3032 bit = ffsl(pc->pc_map[field]) - 1; 3033 pc->pc_map[field] &= ~(1ul << bit); 3034 pv = &pc->pc_pventry[field * 64 + bit]; 3035 va += PAGE_SIZE; 3036 pv->pv_va = va; 3037 m++; 3038 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3039 ("pmap_pv_demote_l2: page %p is not managed", m)); 3040 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3041 m->md.pv_gen++; 3042 if (va == va_last) 3043 goto out; 3044 } 3045 } 3046 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3047 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 3048 } 3049 out: 3050 if (pc_is_full(pc)) { 3051 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3052 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 3053 } 3054 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1)); 3055 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1)); 3056 } 3057 3058 /* 3059 * First find and then destroy the pv entry for the specified pmap and virtual 3060 * address. This operation can be performed on pv lists for either 4KB or 2MB 3061 * page mappings. 3062 */ 3063 static void 3064 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 3065 { 3066 pv_entry_t pv; 3067 3068 pv = pmap_pvh_remove(pvh, pmap, va); 3069 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 3070 free_pv_entry(pmap, pv); 3071 } 3072 3073 /* 3074 * Conditionally create the PV entry for a 4KB page mapping if the required 3075 * memory can be allocated without resorting to reclamation. 3076 */ 3077 static boolean_t 3078 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m, 3079 struct rwlock **lockp) 3080 { 3081 pv_entry_t pv; 3082 3083 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3084 /* Pass NULL instead of the lock pointer to disable reclamation. */ 3085 if ((pv = get_pv_entry(pmap, NULL)) != NULL) { 3086 pv->pv_va = va; 3087 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 3088 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3089 m->md.pv_gen++; 3090 return (TRUE); 3091 } else 3092 return (FALSE); 3093 } 3094 3095 /* 3096 * Create the PV entry for a 2MB page mapping. Always returns true unless the 3097 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns 3098 * false if the PV entry cannot be allocated without resorting to reclamation. 3099 */ 3100 static bool 3101 pmap_pv_insert_l2(pmap_t pmap, vm_offset_t va, pd_entry_t l2e, u_int flags, 3102 struct rwlock **lockp) 3103 { 3104 struct md_page *pvh; 3105 pv_entry_t pv; 3106 vm_paddr_t pa; 3107 3108 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3109 /* Pass NULL instead of the lock pointer to disable reclamation. */ 3110 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ? 3111 NULL : lockp)) == NULL) 3112 return (false); 3113 pv->pv_va = va; 3114 pa = l2e & ~ATTR_MASK; 3115 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 3116 pvh = pa_to_pvh(pa); 3117 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 3118 pvh->pv_gen++; 3119 return (true); 3120 } 3121 3122 static void 3123 pmap_remove_kernel_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va) 3124 { 3125 pt_entry_t newl2, oldl2 __diagused; 3126 vm_page_t ml3; 3127 vm_paddr_t ml3pa; 3128 3129 KASSERT(!VIRT_IN_DMAP(va), ("removing direct mapping of %#lx", va)); 3130 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap)); 3131 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3132 3133 ml3 = pmap_remove_pt_page(pmap, va); 3134 if (ml3 == NULL) 3135 panic("pmap_remove_kernel_l2: Missing pt page"); 3136 3137 ml3pa = VM_PAGE_TO_PHYS(ml3); 3138 newl2 = ml3pa | L2_TABLE; 3139 3140 /* 3141 * If this page table page was unmapped by a promotion, then it 3142 * contains valid mappings. Zero it to invalidate those mappings. 3143 */ 3144 if (ml3->valid != 0) 3145 pagezero((void *)PHYS_TO_DMAP(ml3pa)); 3146 3147 /* 3148 * Demote the mapping. The caller must have already invalidated the 3149 * mapping (i.e., the "break" in break-before-make). 3150 */ 3151 oldl2 = pmap_load_store(l2, newl2); 3152 KASSERT(oldl2 == 0, ("%s: found existing mapping at %p: %#lx", 3153 __func__, l2, oldl2)); 3154 } 3155 3156 /* 3157 * pmap_remove_l2: Do the things to unmap a level 2 superpage. 3158 */ 3159 static int 3160 pmap_remove_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, 3161 pd_entry_t l1e, struct spglist *free, struct rwlock **lockp) 3162 { 3163 struct md_page *pvh; 3164 pt_entry_t old_l2; 3165 vm_page_t m, ml3, mt; 3166 3167 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3168 KASSERT((sva & L2_OFFSET) == 0, ("pmap_remove_l2: sva is not aligned")); 3169 old_l2 = pmap_load_clear(l2); 3170 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK, 3171 ("pmap_remove_l2: L2e %lx is not a block mapping", old_l2)); 3172 3173 /* 3174 * Since a promotion must break the 4KB page mappings before making 3175 * the 2MB page mapping, a pmap_invalidate_page() suffices. 3176 */ 3177 pmap_invalidate_page(pmap, sva, true); 3178 3179 if (old_l2 & ATTR_SW_WIRED) 3180 pmap->pm_stats.wired_count -= L2_SIZE / PAGE_SIZE; 3181 pmap_resident_count_dec(pmap, L2_SIZE / PAGE_SIZE); 3182 if (old_l2 & ATTR_SW_MANAGED) { 3183 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK); 3184 pvh = page_to_pvh(m); 3185 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, old_l2 & ~ATTR_MASK); 3186 pmap_pvh_free(pvh, pmap, sva); 3187 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) { 3188 if (pmap_pte_dirty(pmap, old_l2)) 3189 vm_page_dirty(mt); 3190 if (old_l2 & ATTR_AF) 3191 vm_page_aflag_set(mt, PGA_REFERENCED); 3192 if (TAILQ_EMPTY(&mt->md.pv_list) && 3193 TAILQ_EMPTY(&pvh->pv_list)) 3194 vm_page_aflag_clear(mt, PGA_WRITEABLE); 3195 } 3196 } 3197 if (pmap == kernel_pmap) { 3198 pmap_remove_kernel_l2(pmap, l2, sva); 3199 } else { 3200 ml3 = pmap_remove_pt_page(pmap, sva); 3201 if (ml3 != NULL) { 3202 KASSERT(ml3->valid == VM_PAGE_BITS_ALL, 3203 ("pmap_remove_l2: l3 page not promoted")); 3204 pmap_resident_count_dec(pmap, 1); 3205 KASSERT(ml3->ref_count == NL3PG, 3206 ("pmap_remove_l2: l3 page ref count error")); 3207 ml3->ref_count = 0; 3208 pmap_add_delayed_free_list(ml3, free, FALSE); 3209 } 3210 } 3211 return (pmap_unuse_pt(pmap, sva, l1e, free)); 3212 } 3213 3214 /* 3215 * pmap_remove_l3: do the things to unmap a page in a process 3216 */ 3217 static int 3218 pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va, 3219 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp) 3220 { 3221 struct md_page *pvh; 3222 pt_entry_t old_l3; 3223 vm_page_t m; 3224 3225 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3226 old_l3 = pmap_load_clear(l3); 3227 pmap_invalidate_page(pmap, va, true); 3228 if (old_l3 & ATTR_SW_WIRED) 3229 pmap->pm_stats.wired_count -= 1; 3230 pmap_resident_count_dec(pmap, 1); 3231 if (old_l3 & ATTR_SW_MANAGED) { 3232 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK); 3233 if (pmap_pte_dirty(pmap, old_l3)) 3234 vm_page_dirty(m); 3235 if (old_l3 & ATTR_AF) 3236 vm_page_aflag_set(m, PGA_REFERENCED); 3237 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 3238 pmap_pvh_free(&m->md, pmap, va); 3239 if (TAILQ_EMPTY(&m->md.pv_list) && 3240 (m->flags & PG_FICTITIOUS) == 0) { 3241 pvh = page_to_pvh(m); 3242 if (TAILQ_EMPTY(&pvh->pv_list)) 3243 vm_page_aflag_clear(m, PGA_WRITEABLE); 3244 } 3245 } 3246 return (pmap_unuse_pt(pmap, va, l2e, free)); 3247 } 3248 3249 /* 3250 * Remove the specified range of addresses from the L3 page table that is 3251 * identified by the given L2 entry. 3252 */ 3253 static void 3254 pmap_remove_l3_range(pmap_t pmap, pd_entry_t l2e, vm_offset_t sva, 3255 vm_offset_t eva, struct spglist *free, struct rwlock **lockp) 3256 { 3257 struct md_page *pvh; 3258 struct rwlock *new_lock; 3259 pt_entry_t *l3, old_l3; 3260 vm_offset_t va; 3261 vm_page_t l3pg, m; 3262 3263 KASSERT(ADDR_IS_CANONICAL(sva), 3264 ("%s: Start address not in canonical form: %lx", __func__, sva)); 3265 KASSERT(ADDR_IS_CANONICAL(eva) || eva == VM_MAX_USER_ADDRESS, 3266 ("%s: End address not in canonical form: %lx", __func__, eva)); 3267 3268 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3269 KASSERT(rounddown2(sva, L2_SIZE) + L2_SIZE == roundup2(eva, L2_SIZE), 3270 ("pmap_remove_l3_range: range crosses an L3 page table boundary")); 3271 l3pg = !ADDR_IS_KERNEL(sva) ? PHYS_TO_VM_PAGE(l2e & ~ATTR_MASK) : NULL; 3272 va = eva; 3273 for (l3 = pmap_l2_to_l3(&l2e, sva); sva != eva; l3++, sva += L3_SIZE) { 3274 if (!pmap_l3_valid(pmap_load(l3))) { 3275 if (va != eva) { 3276 pmap_invalidate_range(pmap, va, sva, true); 3277 va = eva; 3278 } 3279 continue; 3280 } 3281 old_l3 = pmap_load_clear(l3); 3282 if ((old_l3 & ATTR_SW_WIRED) != 0) 3283 pmap->pm_stats.wired_count--; 3284 pmap_resident_count_dec(pmap, 1); 3285 if ((old_l3 & ATTR_SW_MANAGED) != 0) { 3286 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK); 3287 if (pmap_pte_dirty(pmap, old_l3)) 3288 vm_page_dirty(m); 3289 if ((old_l3 & ATTR_AF) != 0) 3290 vm_page_aflag_set(m, PGA_REFERENCED); 3291 new_lock = PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m)); 3292 if (new_lock != *lockp) { 3293 if (*lockp != NULL) { 3294 /* 3295 * Pending TLB invalidations must be 3296 * performed before the PV list lock is 3297 * released. Otherwise, a concurrent 3298 * pmap_remove_all() on a physical page 3299 * could return while a stale TLB entry 3300 * still provides access to that page. 3301 */ 3302 if (va != eva) { 3303 pmap_invalidate_range(pmap, va, 3304 sva, true); 3305 va = eva; 3306 } 3307 rw_wunlock(*lockp); 3308 } 3309 *lockp = new_lock; 3310 rw_wlock(*lockp); 3311 } 3312 pmap_pvh_free(&m->md, pmap, sva); 3313 if (TAILQ_EMPTY(&m->md.pv_list) && 3314 (m->flags & PG_FICTITIOUS) == 0) { 3315 pvh = page_to_pvh(m); 3316 if (TAILQ_EMPTY(&pvh->pv_list)) 3317 vm_page_aflag_clear(m, PGA_WRITEABLE); 3318 } 3319 } 3320 if (l3pg != NULL && pmap_unwire_l3(pmap, sva, l3pg, free)) { 3321 /* 3322 * _pmap_unwire_l3() has already invalidated the TLB 3323 * entries at all levels for "sva". So, we need not 3324 * perform "sva += L3_SIZE;" here. Moreover, we need 3325 * not perform "va = sva;" if "sva" is at the start 3326 * of a new valid range consisting of a single page. 3327 */ 3328 break; 3329 } 3330 if (va == eva) 3331 va = sva; 3332 } 3333 if (va != eva) 3334 pmap_invalidate_range(pmap, va, sva, true); 3335 } 3336 3337 /* 3338 * Remove the given range of addresses from the specified map. 3339 * 3340 * It is assumed that the start and end are properly 3341 * rounded to the page size. 3342 */ 3343 void 3344 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3345 { 3346 struct rwlock *lock; 3347 vm_offset_t va_next; 3348 pd_entry_t *l0, *l1, *l2; 3349 pt_entry_t l3_paddr; 3350 struct spglist free; 3351 3352 /* 3353 * Perform an unsynchronized read. This is, however, safe. 3354 */ 3355 if (pmap->pm_stats.resident_count == 0) 3356 return; 3357 3358 SLIST_INIT(&free); 3359 3360 PMAP_LOCK(pmap); 3361 3362 lock = NULL; 3363 for (; sva < eva; sva = va_next) { 3364 if (pmap->pm_stats.resident_count == 0) 3365 break; 3366 3367 l0 = pmap_l0(pmap, sva); 3368 if (pmap_load(l0) == 0) { 3369 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 3370 if (va_next < sva) 3371 va_next = eva; 3372 continue; 3373 } 3374 3375 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 3376 if (va_next < sva) 3377 va_next = eva; 3378 l1 = pmap_l0_to_l1(l0, sva); 3379 if (pmap_load(l1) == 0) 3380 continue; 3381 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) { 3382 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 3383 KASSERT(va_next <= eva, 3384 ("partial update of non-transparent 1G page " 3385 "l1 %#lx sva %#lx eva %#lx va_next %#lx", 3386 pmap_load(l1), sva, eva, va_next)); 3387 MPASS(pmap != kernel_pmap); 3388 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0); 3389 pmap_clear(l1); 3390 pmap_invalidate_page(pmap, sva, true); 3391 pmap_resident_count_dec(pmap, L1_SIZE / PAGE_SIZE); 3392 pmap_unuse_pt(pmap, sva, pmap_load(l0), &free); 3393 continue; 3394 } 3395 3396 /* 3397 * Calculate index for next page table. 3398 */ 3399 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 3400 if (va_next < sva) 3401 va_next = eva; 3402 3403 l2 = pmap_l1_to_l2(l1, sva); 3404 if (l2 == NULL) 3405 continue; 3406 3407 l3_paddr = pmap_load(l2); 3408 3409 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) { 3410 if (sva + L2_SIZE == va_next && eva >= va_next) { 3411 pmap_remove_l2(pmap, l2, sva, pmap_load(l1), 3412 &free, &lock); 3413 continue; 3414 } else if (pmap_demote_l2_locked(pmap, l2, sva, 3415 &lock) == NULL) 3416 continue; 3417 l3_paddr = pmap_load(l2); 3418 } 3419 3420 /* 3421 * Weed out invalid mappings. 3422 */ 3423 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE) 3424 continue; 3425 3426 /* 3427 * Limit our scan to either the end of the va represented 3428 * by the current page table page, or to the end of the 3429 * range being removed. 3430 */ 3431 if (va_next > eva) 3432 va_next = eva; 3433 3434 pmap_remove_l3_range(pmap, l3_paddr, sva, va_next, &free, 3435 &lock); 3436 } 3437 if (lock != NULL) 3438 rw_wunlock(lock); 3439 PMAP_UNLOCK(pmap); 3440 vm_page_free_pages_toq(&free, true); 3441 } 3442 3443 /* 3444 * Routine: pmap_remove_all 3445 * Function: 3446 * Removes this physical page from 3447 * all physical maps in which it resides. 3448 * Reflects back modify bits to the pager. 3449 * 3450 * Notes: 3451 * Original versions of this routine were very 3452 * inefficient because they iteratively called 3453 * pmap_remove (slow...) 3454 */ 3455 3456 void 3457 pmap_remove_all(vm_page_t m) 3458 { 3459 struct md_page *pvh; 3460 pv_entry_t pv; 3461 pmap_t pmap; 3462 struct rwlock *lock; 3463 pd_entry_t *pde, tpde; 3464 pt_entry_t *pte, tpte; 3465 vm_offset_t va; 3466 struct spglist free; 3467 int lvl, pvh_gen, md_gen; 3468 3469 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3470 ("pmap_remove_all: page %p is not managed", m)); 3471 SLIST_INIT(&free); 3472 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3473 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m); 3474 rw_wlock(lock); 3475 retry: 3476 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 3477 pmap = PV_PMAP(pv); 3478 if (!PMAP_TRYLOCK(pmap)) { 3479 pvh_gen = pvh->pv_gen; 3480 rw_wunlock(lock); 3481 PMAP_LOCK(pmap); 3482 rw_wlock(lock); 3483 if (pvh_gen != pvh->pv_gen) { 3484 PMAP_UNLOCK(pmap); 3485 goto retry; 3486 } 3487 } 3488 va = pv->pv_va; 3489 pte = pmap_pte_exists(pmap, va, 2, __func__); 3490 pmap_demote_l2_locked(pmap, pte, va, &lock); 3491 PMAP_UNLOCK(pmap); 3492 } 3493 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3494 pmap = PV_PMAP(pv); 3495 PMAP_ASSERT_STAGE1(pmap); 3496 if (!PMAP_TRYLOCK(pmap)) { 3497 pvh_gen = pvh->pv_gen; 3498 md_gen = m->md.pv_gen; 3499 rw_wunlock(lock); 3500 PMAP_LOCK(pmap); 3501 rw_wlock(lock); 3502 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 3503 PMAP_UNLOCK(pmap); 3504 goto retry; 3505 } 3506 } 3507 pmap_resident_count_dec(pmap, 1); 3508 3509 pde = pmap_pde(pmap, pv->pv_va, &lvl); 3510 KASSERT(pde != NULL, 3511 ("pmap_remove_all: no page directory entry found")); 3512 KASSERT(lvl == 2, 3513 ("pmap_remove_all: invalid pde level %d", lvl)); 3514 tpde = pmap_load(pde); 3515 3516 pte = pmap_l2_to_l3(pde, pv->pv_va); 3517 tpte = pmap_load_clear(pte); 3518 if (tpte & ATTR_SW_WIRED) 3519 pmap->pm_stats.wired_count--; 3520 if ((tpte & ATTR_AF) != 0) { 3521 pmap_invalidate_page(pmap, pv->pv_va, true); 3522 vm_page_aflag_set(m, PGA_REFERENCED); 3523 } 3524 3525 /* 3526 * Update the vm_page_t clean and reference bits. 3527 */ 3528 if (pmap_pte_dirty(pmap, tpte)) 3529 vm_page_dirty(m); 3530 pmap_unuse_pt(pmap, pv->pv_va, tpde, &free); 3531 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3532 m->md.pv_gen++; 3533 free_pv_entry(pmap, pv); 3534 PMAP_UNLOCK(pmap); 3535 } 3536 vm_page_aflag_clear(m, PGA_WRITEABLE); 3537 rw_wunlock(lock); 3538 vm_page_free_pages_toq(&free, true); 3539 } 3540 3541 /* 3542 * Masks and sets bits in a level 2 page table entries in the specified pmap 3543 */ 3544 static void 3545 pmap_protect_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t sva, pt_entry_t mask, 3546 pt_entry_t nbits) 3547 { 3548 pd_entry_t old_l2; 3549 vm_page_t m, mt; 3550 3551 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3552 PMAP_ASSERT_STAGE1(pmap); 3553 KASSERT((sva & L2_OFFSET) == 0, 3554 ("pmap_protect_l2: sva is not 2mpage aligned")); 3555 old_l2 = pmap_load(l2); 3556 KASSERT((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK, 3557 ("pmap_protect_l2: L2e %lx is not a block mapping", old_l2)); 3558 3559 /* 3560 * Return if the L2 entry already has the desired access restrictions 3561 * in place. 3562 */ 3563 if ((old_l2 & mask) == nbits) 3564 return; 3565 3566 while (!atomic_fcmpset_64(l2, &old_l2, (old_l2 & ~mask) | nbits)) 3567 cpu_spinwait(); 3568 3569 /* 3570 * When a dirty read/write superpage mapping is write protected, 3571 * update the dirty field of each of the superpage's constituent 4KB 3572 * pages. 3573 */ 3574 if ((old_l2 & ATTR_SW_MANAGED) != 0 && 3575 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 && 3576 pmap_pte_dirty(pmap, old_l2)) { 3577 m = PHYS_TO_VM_PAGE(old_l2 & ~ATTR_MASK); 3578 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 3579 vm_page_dirty(mt); 3580 } 3581 3582 /* 3583 * Since a promotion must break the 4KB page mappings before making 3584 * the 2MB page mapping, a pmap_invalidate_page() suffices. 3585 */ 3586 pmap_invalidate_page(pmap, sva, true); 3587 } 3588 3589 /* 3590 * Masks and sets bits in last level page table entries in the specified 3591 * pmap and range 3592 */ 3593 static void 3594 pmap_mask_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, pt_entry_t mask, 3595 pt_entry_t nbits, bool invalidate) 3596 { 3597 vm_offset_t va, va_next; 3598 pd_entry_t *l0, *l1, *l2; 3599 pt_entry_t *l3p, l3; 3600 3601 PMAP_LOCK(pmap); 3602 for (; sva < eva; sva = va_next) { 3603 l0 = pmap_l0(pmap, sva); 3604 if (pmap_load(l0) == 0) { 3605 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 3606 if (va_next < sva) 3607 va_next = eva; 3608 continue; 3609 } 3610 3611 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 3612 if (va_next < sva) 3613 va_next = eva; 3614 l1 = pmap_l0_to_l1(l0, sva); 3615 if (pmap_load(l1) == 0) 3616 continue; 3617 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) { 3618 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 3619 KASSERT(va_next <= eva, 3620 ("partial update of non-transparent 1G page " 3621 "l1 %#lx sva %#lx eva %#lx va_next %#lx", 3622 pmap_load(l1), sva, eva, va_next)); 3623 MPASS((pmap_load(l1) & ATTR_SW_MANAGED) == 0); 3624 if ((pmap_load(l1) & mask) != nbits) { 3625 pmap_store(l1, (pmap_load(l1) & ~mask) | nbits); 3626 if (invalidate) 3627 pmap_invalidate_page(pmap, sva, true); 3628 } 3629 continue; 3630 } 3631 3632 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 3633 if (va_next < sva) 3634 va_next = eva; 3635 3636 l2 = pmap_l1_to_l2(l1, sva); 3637 if (pmap_load(l2) == 0) 3638 continue; 3639 3640 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) { 3641 if (sva + L2_SIZE == va_next && eva >= va_next) { 3642 pmap_protect_l2(pmap, l2, sva, mask, nbits); 3643 continue; 3644 } else if (pmap_demote_l2(pmap, l2, sva) == NULL) 3645 continue; 3646 } 3647 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE, 3648 ("pmap_protect: Invalid L2 entry after demotion")); 3649 3650 if (va_next > eva) 3651 va_next = eva; 3652 3653 va = va_next; 3654 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++, 3655 sva += L3_SIZE) { 3656 l3 = pmap_load(l3p); 3657 3658 /* 3659 * Go to the next L3 entry if the current one is 3660 * invalid or already has the desired access 3661 * restrictions in place. (The latter case occurs 3662 * frequently. For example, in a "buildworld" 3663 * workload, almost 1 out of 4 L3 entries already 3664 * have the desired restrictions.) 3665 */ 3666 if (!pmap_l3_valid(l3) || (l3 & mask) == nbits) { 3667 if (va != va_next) { 3668 if (invalidate) 3669 pmap_invalidate_range(pmap, 3670 va, sva, true); 3671 va = va_next; 3672 } 3673 continue; 3674 } 3675 3676 while (!atomic_fcmpset_64(l3p, &l3, (l3 & ~mask) | 3677 nbits)) 3678 cpu_spinwait(); 3679 3680 /* 3681 * When a dirty read/write mapping is write protected, 3682 * update the page's dirty field. 3683 */ 3684 if ((l3 & ATTR_SW_MANAGED) != 0 && 3685 (nbits & ATTR_S1_AP(ATTR_S1_AP_RO)) != 0 && 3686 pmap_pte_dirty(pmap, l3)) 3687 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & ~ATTR_MASK)); 3688 3689 if (va == va_next) 3690 va = sva; 3691 } 3692 if (va != va_next && invalidate) 3693 pmap_invalidate_range(pmap, va, sva, true); 3694 } 3695 PMAP_UNLOCK(pmap); 3696 } 3697 3698 /* 3699 * Set the physical protection on the 3700 * specified range of this map as requested. 3701 */ 3702 void 3703 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3704 { 3705 pt_entry_t mask, nbits; 3706 3707 PMAP_ASSERT_STAGE1(pmap); 3708 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot)); 3709 if (prot == VM_PROT_NONE) { 3710 pmap_remove(pmap, sva, eva); 3711 return; 3712 } 3713 3714 mask = nbits = 0; 3715 if ((prot & VM_PROT_WRITE) == 0) { 3716 mask |= ATTR_S1_AP_RW_BIT | ATTR_SW_DBM; 3717 nbits |= ATTR_S1_AP(ATTR_S1_AP_RO); 3718 } 3719 if ((prot & VM_PROT_EXECUTE) == 0) { 3720 mask |= ATTR_S1_XN; 3721 nbits |= ATTR_S1_XN; 3722 } 3723 if (mask == 0) 3724 return; 3725 3726 pmap_mask_set(pmap, sva, eva, mask, nbits, true); 3727 } 3728 3729 void 3730 pmap_disable_promotion(vm_offset_t sva, vm_size_t size) 3731 { 3732 3733 MPASS((sva & L3_OFFSET) == 0); 3734 MPASS(((sva + size) & L3_OFFSET) == 0); 3735 3736 pmap_mask_set(kernel_pmap, sva, sva + size, ATTR_SW_NO_PROMOTE, 3737 ATTR_SW_NO_PROMOTE, false); 3738 } 3739 3740 /* 3741 * Inserts the specified page table page into the specified pmap's collection 3742 * of idle page table pages. Each of a pmap's page table pages is responsible 3743 * for mapping a distinct range of virtual addresses. The pmap's collection is 3744 * ordered by this virtual address range. 3745 * 3746 * If "promoted" is false, then the page table page "mpte" must be zero filled. 3747 */ 3748 static __inline int 3749 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted) 3750 { 3751 3752 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3753 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0; 3754 return (vm_radix_insert(&pmap->pm_root, mpte)); 3755 } 3756 3757 /* 3758 * Removes the page table page mapping the specified virtual address from the 3759 * specified pmap's collection of idle page table pages, and returns it. 3760 * Otherwise, returns NULL if there is no page table page corresponding to the 3761 * specified virtual address. 3762 */ 3763 static __inline vm_page_t 3764 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va) 3765 { 3766 3767 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3768 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va))); 3769 } 3770 3771 /* 3772 * Performs a break-before-make update of a pmap entry. This is needed when 3773 * either promoting or demoting pages to ensure the TLB doesn't get into an 3774 * inconsistent state. 3775 */ 3776 static void 3777 pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte, 3778 vm_offset_t va, vm_size_t size) 3779 { 3780 register_t intr; 3781 3782 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3783 3784 if ((newpte & ATTR_SW_NO_PROMOTE) != 0) 3785 panic("%s: Updating non-promote pte", __func__); 3786 3787 /* 3788 * Ensure we don't get switched out with the page table in an 3789 * inconsistent state. We also need to ensure no interrupts fire 3790 * as they may make use of an address we are about to invalidate. 3791 */ 3792 intr = intr_disable(); 3793 3794 /* 3795 * Clear the old mapping's valid bit, but leave the rest of the entry 3796 * unchanged, so that a lockless, concurrent pmap_kextract() can still 3797 * lookup the physical address. 3798 */ 3799 pmap_clear_bits(pte, ATTR_DESCR_VALID); 3800 3801 /* 3802 * When promoting, the L{1,2}_TABLE entry that is being replaced might 3803 * be cached, so we invalidate intermediate entries as well as final 3804 * entries. 3805 */ 3806 pmap_invalidate_range(pmap, va, va + size, false); 3807 3808 /* Create the new mapping */ 3809 pmap_store(pte, newpte); 3810 dsb(ishst); 3811 3812 intr_restore(intr); 3813 } 3814 3815 #if VM_NRESERVLEVEL > 0 3816 /* 3817 * After promotion from 512 4KB page mappings to a single 2MB page mapping, 3818 * replace the many pv entries for the 4KB page mappings by a single pv entry 3819 * for the 2MB page mapping. 3820 */ 3821 static void 3822 pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 3823 struct rwlock **lockp) 3824 { 3825 struct md_page *pvh; 3826 pv_entry_t pv; 3827 vm_offset_t va_last; 3828 vm_page_t m; 3829 3830 KASSERT((pa & L2_OFFSET) == 0, 3831 ("pmap_pv_promote_l2: pa is not 2mpage aligned")); 3832 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 3833 3834 /* 3835 * Transfer the first page's pv entry for this mapping to the 2mpage's 3836 * pv list. Aside from avoiding the cost of a call to get_pv_entry(), 3837 * a transfer avoids the possibility that get_pv_entry() calls 3838 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the 3839 * mappings that is being promoted. 3840 */ 3841 m = PHYS_TO_VM_PAGE(pa); 3842 va = va & ~L2_OFFSET; 3843 pv = pmap_pvh_remove(&m->md, pmap, va); 3844 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found")); 3845 pvh = page_to_pvh(m); 3846 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 3847 pvh->pv_gen++; 3848 /* Free the remaining NPTEPG - 1 pv entries. */ 3849 va_last = va + L2_SIZE - PAGE_SIZE; 3850 do { 3851 m++; 3852 va += PAGE_SIZE; 3853 pmap_pvh_free(&m->md, pmap, va); 3854 } while (va < va_last); 3855 } 3856 3857 /* 3858 * Tries to promote the 512, contiguous 4KB page mappings that are within a 3859 * single level 2 table entry to a single 2MB page mapping. For promotion 3860 * to occur, two conditions must be met: (1) the 4KB page mappings must map 3861 * aligned, contiguous physical memory and (2) the 4KB page mappings must have 3862 * identical characteristics. 3863 */ 3864 static void 3865 pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va, vm_page_t mpte, 3866 struct rwlock **lockp) 3867 { 3868 pt_entry_t *firstl3, *l3, newl2, oldl3, pa; 3869 3870 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3871 PMAP_ASSERT_STAGE1(pmap); 3872 3873 firstl3 = (pt_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK); 3874 newl2 = pmap_load(firstl3); 3875 3876 if (((newl2 & (~ATTR_MASK | ATTR_AF)) & L2_OFFSET) != ATTR_AF || 3877 (newl2 & ATTR_SW_NO_PROMOTE) != 0) { 3878 atomic_add_long(&pmap_l2_p_failures, 1); 3879 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx" 3880 " in pmap %p", va, pmap); 3881 return; 3882 } 3883 3884 setl2: 3885 if ((newl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == 3886 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) { 3887 /* 3888 * When the mapping is clean, i.e., ATTR_S1_AP_RO is set, 3889 * ATTR_SW_DBM can be cleared without a TLB invalidation. 3890 */ 3891 if (!atomic_fcmpset_64(firstl3, &newl2, newl2 & ~ATTR_SW_DBM)) 3892 goto setl2; 3893 newl2 &= ~ATTR_SW_DBM; 3894 } 3895 3896 pa = newl2 + L2_SIZE - PAGE_SIZE; 3897 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) { 3898 oldl3 = pmap_load(l3); 3899 setl3: 3900 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == 3901 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM)) { 3902 /* 3903 * When the mapping is clean, i.e., ATTR_S1_AP_RO is 3904 * set, ATTR_SW_DBM can be cleared without a TLB 3905 * invalidation. 3906 */ 3907 if (!atomic_fcmpset_64(l3, &oldl3, oldl3 & 3908 ~ATTR_SW_DBM)) 3909 goto setl3; 3910 oldl3 &= ~ATTR_SW_DBM; 3911 } 3912 if (oldl3 != pa) { 3913 atomic_add_long(&pmap_l2_p_failures, 1); 3914 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx" 3915 " in pmap %p", va, pmap); 3916 return; 3917 } 3918 pa -= PAGE_SIZE; 3919 } 3920 3921 /* 3922 * Save the page table page in its current state until the L2 3923 * mapping the superpage is demoted by pmap_demote_l2() or 3924 * destroyed by pmap_remove_l3(). 3925 */ 3926 if (mpte == NULL) 3927 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK); 3928 KASSERT(mpte >= vm_page_array && 3929 mpte < &vm_page_array[vm_page_array_size], 3930 ("pmap_promote_l2: page table page is out of range")); 3931 KASSERT(mpte->pindex == pmap_l2_pindex(va), 3932 ("pmap_promote_l2: page table page's pindex is wrong")); 3933 if (pmap_insert_pt_page(pmap, mpte, true)) { 3934 atomic_add_long(&pmap_l2_p_failures, 1); 3935 CTR2(KTR_PMAP, 3936 "pmap_promote_l2: failure for va %#lx in pmap %p", va, 3937 pmap); 3938 return; 3939 } 3940 3941 if ((newl2 & ATTR_SW_MANAGED) != 0) 3942 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp); 3943 3944 newl2 &= ~ATTR_DESCR_MASK; 3945 newl2 |= L2_BLOCK; 3946 3947 pmap_update_entry(pmap, l2, newl2, va & ~L2_OFFSET, L2_SIZE); 3948 3949 atomic_add_long(&pmap_l2_promotions, 1); 3950 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va, 3951 pmap); 3952 } 3953 #endif /* VM_NRESERVLEVEL > 0 */ 3954 3955 static int 3956 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags, 3957 int psind) 3958 { 3959 pd_entry_t *l0p, *l1p, *l2p, origpte; 3960 vm_page_t mp; 3961 3962 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3963 KASSERT(psind > 0 && psind < MAXPAGESIZES, 3964 ("psind %d unexpected", psind)); 3965 KASSERT(((newpte & ~ATTR_MASK) & (pagesizes[psind] - 1)) == 0, 3966 ("unaligned phys address %#lx newpte %#lx psind %d", 3967 (newpte & ~ATTR_MASK), newpte, psind)); 3968 3969 restart: 3970 if (psind == 2) { 3971 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 3972 3973 l0p = pmap_l0(pmap, va); 3974 if ((pmap_load(l0p) & ATTR_DESCR_VALID) == 0) { 3975 mp = _pmap_alloc_l3(pmap, pmap_l0_pindex(va), NULL); 3976 if (mp == NULL) { 3977 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 3978 return (KERN_RESOURCE_SHORTAGE); 3979 PMAP_UNLOCK(pmap); 3980 vm_wait(NULL); 3981 PMAP_LOCK(pmap); 3982 goto restart; 3983 } 3984 l1p = pmap_l0_to_l1(l0p, va); 3985 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va)); 3986 origpte = pmap_load(l1p); 3987 } else { 3988 l1p = pmap_l0_to_l1(l0p, va); 3989 KASSERT(l1p != NULL, ("va %#lx lost l1 entry", va)); 3990 origpte = pmap_load(l1p); 3991 if ((origpte & ATTR_DESCR_VALID) == 0) { 3992 mp = PHYS_TO_VM_PAGE(pmap_load(l0p) & 3993 ~ATTR_MASK); 3994 mp->ref_count++; 3995 } 3996 } 3997 KASSERT(((origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK) && 3998 (origpte & ATTR_DESCR_MASK) == L1_BLOCK) || 3999 (origpte & ATTR_DESCR_VALID) == 0, 4000 ("va %#lx changing 1G phys page l1 %#lx newpte %#lx", 4001 va, origpte, newpte)); 4002 pmap_store(l1p, newpte); 4003 } else /* (psind == 1) */ { 4004 l2p = pmap_l2(pmap, va); 4005 if (l2p == NULL) { 4006 mp = _pmap_alloc_l3(pmap, pmap_l1_pindex(va), NULL); 4007 if (mp == NULL) { 4008 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 4009 return (KERN_RESOURCE_SHORTAGE); 4010 PMAP_UNLOCK(pmap); 4011 vm_wait(NULL); 4012 PMAP_LOCK(pmap); 4013 goto restart; 4014 } 4015 l2p = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp)); 4016 l2p = &l2p[pmap_l2_index(va)]; 4017 origpte = pmap_load(l2p); 4018 } else { 4019 l1p = pmap_l1(pmap, va); 4020 origpte = pmap_load(l2p); 4021 if ((origpte & ATTR_DESCR_VALID) == 0) { 4022 mp = PHYS_TO_VM_PAGE(pmap_load(l1p) & 4023 ~ATTR_MASK); 4024 mp->ref_count++; 4025 } 4026 } 4027 KASSERT((origpte & ATTR_DESCR_VALID) == 0 || 4028 ((origpte & ATTR_DESCR_MASK) == L2_BLOCK && 4029 (origpte & ~ATTR_MASK) == (newpte & ~ATTR_MASK)), 4030 ("va %#lx changing 2M phys page l2 %#lx newpte %#lx", 4031 va, origpte, newpte)); 4032 pmap_store(l2p, newpte); 4033 } 4034 dsb(ishst); 4035 4036 if ((origpte & ATTR_DESCR_VALID) == 0) 4037 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE); 4038 if ((newpte & ATTR_SW_WIRED) != 0 && (origpte & ATTR_SW_WIRED) == 0) 4039 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE; 4040 else if ((newpte & ATTR_SW_WIRED) == 0 && 4041 (origpte & ATTR_SW_WIRED) != 0) 4042 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE; 4043 4044 return (KERN_SUCCESS); 4045 } 4046 4047 /* 4048 * Insert the given physical page (p) at 4049 * the specified virtual address (v) in the 4050 * target physical map with the protection requested. 4051 * 4052 * If specified, the page will be wired down, meaning 4053 * that the related pte can not be reclaimed. 4054 * 4055 * NB: This is the only routine which MAY NOT lazy-evaluate 4056 * or lose information. That is, this routine must actually 4057 * insert this page into the given map NOW. 4058 */ 4059 int 4060 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 4061 u_int flags, int8_t psind) 4062 { 4063 struct rwlock *lock; 4064 pd_entry_t *pde; 4065 pt_entry_t new_l3, orig_l3; 4066 pt_entry_t *l2, *l3; 4067 pv_entry_t pv; 4068 vm_paddr_t opa, pa; 4069 vm_page_t mpte, om; 4070 boolean_t nosleep; 4071 int lvl, rv; 4072 4073 KASSERT(ADDR_IS_CANONICAL(va), 4074 ("%s: Address not in canonical form: %lx", __func__, va)); 4075 4076 va = trunc_page(va); 4077 if ((m->oflags & VPO_UNMANAGED) == 0) 4078 VM_PAGE_OBJECT_BUSY_ASSERT(m); 4079 pa = VM_PAGE_TO_PHYS(m); 4080 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | L3_PAGE); 4081 new_l3 |= pmap_pte_memattr(pmap, m->md.pv_memattr); 4082 new_l3 |= pmap_pte_prot(pmap, prot); 4083 4084 if ((flags & PMAP_ENTER_WIRED) != 0) 4085 new_l3 |= ATTR_SW_WIRED; 4086 if (pmap->pm_stage == PM_STAGE1) { 4087 if (!ADDR_IS_KERNEL(va)) 4088 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN; 4089 else 4090 new_l3 |= ATTR_S1_UXN; 4091 if (pmap != kernel_pmap) 4092 new_l3 |= ATTR_S1_nG; 4093 } else { 4094 /* 4095 * Clear the access flag on executable mappings, this will be 4096 * set later when the page is accessed. The fault handler is 4097 * required to invalidate the I-cache. 4098 * 4099 * TODO: Switch to the valid flag to allow hardware management 4100 * of the access flag. Much of the pmap code assumes the 4101 * valid flag is set and fails to destroy the old page tables 4102 * correctly if it is clear. 4103 */ 4104 if (prot & VM_PROT_EXECUTE) 4105 new_l3 &= ~ATTR_AF; 4106 } 4107 if ((m->oflags & VPO_UNMANAGED) == 0) { 4108 new_l3 |= ATTR_SW_MANAGED; 4109 if ((prot & VM_PROT_WRITE) != 0) { 4110 new_l3 |= ATTR_SW_DBM; 4111 if ((flags & VM_PROT_WRITE) == 0) { 4112 if (pmap->pm_stage == PM_STAGE1) 4113 new_l3 |= ATTR_S1_AP(ATTR_S1_AP_RO); 4114 else 4115 new_l3 &= 4116 ~ATTR_S2_S2AP(ATTR_S2_S2AP_WRITE); 4117 } 4118 } 4119 } 4120 4121 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa); 4122 4123 lock = NULL; 4124 PMAP_LOCK(pmap); 4125 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) { 4126 KASSERT((m->oflags & VPO_UNMANAGED) != 0, 4127 ("managed largepage va %#lx flags %#x", va, flags)); 4128 new_l3 &= ~L3_PAGE; 4129 if (psind == 2) { 4130 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 4131 new_l3 |= L1_BLOCK; 4132 } else /* (psind == 1) */ 4133 new_l3 |= L2_BLOCK; 4134 rv = pmap_enter_largepage(pmap, va, new_l3, flags, psind); 4135 goto out; 4136 } 4137 if (psind == 1) { 4138 /* Assert the required virtual and physical alignment. */ 4139 KASSERT((va & L2_OFFSET) == 0, ("pmap_enter: va unaligned")); 4140 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind")); 4141 rv = pmap_enter_l2(pmap, va, (new_l3 & ~L3_PAGE) | L2_BLOCK, 4142 flags, m, &lock); 4143 goto out; 4144 } 4145 mpte = NULL; 4146 4147 /* 4148 * In the case that a page table page is not 4149 * resident, we are creating it here. 4150 */ 4151 retry: 4152 pde = pmap_pde(pmap, va, &lvl); 4153 if (pde != NULL && lvl == 2) { 4154 l3 = pmap_l2_to_l3(pde, va); 4155 if (!ADDR_IS_KERNEL(va) && mpte == NULL) { 4156 mpte = PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK); 4157 mpte->ref_count++; 4158 } 4159 goto havel3; 4160 } else if (pde != NULL && lvl == 1) { 4161 l2 = pmap_l1_to_l2(pde, va); 4162 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK && 4163 (l3 = pmap_demote_l2_locked(pmap, l2, va, &lock)) != NULL) { 4164 l3 = &l3[pmap_l3_index(va)]; 4165 if (!ADDR_IS_KERNEL(va)) { 4166 mpte = PHYS_TO_VM_PAGE( 4167 pmap_load(l2) & ~ATTR_MASK); 4168 mpte->ref_count++; 4169 } 4170 goto havel3; 4171 } 4172 /* We need to allocate an L3 table. */ 4173 } 4174 if (!ADDR_IS_KERNEL(va)) { 4175 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0; 4176 4177 /* 4178 * We use _pmap_alloc_l3() instead of pmap_alloc_l3() in order 4179 * to handle the possibility that a superpage mapping for "va" 4180 * was created while we slept. 4181 */ 4182 mpte = _pmap_alloc_l3(pmap, pmap_l2_pindex(va), 4183 nosleep ? NULL : &lock); 4184 if (mpte == NULL && nosleep) { 4185 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL"); 4186 rv = KERN_RESOURCE_SHORTAGE; 4187 goto out; 4188 } 4189 goto retry; 4190 } else 4191 panic("pmap_enter: missing L3 table for kernel va %#lx", va); 4192 4193 havel3: 4194 orig_l3 = pmap_load(l3); 4195 opa = orig_l3 & ~ATTR_MASK; 4196 pv = NULL; 4197 4198 /* 4199 * Is the specified virtual address already mapped? 4200 */ 4201 if (pmap_l3_valid(orig_l3)) { 4202 /* 4203 * Only allow adding new entries on stage 2 tables for now. 4204 * This simplifies cache invalidation as we may need to call 4205 * into EL2 to perform such actions. 4206 */ 4207 PMAP_ASSERT_STAGE1(pmap); 4208 /* 4209 * Wiring change, just update stats. We don't worry about 4210 * wiring PT pages as they remain resident as long as there 4211 * are valid mappings in them. Hence, if a user page is wired, 4212 * the PT page will be also. 4213 */ 4214 if ((flags & PMAP_ENTER_WIRED) != 0 && 4215 (orig_l3 & ATTR_SW_WIRED) == 0) 4216 pmap->pm_stats.wired_count++; 4217 else if ((flags & PMAP_ENTER_WIRED) == 0 && 4218 (orig_l3 & ATTR_SW_WIRED) != 0) 4219 pmap->pm_stats.wired_count--; 4220 4221 /* 4222 * Remove the extra PT page reference. 4223 */ 4224 if (mpte != NULL) { 4225 mpte->ref_count--; 4226 KASSERT(mpte->ref_count > 0, 4227 ("pmap_enter: missing reference to page table page," 4228 " va: 0x%lx", va)); 4229 } 4230 4231 /* 4232 * Has the physical page changed? 4233 */ 4234 if (opa == pa) { 4235 /* 4236 * No, might be a protection or wiring change. 4237 */ 4238 if ((orig_l3 & ATTR_SW_MANAGED) != 0 && 4239 (new_l3 & ATTR_SW_DBM) != 0) 4240 vm_page_aflag_set(m, PGA_WRITEABLE); 4241 goto validate; 4242 } 4243 4244 /* 4245 * The physical page has changed. Temporarily invalidate 4246 * the mapping. 4247 */ 4248 orig_l3 = pmap_load_clear(l3); 4249 KASSERT((orig_l3 & ~ATTR_MASK) == opa, 4250 ("pmap_enter: unexpected pa update for %#lx", va)); 4251 if ((orig_l3 & ATTR_SW_MANAGED) != 0) { 4252 om = PHYS_TO_VM_PAGE(opa); 4253 4254 /* 4255 * The pmap lock is sufficient to synchronize with 4256 * concurrent calls to pmap_page_test_mappings() and 4257 * pmap_ts_referenced(). 4258 */ 4259 if (pmap_pte_dirty(pmap, orig_l3)) 4260 vm_page_dirty(om); 4261 if ((orig_l3 & ATTR_AF) != 0) { 4262 pmap_invalidate_page(pmap, va, true); 4263 vm_page_aflag_set(om, PGA_REFERENCED); 4264 } 4265 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa); 4266 pv = pmap_pvh_remove(&om->md, pmap, va); 4267 if ((m->oflags & VPO_UNMANAGED) != 0) 4268 free_pv_entry(pmap, pv); 4269 if ((om->a.flags & PGA_WRITEABLE) != 0 && 4270 TAILQ_EMPTY(&om->md.pv_list) && 4271 ((om->flags & PG_FICTITIOUS) != 0 || 4272 TAILQ_EMPTY(&page_to_pvh(om)->pv_list))) 4273 vm_page_aflag_clear(om, PGA_WRITEABLE); 4274 } else { 4275 KASSERT((orig_l3 & ATTR_AF) != 0, 4276 ("pmap_enter: unmanaged mapping lacks ATTR_AF")); 4277 pmap_invalidate_page(pmap, va, true); 4278 } 4279 orig_l3 = 0; 4280 } else { 4281 /* 4282 * Increment the counters. 4283 */ 4284 if ((new_l3 & ATTR_SW_WIRED) != 0) 4285 pmap->pm_stats.wired_count++; 4286 pmap_resident_count_inc(pmap, 1); 4287 } 4288 /* 4289 * Enter on the PV list if part of our managed memory. 4290 */ 4291 if ((m->oflags & VPO_UNMANAGED) == 0) { 4292 if (pv == NULL) { 4293 pv = get_pv_entry(pmap, &lock); 4294 pv->pv_va = va; 4295 } 4296 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa); 4297 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 4298 m->md.pv_gen++; 4299 if ((new_l3 & ATTR_SW_DBM) != 0) 4300 vm_page_aflag_set(m, PGA_WRITEABLE); 4301 } 4302 4303 validate: 4304 if (pmap->pm_stage == PM_STAGE1) { 4305 /* 4306 * Sync icache if exec permission and attribute 4307 * VM_MEMATTR_WRITE_BACK is set. Do it now, before the mapping 4308 * is stored and made valid for hardware table walk. If done 4309 * later, then other can access this page before caches are 4310 * properly synced. Don't do it for kernel memory which is 4311 * mapped with exec permission even if the memory isn't going 4312 * to hold executable code. The only time when icache sync is 4313 * needed is after kernel module is loaded and the relocation 4314 * info is processed. And it's done in elf_cpu_load_file(). 4315 */ 4316 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap && 4317 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK && 4318 (opa != pa || (orig_l3 & ATTR_S1_XN))) { 4319 PMAP_ASSERT_STAGE1(pmap); 4320 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE); 4321 } 4322 } else { 4323 cpu_dcache_wb_range(PHYS_TO_DMAP(pa), PAGE_SIZE); 4324 } 4325 4326 /* 4327 * Update the L3 entry 4328 */ 4329 if (pmap_l3_valid(orig_l3)) { 4330 PMAP_ASSERT_STAGE1(pmap); 4331 KASSERT(opa == pa, ("pmap_enter: invalid update")); 4332 if ((orig_l3 & ~ATTR_AF) != (new_l3 & ~ATTR_AF)) { 4333 /* same PA, different attributes */ 4334 orig_l3 = pmap_load_store(l3, new_l3); 4335 pmap_invalidate_page(pmap, va, true); 4336 if ((orig_l3 & ATTR_SW_MANAGED) != 0 && 4337 pmap_pte_dirty(pmap, orig_l3)) 4338 vm_page_dirty(m); 4339 } else { 4340 /* 4341 * orig_l3 == new_l3 4342 * This can happens if multiple threads simultaneously 4343 * access not yet mapped page. This bad for performance 4344 * since this can cause full demotion-NOP-promotion 4345 * cycle. 4346 * Another possible reasons are: 4347 * - VM and pmap memory layout are diverged 4348 * - tlb flush is missing somewhere and CPU doesn't see 4349 * actual mapping. 4350 */ 4351 CTR4(KTR_PMAP, "%s: already mapped page - " 4352 "pmap %p va 0x%#lx pte 0x%lx", 4353 __func__, pmap, va, new_l3); 4354 } 4355 } else { 4356 /* New mapping */ 4357 pmap_store(l3, new_l3); 4358 dsb(ishst); 4359 } 4360 4361 #if VM_NRESERVLEVEL > 0 4362 /* 4363 * Try to promote from level 3 pages to a level 2 superpage. This 4364 * currently only works on stage 1 pmaps as pmap_promote_l2 looks at 4365 * stage 1 specific fields and performs a break-before-make sequence 4366 * that is incorrect a stage 2 pmap. 4367 */ 4368 if ((mpte == NULL || mpte->ref_count == NL3PG) && 4369 pmap_ps_enabled(pmap) && pmap->pm_stage == PM_STAGE1 && 4370 (m->flags & PG_FICTITIOUS) == 0 && 4371 vm_reserv_level_iffullpop(m) == 0) { 4372 pmap_promote_l2(pmap, pde, va, mpte, &lock); 4373 } 4374 #endif 4375 4376 rv = KERN_SUCCESS; 4377 out: 4378 if (lock != NULL) 4379 rw_wunlock(lock); 4380 PMAP_UNLOCK(pmap); 4381 return (rv); 4382 } 4383 4384 /* 4385 * Tries to create a read- and/or execute-only 2MB page mapping. Returns 4386 * KERN_SUCCESS if the mapping was created. Otherwise, returns an error 4387 * value. See pmap_enter_l2() for the possible error values when "no sleep", 4388 * "no replace", and "no reclaim" are specified. 4389 */ 4390 static int 4391 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 4392 struct rwlock **lockp) 4393 { 4394 pd_entry_t new_l2; 4395 4396 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4397 PMAP_ASSERT_STAGE1(pmap); 4398 KASSERT(ADDR_IS_CANONICAL(va), 4399 ("%s: Address not in canonical form: %lx", __func__, va)); 4400 4401 new_l2 = (pd_entry_t)(VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | 4402 ATTR_S1_IDX(m->md.pv_memattr) | ATTR_S1_AP(ATTR_S1_AP_RO) | 4403 L2_BLOCK); 4404 if ((m->oflags & VPO_UNMANAGED) == 0) { 4405 new_l2 |= ATTR_SW_MANAGED; 4406 new_l2 &= ~ATTR_AF; 4407 } 4408 if ((prot & VM_PROT_EXECUTE) == 0 || 4409 m->md.pv_memattr == VM_MEMATTR_DEVICE) 4410 new_l2 |= ATTR_S1_XN; 4411 if (!ADDR_IS_KERNEL(va)) 4412 new_l2 |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN; 4413 else 4414 new_l2 |= ATTR_S1_UXN; 4415 if (pmap != kernel_pmap) 4416 new_l2 |= ATTR_S1_nG; 4417 return (pmap_enter_l2(pmap, va, new_l2, PMAP_ENTER_NOSLEEP | 4418 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, m, lockp)); 4419 } 4420 4421 /* 4422 * Returns true if every page table entry in the specified page table is 4423 * zero. 4424 */ 4425 static bool 4426 pmap_every_pte_zero(vm_paddr_t pa) 4427 { 4428 pt_entry_t *pt_end, *pte; 4429 4430 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned")); 4431 pte = (pt_entry_t *)PHYS_TO_DMAP(pa); 4432 for (pt_end = pte + Ln_ENTRIES; pte < pt_end; pte++) { 4433 if (*pte != 0) 4434 return (false); 4435 } 4436 return (true); 4437 } 4438 4439 /* 4440 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if 4441 * the mapping was created, and one of KERN_FAILURE, KERN_NO_SPACE, or 4442 * KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if 4443 * PMAP_ENTER_NOREPLACE was specified and a 4KB page mapping already exists 4444 * within the 2MB virtual address range starting at the specified virtual 4445 * address. Returns KERN_NO_SPACE if PMAP_ENTER_NOREPLACE was specified and a 4446 * 2MB page mapping already exists at the specified virtual address. Returns 4447 * KERN_RESOURCE_SHORTAGE if either (1) PMAP_ENTER_NOSLEEP was specified and a 4448 * page table page allocation failed or (2) PMAP_ENTER_NORECLAIM was specified 4449 * and a PV entry allocation failed. 4450 */ 4451 static int 4452 pmap_enter_l2(pmap_t pmap, vm_offset_t va, pd_entry_t new_l2, u_int flags, 4453 vm_page_t m, struct rwlock **lockp) 4454 { 4455 struct spglist free; 4456 pd_entry_t *l2, old_l2; 4457 vm_page_t l2pg, mt; 4458 4459 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4460 KASSERT(ADDR_IS_CANONICAL(va), 4461 ("%s: Address not in canonical form: %lx", __func__, va)); 4462 4463 if ((l2 = pmap_alloc_l2(pmap, va, &l2pg, (flags & 4464 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) { 4465 CTR2(KTR_PMAP, "pmap_enter_l2: failure for va %#lx in pmap %p", 4466 va, pmap); 4467 return (KERN_RESOURCE_SHORTAGE); 4468 } 4469 4470 /* 4471 * If there are existing mappings, either abort or remove them. 4472 */ 4473 if ((old_l2 = pmap_load(l2)) != 0) { 4474 KASSERT(l2pg == NULL || l2pg->ref_count > 1, 4475 ("pmap_enter_l2: l2pg's ref count is too low")); 4476 if ((flags & PMAP_ENTER_NOREPLACE) != 0) { 4477 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK) { 4478 if (l2pg != NULL) 4479 l2pg->ref_count--; 4480 CTR2(KTR_PMAP, 4481 "pmap_enter_l2: no space for va %#lx" 4482 " in pmap %p", va, pmap); 4483 return (KERN_NO_SPACE); 4484 } else if (!ADDR_IS_KERNEL(va) || 4485 !pmap_every_pte_zero(old_l2 & ~ATTR_MASK)) { 4486 if (l2pg != NULL) 4487 l2pg->ref_count--; 4488 CTR2(KTR_PMAP, 4489 "pmap_enter_l2: failure for va %#lx" 4490 " in pmap %p", va, pmap); 4491 return (KERN_FAILURE); 4492 } 4493 } 4494 SLIST_INIT(&free); 4495 if ((old_l2 & ATTR_DESCR_MASK) == L2_BLOCK) 4496 (void)pmap_remove_l2(pmap, l2, va, 4497 pmap_load(pmap_l1(pmap, va)), &free, lockp); 4498 else 4499 pmap_remove_l3_range(pmap, old_l2, va, va + L2_SIZE, 4500 &free, lockp); 4501 if (!ADDR_IS_KERNEL(va)) { 4502 vm_page_free_pages_toq(&free, true); 4503 KASSERT(pmap_load(l2) == 0, 4504 ("pmap_enter_l2: non-zero L2 entry %p", l2)); 4505 } else { 4506 KASSERT(SLIST_EMPTY(&free), 4507 ("pmap_enter_l2: freed kernel page table page")); 4508 4509 /* 4510 * Both pmap_remove_l2() and pmap_remove_l3_range() 4511 * will leave the kernel page table page zero filled. 4512 * Nonetheless, the TLB could have an intermediate 4513 * entry for the kernel page table page, so request 4514 * an invalidation at all levels after clearing 4515 * the L2_TABLE entry. 4516 */ 4517 mt = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK); 4518 if (pmap_insert_pt_page(pmap, mt, false)) 4519 panic("pmap_enter_l2: trie insert failed"); 4520 pmap_clear(l2); 4521 pmap_invalidate_page(pmap, va, false); 4522 } 4523 } 4524 4525 if ((new_l2 & ATTR_SW_MANAGED) != 0) { 4526 /* 4527 * Abort this mapping if its PV entry could not be created. 4528 */ 4529 if (!pmap_pv_insert_l2(pmap, va, new_l2, flags, lockp)) { 4530 if (l2pg != NULL) 4531 pmap_abort_ptp(pmap, va, l2pg); 4532 CTR2(KTR_PMAP, 4533 "pmap_enter_l2: failure for va %#lx in pmap %p", 4534 va, pmap); 4535 return (KERN_RESOURCE_SHORTAGE); 4536 } 4537 if ((new_l2 & ATTR_SW_DBM) != 0) 4538 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 4539 vm_page_aflag_set(mt, PGA_WRITEABLE); 4540 } 4541 4542 /* 4543 * Increment counters. 4544 */ 4545 if ((new_l2 & ATTR_SW_WIRED) != 0) 4546 pmap->pm_stats.wired_count += L2_SIZE / PAGE_SIZE; 4547 pmap->pm_stats.resident_count += L2_SIZE / PAGE_SIZE; 4548 4549 /* 4550 * Conditionally sync the icache. See pmap_enter() for details. 4551 */ 4552 if ((new_l2 & ATTR_S1_XN) == 0 && ((new_l2 & ~ATTR_MASK) != 4553 (old_l2 & ~ATTR_MASK) || (old_l2 & ATTR_S1_XN) != 0) && 4554 pmap != kernel_pmap && m->md.pv_memattr == VM_MEMATTR_WRITE_BACK) { 4555 cpu_icache_sync_range(PHYS_TO_DMAP(new_l2 & ~ATTR_MASK), 4556 L2_SIZE); 4557 } 4558 4559 /* 4560 * Map the superpage. 4561 */ 4562 pmap_store(l2, new_l2); 4563 dsb(ishst); 4564 4565 atomic_add_long(&pmap_l2_mappings, 1); 4566 CTR2(KTR_PMAP, "pmap_enter_l2: success for va %#lx in pmap %p", 4567 va, pmap); 4568 4569 return (KERN_SUCCESS); 4570 } 4571 4572 /* 4573 * Maps a sequence of resident pages belonging to the same object. 4574 * The sequence begins with the given page m_start. This page is 4575 * mapped at the given virtual address start. Each subsequent page is 4576 * mapped at a virtual address that is offset from start by the same 4577 * amount as the page is offset from m_start within the object. The 4578 * last page in the sequence is the page with the largest offset from 4579 * m_start that can be mapped at a virtual address less than the given 4580 * virtual address end. Not every virtual page between start and end 4581 * is mapped; only those for which a resident page exists with the 4582 * corresponding offset from m_start are mapped. 4583 */ 4584 void 4585 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 4586 vm_page_t m_start, vm_prot_t prot) 4587 { 4588 struct rwlock *lock; 4589 vm_offset_t va; 4590 vm_page_t m, mpte; 4591 vm_pindex_t diff, psize; 4592 int rv; 4593 4594 VM_OBJECT_ASSERT_LOCKED(m_start->object); 4595 4596 psize = atop(end - start); 4597 mpte = NULL; 4598 m = m_start; 4599 lock = NULL; 4600 PMAP_LOCK(pmap); 4601 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 4602 va = start + ptoa(diff); 4603 if ((va & L2_OFFSET) == 0 && va + L2_SIZE <= end && 4604 m->psind == 1 && pmap_ps_enabled(pmap) && 4605 ((rv = pmap_enter_2mpage(pmap, va, m, prot, &lock)) == 4606 KERN_SUCCESS || rv == KERN_NO_SPACE)) 4607 m = &m[L2_SIZE / PAGE_SIZE - 1]; 4608 else 4609 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, 4610 &lock); 4611 m = TAILQ_NEXT(m, listq); 4612 } 4613 if (lock != NULL) 4614 rw_wunlock(lock); 4615 PMAP_UNLOCK(pmap); 4616 } 4617 4618 /* 4619 * this code makes some *MAJOR* assumptions: 4620 * 1. Current pmap & pmap exists. 4621 * 2. Not wired. 4622 * 3. Read access. 4623 * 4. No page table pages. 4624 * but is *MUCH* faster than pmap_enter... 4625 */ 4626 4627 void 4628 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 4629 { 4630 struct rwlock *lock; 4631 4632 lock = NULL; 4633 PMAP_LOCK(pmap); 4634 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock); 4635 if (lock != NULL) 4636 rw_wunlock(lock); 4637 PMAP_UNLOCK(pmap); 4638 } 4639 4640 static vm_page_t 4641 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 4642 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp) 4643 { 4644 pd_entry_t *pde; 4645 pt_entry_t *l1, *l2, *l3, l3_val; 4646 vm_paddr_t pa; 4647 int lvl; 4648 4649 KASSERT(!VA_IS_CLEANMAP(va) || 4650 (m->oflags & VPO_UNMANAGED) != 0, 4651 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 4652 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4653 PMAP_ASSERT_STAGE1(pmap); 4654 KASSERT(ADDR_IS_CANONICAL(va), 4655 ("%s: Address not in canonical form: %lx", __func__, va)); 4656 4657 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va); 4658 /* 4659 * In the case that a page table page is not 4660 * resident, we are creating it here. 4661 */ 4662 if (!ADDR_IS_KERNEL(va)) { 4663 vm_pindex_t l2pindex; 4664 4665 /* 4666 * Calculate pagetable page index 4667 */ 4668 l2pindex = pmap_l2_pindex(va); 4669 if (mpte && (mpte->pindex == l2pindex)) { 4670 mpte->ref_count++; 4671 } else { 4672 /* 4673 * If the page table page is mapped, we just increment 4674 * the hold count, and activate it. Otherwise, we 4675 * attempt to allocate a page table page, passing NULL 4676 * instead of the PV list lock pointer because we don't 4677 * intend to sleep. If this attempt fails, we don't 4678 * retry. Instead, we give up. 4679 */ 4680 l1 = pmap_l1(pmap, va); 4681 if (l1 != NULL && pmap_load(l1) != 0) { 4682 if ((pmap_load(l1) & ATTR_DESCR_MASK) == 4683 L1_BLOCK) 4684 return (NULL); 4685 l2 = pmap_l1_to_l2(l1, va); 4686 if (pmap_load(l2) != 0) { 4687 if ((pmap_load(l2) & ATTR_DESCR_MASK) == 4688 L2_BLOCK) 4689 return (NULL); 4690 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & 4691 ~ATTR_MASK); 4692 mpte->ref_count++; 4693 } else { 4694 mpte = _pmap_alloc_l3(pmap, l2pindex, 4695 NULL); 4696 if (mpte == NULL) 4697 return (mpte); 4698 } 4699 } else { 4700 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL); 4701 if (mpte == NULL) 4702 return (mpte); 4703 } 4704 } 4705 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte)); 4706 l3 = &l3[pmap_l3_index(va)]; 4707 } else { 4708 mpte = NULL; 4709 pde = pmap_pde(kernel_pmap, va, &lvl); 4710 KASSERT(pde != NULL, 4711 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx", 4712 va)); 4713 KASSERT(lvl == 2, 4714 ("pmap_enter_quick_locked: Invalid level %d", lvl)); 4715 l3 = pmap_l2_to_l3(pde, va); 4716 } 4717 4718 /* 4719 * Abort if a mapping already exists. 4720 */ 4721 if (pmap_load(l3) != 0) { 4722 if (mpte != NULL) 4723 mpte->ref_count--; 4724 return (NULL); 4725 } 4726 4727 /* 4728 * Enter on the PV list if part of our managed memory. 4729 */ 4730 if ((m->oflags & VPO_UNMANAGED) == 0 && 4731 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) { 4732 if (mpte != NULL) 4733 pmap_abort_ptp(pmap, va, mpte); 4734 return (NULL); 4735 } 4736 4737 /* 4738 * Increment counters 4739 */ 4740 pmap_resident_count_inc(pmap, 1); 4741 4742 pa = VM_PAGE_TO_PHYS(m); 4743 l3_val = pa | ATTR_DEFAULT | ATTR_S1_IDX(m->md.pv_memattr) | 4744 ATTR_S1_AP(ATTR_S1_AP_RO) | L3_PAGE; 4745 if ((prot & VM_PROT_EXECUTE) == 0 || 4746 m->md.pv_memattr == VM_MEMATTR_DEVICE) 4747 l3_val |= ATTR_S1_XN; 4748 if (!ADDR_IS_KERNEL(va)) 4749 l3_val |= ATTR_S1_AP(ATTR_S1_AP_USER) | ATTR_S1_PXN; 4750 else 4751 l3_val |= ATTR_S1_UXN; 4752 if (pmap != kernel_pmap) 4753 l3_val |= ATTR_S1_nG; 4754 4755 /* 4756 * Now validate mapping with RO protection 4757 */ 4758 if ((m->oflags & VPO_UNMANAGED) == 0) { 4759 l3_val |= ATTR_SW_MANAGED; 4760 l3_val &= ~ATTR_AF; 4761 } 4762 4763 /* Sync icache before the mapping is stored to PTE */ 4764 if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap && 4765 m->md.pv_memattr == VM_MEMATTR_WRITE_BACK) 4766 cpu_icache_sync_range(PHYS_TO_DMAP(pa), PAGE_SIZE); 4767 4768 pmap_store(l3, l3_val); 4769 dsb(ishst); 4770 4771 return (mpte); 4772 } 4773 4774 /* 4775 * This code maps large physical mmap regions into the 4776 * processor address space. Note that some shortcuts 4777 * are taken, but the code works. 4778 */ 4779 void 4780 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 4781 vm_pindex_t pindex, vm_size_t size) 4782 { 4783 4784 VM_OBJECT_ASSERT_WLOCKED(object); 4785 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 4786 ("pmap_object_init_pt: non-device object")); 4787 } 4788 4789 /* 4790 * Clear the wired attribute from the mappings for the specified range of 4791 * addresses in the given pmap. Every valid mapping within that range 4792 * must have the wired attribute set. In contrast, invalid mappings 4793 * cannot have the wired attribute set, so they are ignored. 4794 * 4795 * The wired attribute of the page table entry is not a hardware feature, 4796 * so there is no need to invalidate any TLB entries. 4797 */ 4798 void 4799 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 4800 { 4801 vm_offset_t va_next; 4802 pd_entry_t *l0, *l1, *l2; 4803 pt_entry_t *l3; 4804 4805 PMAP_LOCK(pmap); 4806 for (; sva < eva; sva = va_next) { 4807 l0 = pmap_l0(pmap, sva); 4808 if (pmap_load(l0) == 0) { 4809 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 4810 if (va_next < sva) 4811 va_next = eva; 4812 continue; 4813 } 4814 4815 l1 = pmap_l0_to_l1(l0, sva); 4816 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 4817 if (va_next < sva) 4818 va_next = eva; 4819 if (pmap_load(l1) == 0) 4820 continue; 4821 4822 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) { 4823 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 4824 KASSERT(va_next <= eva, 4825 ("partial update of non-transparent 1G page " 4826 "l1 %#lx sva %#lx eva %#lx va_next %#lx", 4827 pmap_load(l1), sva, eva, va_next)); 4828 MPASS(pmap != kernel_pmap); 4829 MPASS((pmap_load(l1) & (ATTR_SW_MANAGED | 4830 ATTR_SW_WIRED)) == ATTR_SW_WIRED); 4831 pmap_clear_bits(l1, ATTR_SW_WIRED); 4832 pmap->pm_stats.wired_count -= L1_SIZE / PAGE_SIZE; 4833 continue; 4834 } 4835 4836 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 4837 if (va_next < sva) 4838 va_next = eva; 4839 4840 l2 = pmap_l1_to_l2(l1, sva); 4841 if (pmap_load(l2) == 0) 4842 continue; 4843 4844 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) { 4845 if ((pmap_load(l2) & ATTR_SW_WIRED) == 0) 4846 panic("pmap_unwire: l2 %#jx is missing " 4847 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l2)); 4848 4849 /* 4850 * Are we unwiring the entire large page? If not, 4851 * demote the mapping and fall through. 4852 */ 4853 if (sva + L2_SIZE == va_next && eva >= va_next) { 4854 pmap_clear_bits(l2, ATTR_SW_WIRED); 4855 pmap->pm_stats.wired_count -= L2_SIZE / 4856 PAGE_SIZE; 4857 continue; 4858 } else if (pmap_demote_l2(pmap, l2, sva) == NULL) 4859 panic("pmap_unwire: demotion failed"); 4860 } 4861 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE, 4862 ("pmap_unwire: Invalid l2 entry after demotion")); 4863 4864 if (va_next > eva) 4865 va_next = eva; 4866 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++, 4867 sva += L3_SIZE) { 4868 if (pmap_load(l3) == 0) 4869 continue; 4870 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0) 4871 panic("pmap_unwire: l3 %#jx is missing " 4872 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3)); 4873 4874 /* 4875 * ATTR_SW_WIRED must be cleared atomically. Although 4876 * the pmap lock synchronizes access to ATTR_SW_WIRED, 4877 * the System MMU may write to the entry concurrently. 4878 */ 4879 pmap_clear_bits(l3, ATTR_SW_WIRED); 4880 pmap->pm_stats.wired_count--; 4881 } 4882 } 4883 PMAP_UNLOCK(pmap); 4884 } 4885 4886 /* 4887 * Copy the range specified by src_addr/len 4888 * from the source map to the range dst_addr/len 4889 * in the destination map. 4890 * 4891 * This routine is only advisory and need not do anything. 4892 * 4893 * Because the executable mappings created by this routine are copied, 4894 * it should not have to flush the instruction cache. 4895 */ 4896 void 4897 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 4898 vm_offset_t src_addr) 4899 { 4900 struct rwlock *lock; 4901 pd_entry_t *l0, *l1, *l2, srcptepaddr; 4902 pt_entry_t *dst_pte, mask, nbits, ptetemp, *src_pte; 4903 vm_offset_t addr, end_addr, va_next; 4904 vm_page_t dst_m, dstmpte, srcmpte; 4905 4906 PMAP_ASSERT_STAGE1(dst_pmap); 4907 PMAP_ASSERT_STAGE1(src_pmap); 4908 4909 if (dst_addr != src_addr) 4910 return; 4911 end_addr = src_addr + len; 4912 lock = NULL; 4913 if (dst_pmap < src_pmap) { 4914 PMAP_LOCK(dst_pmap); 4915 PMAP_LOCK(src_pmap); 4916 } else { 4917 PMAP_LOCK(src_pmap); 4918 PMAP_LOCK(dst_pmap); 4919 } 4920 for (addr = src_addr; addr < end_addr; addr = va_next) { 4921 l0 = pmap_l0(src_pmap, addr); 4922 if (pmap_load(l0) == 0) { 4923 va_next = (addr + L0_SIZE) & ~L0_OFFSET; 4924 if (va_next < addr) 4925 va_next = end_addr; 4926 continue; 4927 } 4928 4929 va_next = (addr + L1_SIZE) & ~L1_OFFSET; 4930 if (va_next < addr) 4931 va_next = end_addr; 4932 l1 = pmap_l0_to_l1(l0, addr); 4933 if (pmap_load(l1) == 0) 4934 continue; 4935 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) { 4936 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 4937 KASSERT(va_next <= end_addr, 4938 ("partial update of non-transparent 1G page " 4939 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx", 4940 pmap_load(l1), addr, end_addr, va_next)); 4941 srcptepaddr = pmap_load(l1); 4942 l1 = pmap_l1(dst_pmap, addr); 4943 if (l1 == NULL) { 4944 if (_pmap_alloc_l3(dst_pmap, 4945 pmap_l0_pindex(addr), NULL) == NULL) 4946 break; 4947 l1 = pmap_l1(dst_pmap, addr); 4948 } else { 4949 l0 = pmap_l0(dst_pmap, addr); 4950 dst_m = PHYS_TO_VM_PAGE(pmap_load(l0) & 4951 ~ATTR_MASK); 4952 dst_m->ref_count++; 4953 } 4954 KASSERT(pmap_load(l1) == 0, 4955 ("1G mapping present in dst pmap " 4956 "l1 %#lx addr %#lx end_addr %#lx va_next %#lx", 4957 pmap_load(l1), addr, end_addr, va_next)); 4958 pmap_store(l1, srcptepaddr & ~ATTR_SW_WIRED); 4959 pmap_resident_count_inc(dst_pmap, L1_SIZE / PAGE_SIZE); 4960 continue; 4961 } 4962 4963 va_next = (addr + L2_SIZE) & ~L2_OFFSET; 4964 if (va_next < addr) 4965 va_next = end_addr; 4966 l2 = pmap_l1_to_l2(l1, addr); 4967 srcptepaddr = pmap_load(l2); 4968 if (srcptepaddr == 0) 4969 continue; 4970 if ((srcptepaddr & ATTR_DESCR_MASK) == L2_BLOCK) { 4971 /* 4972 * We can only virtual copy whole superpages. 4973 */ 4974 if ((addr & L2_OFFSET) != 0 || 4975 addr + L2_SIZE > end_addr) 4976 continue; 4977 l2 = pmap_alloc_l2(dst_pmap, addr, &dst_m, NULL); 4978 if (l2 == NULL) 4979 break; 4980 if (pmap_load(l2) == 0 && 4981 ((srcptepaddr & ATTR_SW_MANAGED) == 0 || 4982 pmap_pv_insert_l2(dst_pmap, addr, srcptepaddr, 4983 PMAP_ENTER_NORECLAIM, &lock))) { 4984 /* 4985 * We leave the dirty bit unchanged because 4986 * managed read/write superpage mappings are 4987 * required to be dirty. However, managed 4988 * superpage mappings are not required to 4989 * have their accessed bit set, so we clear 4990 * it because we don't know if this mapping 4991 * will be used. 4992 */ 4993 srcptepaddr &= ~ATTR_SW_WIRED; 4994 if ((srcptepaddr & ATTR_SW_MANAGED) != 0) 4995 srcptepaddr &= ~ATTR_AF; 4996 pmap_store(l2, srcptepaddr); 4997 pmap_resident_count_inc(dst_pmap, L2_SIZE / 4998 PAGE_SIZE); 4999 atomic_add_long(&pmap_l2_mappings, 1); 5000 } else 5001 pmap_abort_ptp(dst_pmap, addr, dst_m); 5002 continue; 5003 } 5004 KASSERT((srcptepaddr & ATTR_DESCR_MASK) == L2_TABLE, 5005 ("pmap_copy: invalid L2 entry")); 5006 srcptepaddr &= ~ATTR_MASK; 5007 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr); 5008 KASSERT(srcmpte->ref_count > 0, 5009 ("pmap_copy: source page table page is unused")); 5010 if (va_next > end_addr) 5011 va_next = end_addr; 5012 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr); 5013 src_pte = &src_pte[pmap_l3_index(addr)]; 5014 dstmpte = NULL; 5015 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) { 5016 ptetemp = pmap_load(src_pte); 5017 5018 /* 5019 * We only virtual copy managed pages. 5020 */ 5021 if ((ptetemp & ATTR_SW_MANAGED) == 0) 5022 continue; 5023 5024 if (dstmpte != NULL) { 5025 KASSERT(dstmpte->pindex == pmap_l2_pindex(addr), 5026 ("dstmpte pindex/addr mismatch")); 5027 dstmpte->ref_count++; 5028 } else if ((dstmpte = pmap_alloc_l3(dst_pmap, addr, 5029 NULL)) == NULL) 5030 goto out; 5031 dst_pte = (pt_entry_t *) 5032 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte)); 5033 dst_pte = &dst_pte[pmap_l3_index(addr)]; 5034 if (pmap_load(dst_pte) == 0 && 5035 pmap_try_insert_pv_entry(dst_pmap, addr, 5036 PHYS_TO_VM_PAGE(ptetemp & ~ATTR_MASK), &lock)) { 5037 /* 5038 * Clear the wired, modified, and accessed 5039 * (referenced) bits during the copy. 5040 */ 5041 mask = ATTR_AF | ATTR_SW_WIRED; 5042 nbits = 0; 5043 if ((ptetemp & ATTR_SW_DBM) != 0) 5044 nbits |= ATTR_S1_AP_RW_BIT; 5045 pmap_store(dst_pte, (ptetemp & ~mask) | nbits); 5046 pmap_resident_count_inc(dst_pmap, 1); 5047 } else { 5048 pmap_abort_ptp(dst_pmap, addr, dstmpte); 5049 goto out; 5050 } 5051 /* Have we copied all of the valid mappings? */ 5052 if (dstmpte->ref_count >= srcmpte->ref_count) 5053 break; 5054 } 5055 } 5056 out: 5057 /* 5058 * XXX This barrier may not be needed because the destination pmap is 5059 * not active. 5060 */ 5061 dsb(ishst); 5062 5063 if (lock != NULL) 5064 rw_wunlock(lock); 5065 PMAP_UNLOCK(src_pmap); 5066 PMAP_UNLOCK(dst_pmap); 5067 } 5068 5069 /* 5070 * pmap_zero_page zeros the specified hardware page by mapping 5071 * the page into KVM and using bzero to clear its contents. 5072 */ 5073 void 5074 pmap_zero_page(vm_page_t m) 5075 { 5076 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 5077 5078 pagezero((void *)va); 5079 } 5080 5081 /* 5082 * pmap_zero_page_area zeros the specified hardware page by mapping 5083 * the page into KVM and using bzero to clear its contents. 5084 * 5085 * off and size may not cover an area beyond a single hardware page. 5086 */ 5087 void 5088 pmap_zero_page_area(vm_page_t m, int off, int size) 5089 { 5090 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 5091 5092 if (off == 0 && size == PAGE_SIZE) 5093 pagezero((void *)va); 5094 else 5095 bzero((char *)va + off, size); 5096 } 5097 5098 /* 5099 * pmap_copy_page copies the specified (machine independent) 5100 * page by mapping the page into virtual memory and using 5101 * bcopy to copy the page, one machine dependent page at a 5102 * time. 5103 */ 5104 void 5105 pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 5106 { 5107 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc)); 5108 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst)); 5109 5110 pagecopy((void *)src, (void *)dst); 5111 } 5112 5113 int unmapped_buf_allowed = 1; 5114 5115 void 5116 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 5117 vm_offset_t b_offset, int xfersize) 5118 { 5119 void *a_cp, *b_cp; 5120 vm_page_t m_a, m_b; 5121 vm_paddr_t p_a, p_b; 5122 vm_offset_t a_pg_offset, b_pg_offset; 5123 int cnt; 5124 5125 while (xfersize > 0) { 5126 a_pg_offset = a_offset & PAGE_MASK; 5127 m_a = ma[a_offset >> PAGE_SHIFT]; 5128 p_a = m_a->phys_addr; 5129 b_pg_offset = b_offset & PAGE_MASK; 5130 m_b = mb[b_offset >> PAGE_SHIFT]; 5131 p_b = m_b->phys_addr; 5132 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 5133 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 5134 if (__predict_false(!PHYS_IN_DMAP(p_a))) { 5135 panic("!DMAP a %lx", p_a); 5136 } else { 5137 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset; 5138 } 5139 if (__predict_false(!PHYS_IN_DMAP(p_b))) { 5140 panic("!DMAP b %lx", p_b); 5141 } else { 5142 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset; 5143 } 5144 bcopy(a_cp, b_cp, cnt); 5145 a_offset += cnt; 5146 b_offset += cnt; 5147 xfersize -= cnt; 5148 } 5149 } 5150 5151 vm_offset_t 5152 pmap_quick_enter_page(vm_page_t m) 5153 { 5154 5155 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m))); 5156 } 5157 5158 void 5159 pmap_quick_remove_page(vm_offset_t addr) 5160 { 5161 } 5162 5163 /* 5164 * Returns true if the pmap's pv is one of the first 5165 * 16 pvs linked to from this page. This count may 5166 * be changed upwards or downwards in the future; it 5167 * is only necessary that true be returned for a small 5168 * subset of pmaps for proper page aging. 5169 */ 5170 boolean_t 5171 pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 5172 { 5173 struct md_page *pvh; 5174 struct rwlock *lock; 5175 pv_entry_t pv; 5176 int loops = 0; 5177 boolean_t rv; 5178 5179 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5180 ("pmap_page_exists_quick: page %p is not managed", m)); 5181 rv = FALSE; 5182 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5183 rw_rlock(lock); 5184 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5185 if (PV_PMAP(pv) == pmap) { 5186 rv = TRUE; 5187 break; 5188 } 5189 loops++; 5190 if (loops >= 16) 5191 break; 5192 } 5193 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 5194 pvh = page_to_pvh(m); 5195 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 5196 if (PV_PMAP(pv) == pmap) { 5197 rv = TRUE; 5198 break; 5199 } 5200 loops++; 5201 if (loops >= 16) 5202 break; 5203 } 5204 } 5205 rw_runlock(lock); 5206 return (rv); 5207 } 5208 5209 /* 5210 * pmap_page_wired_mappings: 5211 * 5212 * Return the number of managed mappings to the given physical page 5213 * that are wired. 5214 */ 5215 int 5216 pmap_page_wired_mappings(vm_page_t m) 5217 { 5218 struct rwlock *lock; 5219 struct md_page *pvh; 5220 pmap_t pmap; 5221 pt_entry_t *pte; 5222 pv_entry_t pv; 5223 int count, md_gen, pvh_gen; 5224 5225 if ((m->oflags & VPO_UNMANAGED) != 0) 5226 return (0); 5227 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5228 rw_rlock(lock); 5229 restart: 5230 count = 0; 5231 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5232 pmap = PV_PMAP(pv); 5233 if (!PMAP_TRYLOCK(pmap)) { 5234 md_gen = m->md.pv_gen; 5235 rw_runlock(lock); 5236 PMAP_LOCK(pmap); 5237 rw_rlock(lock); 5238 if (md_gen != m->md.pv_gen) { 5239 PMAP_UNLOCK(pmap); 5240 goto restart; 5241 } 5242 } 5243 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__); 5244 if ((pmap_load(pte) & ATTR_SW_WIRED) != 0) 5245 count++; 5246 PMAP_UNLOCK(pmap); 5247 } 5248 if ((m->flags & PG_FICTITIOUS) == 0) { 5249 pvh = page_to_pvh(m); 5250 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 5251 pmap = PV_PMAP(pv); 5252 if (!PMAP_TRYLOCK(pmap)) { 5253 md_gen = m->md.pv_gen; 5254 pvh_gen = pvh->pv_gen; 5255 rw_runlock(lock); 5256 PMAP_LOCK(pmap); 5257 rw_rlock(lock); 5258 if (md_gen != m->md.pv_gen || 5259 pvh_gen != pvh->pv_gen) { 5260 PMAP_UNLOCK(pmap); 5261 goto restart; 5262 } 5263 } 5264 pte = pmap_pte_exists(pmap, pv->pv_va, 2, __func__); 5265 if ((pmap_load(pte) & ATTR_SW_WIRED) != 0) 5266 count++; 5267 PMAP_UNLOCK(pmap); 5268 } 5269 } 5270 rw_runlock(lock); 5271 return (count); 5272 } 5273 5274 /* 5275 * Returns true if the given page is mapped individually or as part of 5276 * a 2mpage. Otherwise, returns false. 5277 */ 5278 bool 5279 pmap_page_is_mapped(vm_page_t m) 5280 { 5281 struct rwlock *lock; 5282 bool rv; 5283 5284 if ((m->oflags & VPO_UNMANAGED) != 0) 5285 return (false); 5286 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5287 rw_rlock(lock); 5288 rv = !TAILQ_EMPTY(&m->md.pv_list) || 5289 ((m->flags & PG_FICTITIOUS) == 0 && 5290 !TAILQ_EMPTY(&page_to_pvh(m)->pv_list)); 5291 rw_runlock(lock); 5292 return (rv); 5293 } 5294 5295 /* 5296 * Destroy all managed, non-wired mappings in the given user-space 5297 * pmap. This pmap cannot be active on any processor besides the 5298 * caller. 5299 * 5300 * This function cannot be applied to the kernel pmap. Moreover, it 5301 * is not intended for general use. It is only to be used during 5302 * process termination. Consequently, it can be implemented in ways 5303 * that make it faster than pmap_remove(). First, it can more quickly 5304 * destroy mappings by iterating over the pmap's collection of PV 5305 * entries, rather than searching the page table. Second, it doesn't 5306 * have to test and clear the page table entries atomically, because 5307 * no processor is currently accessing the user address space. In 5308 * particular, a page table entry's dirty bit won't change state once 5309 * this function starts. 5310 */ 5311 void 5312 pmap_remove_pages(pmap_t pmap) 5313 { 5314 pd_entry_t *pde; 5315 pt_entry_t *pte, tpte; 5316 struct spglist free; 5317 struct pv_chunklist free_chunks[PMAP_MEMDOM]; 5318 vm_page_t m, ml3, mt; 5319 pv_entry_t pv; 5320 struct md_page *pvh; 5321 struct pv_chunk *pc, *npc; 5322 struct rwlock *lock; 5323 int64_t bit; 5324 uint64_t inuse, bitmask; 5325 int allfree, field, freed, i, idx, lvl; 5326 vm_paddr_t pa; 5327 5328 lock = NULL; 5329 5330 for (i = 0; i < PMAP_MEMDOM; i++) 5331 TAILQ_INIT(&free_chunks[i]); 5332 SLIST_INIT(&free); 5333 PMAP_LOCK(pmap); 5334 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 5335 allfree = 1; 5336 freed = 0; 5337 for (field = 0; field < _NPCM; field++) { 5338 inuse = ~pc->pc_map[field] & pc_freemask[field]; 5339 while (inuse != 0) { 5340 bit = ffsl(inuse) - 1; 5341 bitmask = 1UL << bit; 5342 idx = field * 64 + bit; 5343 pv = &pc->pc_pventry[idx]; 5344 inuse &= ~bitmask; 5345 5346 pde = pmap_pde(pmap, pv->pv_va, &lvl); 5347 KASSERT(pde != NULL, 5348 ("Attempting to remove an unmapped page")); 5349 5350 switch(lvl) { 5351 case 1: 5352 pte = pmap_l1_to_l2(pde, pv->pv_va); 5353 tpte = pmap_load(pte); 5354 KASSERT((tpte & ATTR_DESCR_MASK) == 5355 L2_BLOCK, 5356 ("Attempting to remove an invalid " 5357 "block: %lx", tpte)); 5358 break; 5359 case 2: 5360 pte = pmap_l2_to_l3(pde, pv->pv_va); 5361 tpte = pmap_load(pte); 5362 KASSERT((tpte & ATTR_DESCR_MASK) == 5363 L3_PAGE, 5364 ("Attempting to remove an invalid " 5365 "page: %lx", tpte)); 5366 break; 5367 default: 5368 panic( 5369 "Invalid page directory level: %d", 5370 lvl); 5371 } 5372 5373 /* 5374 * We cannot remove wired pages from a process' mapping at this time 5375 */ 5376 if (tpte & ATTR_SW_WIRED) { 5377 allfree = 0; 5378 continue; 5379 } 5380 5381 /* Mark free */ 5382 pc->pc_map[field] |= bitmask; 5383 5384 /* 5385 * Because this pmap is not active on other 5386 * processors, the dirty bit cannot have 5387 * changed state since we last loaded pte. 5388 */ 5389 pmap_clear(pte); 5390 5391 pa = tpte & ~ATTR_MASK; 5392 5393 m = PHYS_TO_VM_PAGE(pa); 5394 KASSERT(m->phys_addr == pa, 5395 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 5396 m, (uintmax_t)m->phys_addr, 5397 (uintmax_t)tpte)); 5398 5399 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 5400 m < &vm_page_array[vm_page_array_size], 5401 ("pmap_remove_pages: bad pte %#jx", 5402 (uintmax_t)tpte)); 5403 5404 /* 5405 * Update the vm_page_t clean/reference bits. 5406 */ 5407 if (pmap_pte_dirty(pmap, tpte)) { 5408 switch (lvl) { 5409 case 1: 5410 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 5411 vm_page_dirty(mt); 5412 break; 5413 case 2: 5414 vm_page_dirty(m); 5415 break; 5416 } 5417 } 5418 5419 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m); 5420 5421 switch (lvl) { 5422 case 1: 5423 pmap_resident_count_dec(pmap, 5424 L2_SIZE / PAGE_SIZE); 5425 pvh = page_to_pvh(m); 5426 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next); 5427 pvh->pv_gen++; 5428 if (TAILQ_EMPTY(&pvh->pv_list)) { 5429 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 5430 if ((mt->a.flags & PGA_WRITEABLE) != 0 && 5431 TAILQ_EMPTY(&mt->md.pv_list)) 5432 vm_page_aflag_clear(mt, PGA_WRITEABLE); 5433 } 5434 ml3 = pmap_remove_pt_page(pmap, 5435 pv->pv_va); 5436 if (ml3 != NULL) { 5437 KASSERT(ml3->valid == VM_PAGE_BITS_ALL, 5438 ("pmap_remove_pages: l3 page not promoted")); 5439 pmap_resident_count_dec(pmap,1); 5440 KASSERT(ml3->ref_count == NL3PG, 5441 ("pmap_remove_pages: l3 page ref count error")); 5442 ml3->ref_count = 0; 5443 pmap_add_delayed_free_list(ml3, 5444 &free, FALSE); 5445 } 5446 break; 5447 case 2: 5448 pmap_resident_count_dec(pmap, 1); 5449 TAILQ_REMOVE(&m->md.pv_list, pv, 5450 pv_next); 5451 m->md.pv_gen++; 5452 if ((m->a.flags & PGA_WRITEABLE) != 0 && 5453 TAILQ_EMPTY(&m->md.pv_list) && 5454 (m->flags & PG_FICTITIOUS) == 0) { 5455 pvh = page_to_pvh(m); 5456 if (TAILQ_EMPTY(&pvh->pv_list)) 5457 vm_page_aflag_clear(m, 5458 PGA_WRITEABLE); 5459 } 5460 break; 5461 } 5462 pmap_unuse_pt(pmap, pv->pv_va, pmap_load(pde), 5463 &free); 5464 freed++; 5465 } 5466 } 5467 PV_STAT(atomic_add_long(&pv_entry_frees, freed)); 5468 PV_STAT(atomic_add_int(&pv_entry_spare, freed)); 5469 PV_STAT(atomic_subtract_long(&pv_entry_count, freed)); 5470 if (allfree) { 5471 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 5472 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, 5473 pc_list); 5474 } 5475 } 5476 if (lock != NULL) 5477 rw_wunlock(lock); 5478 pmap_invalidate_all(pmap); 5479 free_pv_chunk_batch(free_chunks); 5480 PMAP_UNLOCK(pmap); 5481 vm_page_free_pages_toq(&free, true); 5482 } 5483 5484 /* 5485 * This is used to check if a page has been accessed or modified. 5486 */ 5487 static boolean_t 5488 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified) 5489 { 5490 struct rwlock *lock; 5491 pv_entry_t pv; 5492 struct md_page *pvh; 5493 pt_entry_t *pte, mask, value; 5494 pmap_t pmap; 5495 int md_gen, pvh_gen; 5496 boolean_t rv; 5497 5498 rv = FALSE; 5499 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5500 rw_rlock(lock); 5501 restart: 5502 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5503 pmap = PV_PMAP(pv); 5504 PMAP_ASSERT_STAGE1(pmap); 5505 if (!PMAP_TRYLOCK(pmap)) { 5506 md_gen = m->md.pv_gen; 5507 rw_runlock(lock); 5508 PMAP_LOCK(pmap); 5509 rw_rlock(lock); 5510 if (md_gen != m->md.pv_gen) { 5511 PMAP_UNLOCK(pmap); 5512 goto restart; 5513 } 5514 } 5515 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__); 5516 mask = 0; 5517 value = 0; 5518 if (modified) { 5519 mask |= ATTR_S1_AP_RW_BIT; 5520 value |= ATTR_S1_AP(ATTR_S1_AP_RW); 5521 } 5522 if (accessed) { 5523 mask |= ATTR_AF | ATTR_DESCR_MASK; 5524 value |= ATTR_AF | L3_PAGE; 5525 } 5526 rv = (pmap_load(pte) & mask) == value; 5527 PMAP_UNLOCK(pmap); 5528 if (rv) 5529 goto out; 5530 } 5531 if ((m->flags & PG_FICTITIOUS) == 0) { 5532 pvh = page_to_pvh(m); 5533 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 5534 pmap = PV_PMAP(pv); 5535 PMAP_ASSERT_STAGE1(pmap); 5536 if (!PMAP_TRYLOCK(pmap)) { 5537 md_gen = m->md.pv_gen; 5538 pvh_gen = pvh->pv_gen; 5539 rw_runlock(lock); 5540 PMAP_LOCK(pmap); 5541 rw_rlock(lock); 5542 if (md_gen != m->md.pv_gen || 5543 pvh_gen != pvh->pv_gen) { 5544 PMAP_UNLOCK(pmap); 5545 goto restart; 5546 } 5547 } 5548 pte = pmap_pte_exists(pmap, pv->pv_va, 2, __func__); 5549 mask = 0; 5550 value = 0; 5551 if (modified) { 5552 mask |= ATTR_S1_AP_RW_BIT; 5553 value |= ATTR_S1_AP(ATTR_S1_AP_RW); 5554 } 5555 if (accessed) { 5556 mask |= ATTR_AF | ATTR_DESCR_MASK; 5557 value |= ATTR_AF | L2_BLOCK; 5558 } 5559 rv = (pmap_load(pte) & mask) == value; 5560 PMAP_UNLOCK(pmap); 5561 if (rv) 5562 goto out; 5563 } 5564 } 5565 out: 5566 rw_runlock(lock); 5567 return (rv); 5568 } 5569 5570 /* 5571 * pmap_is_modified: 5572 * 5573 * Return whether or not the specified physical page was modified 5574 * in any physical maps. 5575 */ 5576 boolean_t 5577 pmap_is_modified(vm_page_t m) 5578 { 5579 5580 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5581 ("pmap_is_modified: page %p is not managed", m)); 5582 5583 /* 5584 * If the page is not busied then this check is racy. 5585 */ 5586 if (!pmap_page_is_write_mapped(m)) 5587 return (FALSE); 5588 return (pmap_page_test_mappings(m, FALSE, TRUE)); 5589 } 5590 5591 /* 5592 * pmap_is_prefaultable: 5593 * 5594 * Return whether or not the specified virtual address is eligible 5595 * for prefault. 5596 */ 5597 boolean_t 5598 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 5599 { 5600 pd_entry_t *pde; 5601 pt_entry_t *pte; 5602 boolean_t rv; 5603 int lvl; 5604 5605 /* 5606 * Return TRUE if and only if the L3 entry for the specified virtual 5607 * address is allocated but invalid. 5608 */ 5609 rv = FALSE; 5610 PMAP_LOCK(pmap); 5611 pde = pmap_pde(pmap, addr, &lvl); 5612 if (pde != NULL && lvl == 2) { 5613 pte = pmap_l2_to_l3(pde, addr); 5614 rv = pmap_load(pte) == 0; 5615 } 5616 PMAP_UNLOCK(pmap); 5617 return (rv); 5618 } 5619 5620 /* 5621 * pmap_is_referenced: 5622 * 5623 * Return whether or not the specified physical page was referenced 5624 * in any physical maps. 5625 */ 5626 boolean_t 5627 pmap_is_referenced(vm_page_t m) 5628 { 5629 5630 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5631 ("pmap_is_referenced: page %p is not managed", m)); 5632 return (pmap_page_test_mappings(m, TRUE, FALSE)); 5633 } 5634 5635 /* 5636 * Clear the write and modified bits in each of the given page's mappings. 5637 */ 5638 void 5639 pmap_remove_write(vm_page_t m) 5640 { 5641 struct md_page *pvh; 5642 pmap_t pmap; 5643 struct rwlock *lock; 5644 pv_entry_t next_pv, pv; 5645 pt_entry_t oldpte, *pte; 5646 vm_offset_t va; 5647 int md_gen, pvh_gen; 5648 5649 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5650 ("pmap_remove_write: page %p is not managed", m)); 5651 vm_page_assert_busied(m); 5652 5653 if (!pmap_page_is_write_mapped(m)) 5654 return; 5655 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 5656 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m); 5657 rw_wlock(lock); 5658 retry: 5659 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 5660 pmap = PV_PMAP(pv); 5661 PMAP_ASSERT_STAGE1(pmap); 5662 if (!PMAP_TRYLOCK(pmap)) { 5663 pvh_gen = pvh->pv_gen; 5664 rw_wunlock(lock); 5665 PMAP_LOCK(pmap); 5666 rw_wlock(lock); 5667 if (pvh_gen != pvh->pv_gen) { 5668 PMAP_UNLOCK(pmap); 5669 goto retry; 5670 } 5671 } 5672 va = pv->pv_va; 5673 pte = pmap_pte_exists(pmap, va, 2, __func__); 5674 if ((pmap_load(pte) & ATTR_SW_DBM) != 0) 5675 (void)pmap_demote_l2_locked(pmap, pte, va, &lock); 5676 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 5677 ("inconsistent pv lock %p %p for page %p", 5678 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 5679 PMAP_UNLOCK(pmap); 5680 } 5681 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5682 pmap = PV_PMAP(pv); 5683 PMAP_ASSERT_STAGE1(pmap); 5684 if (!PMAP_TRYLOCK(pmap)) { 5685 pvh_gen = pvh->pv_gen; 5686 md_gen = m->md.pv_gen; 5687 rw_wunlock(lock); 5688 PMAP_LOCK(pmap); 5689 rw_wlock(lock); 5690 if (pvh_gen != pvh->pv_gen || 5691 md_gen != m->md.pv_gen) { 5692 PMAP_UNLOCK(pmap); 5693 goto retry; 5694 } 5695 } 5696 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__); 5697 oldpte = pmap_load(pte); 5698 if ((oldpte & ATTR_SW_DBM) != 0) { 5699 while (!atomic_fcmpset_64(pte, &oldpte, 5700 (oldpte | ATTR_S1_AP_RW_BIT) & ~ATTR_SW_DBM)) 5701 cpu_spinwait(); 5702 if ((oldpte & ATTR_S1_AP_RW_BIT) == 5703 ATTR_S1_AP(ATTR_S1_AP_RW)) 5704 vm_page_dirty(m); 5705 pmap_invalidate_page(pmap, pv->pv_va, true); 5706 } 5707 PMAP_UNLOCK(pmap); 5708 } 5709 rw_wunlock(lock); 5710 vm_page_aflag_clear(m, PGA_WRITEABLE); 5711 } 5712 5713 /* 5714 * pmap_ts_referenced: 5715 * 5716 * Return a count of reference bits for a page, clearing those bits. 5717 * It is not necessary for every reference bit to be cleared, but it 5718 * is necessary that 0 only be returned when there are truly no 5719 * reference bits set. 5720 * 5721 * As an optimization, update the page's dirty field if a modified bit is 5722 * found while counting reference bits. This opportunistic update can be 5723 * performed at low cost and can eliminate the need for some future calls 5724 * to pmap_is_modified(). However, since this function stops after 5725 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 5726 * dirty pages. Those dirty pages will only be detected by a future call 5727 * to pmap_is_modified(). 5728 */ 5729 int 5730 pmap_ts_referenced(vm_page_t m) 5731 { 5732 struct md_page *pvh; 5733 pv_entry_t pv, pvf; 5734 pmap_t pmap; 5735 struct rwlock *lock; 5736 pt_entry_t *pte, tpte; 5737 vm_offset_t va; 5738 vm_paddr_t pa; 5739 int cleared, md_gen, not_cleared, pvh_gen; 5740 struct spglist free; 5741 5742 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 5743 ("pmap_ts_referenced: page %p is not managed", m)); 5744 SLIST_INIT(&free); 5745 cleared = 0; 5746 pa = VM_PAGE_TO_PHYS(m); 5747 lock = PHYS_TO_PV_LIST_LOCK(pa); 5748 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m); 5749 rw_wlock(lock); 5750 retry: 5751 not_cleared = 0; 5752 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 5753 goto small_mappings; 5754 pv = pvf; 5755 do { 5756 if (pvf == NULL) 5757 pvf = pv; 5758 pmap = PV_PMAP(pv); 5759 if (!PMAP_TRYLOCK(pmap)) { 5760 pvh_gen = pvh->pv_gen; 5761 rw_wunlock(lock); 5762 PMAP_LOCK(pmap); 5763 rw_wlock(lock); 5764 if (pvh_gen != pvh->pv_gen) { 5765 PMAP_UNLOCK(pmap); 5766 goto retry; 5767 } 5768 } 5769 va = pv->pv_va; 5770 pte = pmap_pte_exists(pmap, va, 2, __func__); 5771 tpte = pmap_load(pte); 5772 if (pmap_pte_dirty(pmap, tpte)) { 5773 /* 5774 * Although "tpte" is mapping a 2MB page, because 5775 * this function is called at a 4KB page granularity, 5776 * we only update the 4KB page under test. 5777 */ 5778 vm_page_dirty(m); 5779 } 5780 if ((tpte & ATTR_AF) != 0) { 5781 /* 5782 * Since this reference bit is shared by 512 4KB pages, 5783 * it should not be cleared every time it is tested. 5784 * Apply a simple "hash" function on the physical page 5785 * number, the virtual superpage number, and the pmap 5786 * address to select one 4KB page out of the 512 on 5787 * which testing the reference bit will result in 5788 * clearing that reference bit. This function is 5789 * designed to avoid the selection of the same 4KB page 5790 * for every 2MB page mapping. 5791 * 5792 * On demotion, a mapping that hasn't been referenced 5793 * is simply destroyed. To avoid the possibility of a 5794 * subsequent page fault on a demoted wired mapping, 5795 * always leave its reference bit set. Moreover, 5796 * since the superpage is wired, the current state of 5797 * its reference bit won't affect page replacement. 5798 */ 5799 if ((((pa >> PAGE_SHIFT) ^ (va >> L2_SHIFT) ^ 5800 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 && 5801 (tpte & ATTR_SW_WIRED) == 0) { 5802 pmap_clear_bits(pte, ATTR_AF); 5803 pmap_invalidate_page(pmap, va, true); 5804 cleared++; 5805 } else 5806 not_cleared++; 5807 } 5808 PMAP_UNLOCK(pmap); 5809 /* Rotate the PV list if it has more than one entry. */ 5810 if (TAILQ_NEXT(pv, pv_next) != NULL) { 5811 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 5812 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 5813 pvh->pv_gen++; 5814 } 5815 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX) 5816 goto out; 5817 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 5818 small_mappings: 5819 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 5820 goto out; 5821 pv = pvf; 5822 do { 5823 if (pvf == NULL) 5824 pvf = pv; 5825 pmap = PV_PMAP(pv); 5826 if (!PMAP_TRYLOCK(pmap)) { 5827 pvh_gen = pvh->pv_gen; 5828 md_gen = m->md.pv_gen; 5829 rw_wunlock(lock); 5830 PMAP_LOCK(pmap); 5831 rw_wlock(lock); 5832 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 5833 PMAP_UNLOCK(pmap); 5834 goto retry; 5835 } 5836 } 5837 pte = pmap_pte_exists(pmap, pv->pv_va, 3, __func__); 5838 tpte = pmap_load(pte); 5839 if (pmap_pte_dirty(pmap, tpte)) 5840 vm_page_dirty(m); 5841 if ((tpte & ATTR_AF) != 0) { 5842 if ((tpte & ATTR_SW_WIRED) == 0) { 5843 pmap_clear_bits(pte, ATTR_AF); 5844 pmap_invalidate_page(pmap, pv->pv_va, true); 5845 cleared++; 5846 } else 5847 not_cleared++; 5848 } 5849 PMAP_UNLOCK(pmap); 5850 /* Rotate the PV list if it has more than one entry. */ 5851 if (TAILQ_NEXT(pv, pv_next) != NULL) { 5852 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 5853 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 5854 m->md.pv_gen++; 5855 } 5856 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared + 5857 not_cleared < PMAP_TS_REFERENCED_MAX); 5858 out: 5859 rw_wunlock(lock); 5860 vm_page_free_pages_toq(&free, true); 5861 return (cleared + not_cleared); 5862 } 5863 5864 /* 5865 * Apply the given advice to the specified range of addresses within the 5866 * given pmap. Depending on the advice, clear the referenced and/or 5867 * modified flags in each mapping and set the mapped page's dirty field. 5868 */ 5869 void 5870 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 5871 { 5872 struct rwlock *lock; 5873 vm_offset_t va, va_next; 5874 vm_page_t m; 5875 pd_entry_t *l0, *l1, *l2, oldl2; 5876 pt_entry_t *l3, oldl3; 5877 5878 PMAP_ASSERT_STAGE1(pmap); 5879 5880 if (advice != MADV_DONTNEED && advice != MADV_FREE) 5881 return; 5882 5883 PMAP_LOCK(pmap); 5884 for (; sva < eva; sva = va_next) { 5885 l0 = pmap_l0(pmap, sva); 5886 if (pmap_load(l0) == 0) { 5887 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 5888 if (va_next < sva) 5889 va_next = eva; 5890 continue; 5891 } 5892 5893 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 5894 if (va_next < sva) 5895 va_next = eva; 5896 l1 = pmap_l0_to_l1(l0, sva); 5897 if (pmap_load(l1) == 0) 5898 continue; 5899 if ((pmap_load(l1) & ATTR_DESCR_MASK) == L1_BLOCK) { 5900 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 5901 continue; 5902 } 5903 5904 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 5905 if (va_next < sva) 5906 va_next = eva; 5907 l2 = pmap_l1_to_l2(l1, sva); 5908 oldl2 = pmap_load(l2); 5909 if (oldl2 == 0) 5910 continue; 5911 if ((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK) { 5912 if ((oldl2 & ATTR_SW_MANAGED) == 0) 5913 continue; 5914 lock = NULL; 5915 if (!pmap_demote_l2_locked(pmap, l2, sva, &lock)) { 5916 if (lock != NULL) 5917 rw_wunlock(lock); 5918 5919 /* 5920 * The 2MB page mapping was destroyed. 5921 */ 5922 continue; 5923 } 5924 5925 /* 5926 * Unless the page mappings are wired, remove the 5927 * mapping to a single page so that a subsequent 5928 * access may repromote. Choosing the last page 5929 * within the address range [sva, min(va_next, eva)) 5930 * generally results in more repromotions. Since the 5931 * underlying page table page is fully populated, this 5932 * removal never frees a page table page. 5933 */ 5934 if ((oldl2 & ATTR_SW_WIRED) == 0) { 5935 va = eva; 5936 if (va > va_next) 5937 va = va_next; 5938 va -= PAGE_SIZE; 5939 KASSERT(va >= sva, 5940 ("pmap_advise: no address gap")); 5941 l3 = pmap_l2_to_l3(l2, va); 5942 KASSERT(pmap_load(l3) != 0, 5943 ("pmap_advise: invalid PTE")); 5944 pmap_remove_l3(pmap, l3, va, pmap_load(l2), 5945 NULL, &lock); 5946 } 5947 if (lock != NULL) 5948 rw_wunlock(lock); 5949 } 5950 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE, 5951 ("pmap_advise: invalid L2 entry after demotion")); 5952 if (va_next > eva) 5953 va_next = eva; 5954 va = va_next; 5955 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++, 5956 sva += L3_SIZE) { 5957 oldl3 = pmap_load(l3); 5958 if ((oldl3 & (ATTR_SW_MANAGED | ATTR_DESCR_MASK)) != 5959 (ATTR_SW_MANAGED | L3_PAGE)) 5960 goto maybe_invlrng; 5961 else if (pmap_pte_dirty(pmap, oldl3)) { 5962 if (advice == MADV_DONTNEED) { 5963 /* 5964 * Future calls to pmap_is_modified() 5965 * can be avoided by making the page 5966 * dirty now. 5967 */ 5968 m = PHYS_TO_VM_PAGE(oldl3 & ~ATTR_MASK); 5969 vm_page_dirty(m); 5970 } 5971 while (!atomic_fcmpset_long(l3, &oldl3, 5972 (oldl3 & ~ATTR_AF) | 5973 ATTR_S1_AP(ATTR_S1_AP_RO))) 5974 cpu_spinwait(); 5975 } else if ((oldl3 & ATTR_AF) != 0) 5976 pmap_clear_bits(l3, ATTR_AF); 5977 else 5978 goto maybe_invlrng; 5979 if (va == va_next) 5980 va = sva; 5981 continue; 5982 maybe_invlrng: 5983 if (va != va_next) { 5984 pmap_invalidate_range(pmap, va, sva, true); 5985 va = va_next; 5986 } 5987 } 5988 if (va != va_next) 5989 pmap_invalidate_range(pmap, va, sva, true); 5990 } 5991 PMAP_UNLOCK(pmap); 5992 } 5993 5994 /* 5995 * Clear the modify bits on the specified physical page. 5996 */ 5997 void 5998 pmap_clear_modify(vm_page_t m) 5999 { 6000 struct md_page *pvh; 6001 struct rwlock *lock; 6002 pmap_t pmap; 6003 pv_entry_t next_pv, pv; 6004 pd_entry_t *l2, oldl2; 6005 pt_entry_t *l3, oldl3; 6006 vm_offset_t va; 6007 int md_gen, pvh_gen; 6008 6009 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 6010 ("pmap_clear_modify: page %p is not managed", m)); 6011 vm_page_assert_busied(m); 6012 6013 if (!pmap_page_is_write_mapped(m)) 6014 return; 6015 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : page_to_pvh(m); 6016 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 6017 rw_wlock(lock); 6018 restart: 6019 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 6020 pmap = PV_PMAP(pv); 6021 PMAP_ASSERT_STAGE1(pmap); 6022 if (!PMAP_TRYLOCK(pmap)) { 6023 pvh_gen = pvh->pv_gen; 6024 rw_wunlock(lock); 6025 PMAP_LOCK(pmap); 6026 rw_wlock(lock); 6027 if (pvh_gen != pvh->pv_gen) { 6028 PMAP_UNLOCK(pmap); 6029 goto restart; 6030 } 6031 } 6032 va = pv->pv_va; 6033 l2 = pmap_l2(pmap, va); 6034 oldl2 = pmap_load(l2); 6035 /* If oldl2 has ATTR_SW_DBM set, then it is also dirty. */ 6036 if ((oldl2 & ATTR_SW_DBM) != 0 && 6037 pmap_demote_l2_locked(pmap, l2, va, &lock) && 6038 (oldl2 & ATTR_SW_WIRED) == 0) { 6039 /* 6040 * Write protect the mapping to a single page so that 6041 * a subsequent write access may repromote. 6042 */ 6043 va += VM_PAGE_TO_PHYS(m) - (oldl2 & ~ATTR_MASK); 6044 l3 = pmap_l2_to_l3(l2, va); 6045 oldl3 = pmap_load(l3); 6046 while (!atomic_fcmpset_long(l3, &oldl3, 6047 (oldl3 & ~ATTR_SW_DBM) | ATTR_S1_AP(ATTR_S1_AP_RO))) 6048 cpu_spinwait(); 6049 vm_page_dirty(m); 6050 pmap_invalidate_page(pmap, va, true); 6051 } 6052 PMAP_UNLOCK(pmap); 6053 } 6054 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 6055 pmap = PV_PMAP(pv); 6056 PMAP_ASSERT_STAGE1(pmap); 6057 if (!PMAP_TRYLOCK(pmap)) { 6058 md_gen = m->md.pv_gen; 6059 pvh_gen = pvh->pv_gen; 6060 rw_wunlock(lock); 6061 PMAP_LOCK(pmap); 6062 rw_wlock(lock); 6063 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 6064 PMAP_UNLOCK(pmap); 6065 goto restart; 6066 } 6067 } 6068 l2 = pmap_l2(pmap, pv->pv_va); 6069 l3 = pmap_l2_to_l3(l2, pv->pv_va); 6070 oldl3 = pmap_load(l3); 6071 if ((oldl3 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) == ATTR_SW_DBM){ 6072 pmap_set_bits(l3, ATTR_S1_AP(ATTR_S1_AP_RO)); 6073 pmap_invalidate_page(pmap, pv->pv_va, true); 6074 } 6075 PMAP_UNLOCK(pmap); 6076 } 6077 rw_wunlock(lock); 6078 } 6079 6080 void * 6081 pmap_mapbios(vm_paddr_t pa, vm_size_t size) 6082 { 6083 struct pmap_preinit_mapping *ppim; 6084 vm_offset_t va, offset; 6085 pd_entry_t *pde; 6086 pt_entry_t *l2; 6087 int i, lvl, l2_blocks, free_l2_count, start_idx; 6088 6089 if (!vm_initialized) { 6090 /* 6091 * No L3 ptables so map entire L2 blocks where start VA is: 6092 * preinit_map_va + start_idx * L2_SIZE 6093 * There may be duplicate mappings (multiple VA -> same PA) but 6094 * ARM64 dcache is always PIPT so that's acceptable. 6095 */ 6096 if (size == 0) 6097 return (NULL); 6098 6099 /* Calculate how many L2 blocks are needed for the mapping */ 6100 l2_blocks = (roundup2(pa + size, L2_SIZE) - 6101 rounddown2(pa, L2_SIZE)) >> L2_SHIFT; 6102 6103 offset = pa & L2_OFFSET; 6104 6105 if (preinit_map_va == 0) 6106 return (NULL); 6107 6108 /* Map 2MiB L2 blocks from reserved VA space */ 6109 6110 free_l2_count = 0; 6111 start_idx = -1; 6112 /* Find enough free contiguous VA space */ 6113 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 6114 ppim = pmap_preinit_mapping + i; 6115 if (free_l2_count > 0 && ppim->pa != 0) { 6116 /* Not enough space here */ 6117 free_l2_count = 0; 6118 start_idx = -1; 6119 continue; 6120 } 6121 6122 if (ppim->pa == 0) { 6123 /* Free L2 block */ 6124 if (start_idx == -1) 6125 start_idx = i; 6126 free_l2_count++; 6127 if (free_l2_count == l2_blocks) 6128 break; 6129 } 6130 } 6131 if (free_l2_count != l2_blocks) 6132 panic("%s: too many preinit mappings", __func__); 6133 6134 va = preinit_map_va + (start_idx * L2_SIZE); 6135 for (i = start_idx; i < start_idx + l2_blocks; i++) { 6136 /* Mark entries as allocated */ 6137 ppim = pmap_preinit_mapping + i; 6138 ppim->pa = pa; 6139 ppim->va = va + offset; 6140 ppim->size = size; 6141 } 6142 6143 /* Map L2 blocks */ 6144 pa = rounddown2(pa, L2_SIZE); 6145 for (i = 0; i < l2_blocks; i++) { 6146 pde = pmap_pde(kernel_pmap, va, &lvl); 6147 KASSERT(pde != NULL, 6148 ("pmap_mapbios: Invalid page entry, va: 0x%lx", 6149 va)); 6150 KASSERT(lvl == 1, 6151 ("pmap_mapbios: Invalid level %d", lvl)); 6152 6153 /* Insert L2_BLOCK */ 6154 l2 = pmap_l1_to_l2(pde, va); 6155 pmap_load_store(l2, 6156 pa | ATTR_DEFAULT | ATTR_S1_XN | 6157 ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | L2_BLOCK); 6158 6159 va += L2_SIZE; 6160 pa += L2_SIZE; 6161 } 6162 pmap_invalidate_all(kernel_pmap); 6163 6164 va = preinit_map_va + (start_idx * L2_SIZE); 6165 6166 } else { 6167 /* kva_alloc may be used to map the pages */ 6168 offset = pa & PAGE_MASK; 6169 size = round_page(offset + size); 6170 6171 va = kva_alloc(size); 6172 if (va == 0) 6173 panic("%s: Couldn't allocate KVA", __func__); 6174 6175 pde = pmap_pde(kernel_pmap, va, &lvl); 6176 KASSERT(lvl == 2, ("pmap_mapbios: Invalid level %d", lvl)); 6177 6178 /* L3 table is linked */ 6179 va = trunc_page(va); 6180 pa = trunc_page(pa); 6181 pmap_kenter(va, size, pa, memory_mapping_mode(pa)); 6182 } 6183 6184 return ((void *)(va + offset)); 6185 } 6186 6187 void 6188 pmap_unmapbios(void *p, vm_size_t size) 6189 { 6190 struct pmap_preinit_mapping *ppim; 6191 vm_offset_t offset, tmpsize, va, va_trunc; 6192 pd_entry_t *pde; 6193 pt_entry_t *l2; 6194 int i, lvl, l2_blocks, block; 6195 bool preinit_map; 6196 6197 va = (vm_offset_t)p; 6198 l2_blocks = 6199 (roundup2(va + size, L2_SIZE) - rounddown2(va, L2_SIZE)) >> L2_SHIFT; 6200 KASSERT(l2_blocks > 0, ("pmap_unmapbios: invalid size %lx", size)); 6201 6202 /* Remove preinit mapping */ 6203 preinit_map = false; 6204 block = 0; 6205 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) { 6206 ppim = pmap_preinit_mapping + i; 6207 if (ppim->va == va) { 6208 KASSERT(ppim->size == size, 6209 ("pmap_unmapbios: size mismatch")); 6210 ppim->va = 0; 6211 ppim->pa = 0; 6212 ppim->size = 0; 6213 preinit_map = true; 6214 offset = block * L2_SIZE; 6215 va_trunc = rounddown2(va, L2_SIZE) + offset; 6216 6217 /* Remove L2_BLOCK */ 6218 pde = pmap_pde(kernel_pmap, va_trunc, &lvl); 6219 KASSERT(pde != NULL, 6220 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", 6221 va_trunc)); 6222 l2 = pmap_l1_to_l2(pde, va_trunc); 6223 pmap_clear(l2); 6224 6225 if (block == (l2_blocks - 1)) 6226 break; 6227 block++; 6228 } 6229 } 6230 if (preinit_map) { 6231 pmap_invalidate_all(kernel_pmap); 6232 return; 6233 } 6234 6235 /* Unmap the pages reserved with kva_alloc. */ 6236 if (vm_initialized) { 6237 offset = va & PAGE_MASK; 6238 size = round_page(offset + size); 6239 va = trunc_page(va); 6240 6241 pde = pmap_pde(kernel_pmap, va, &lvl); 6242 KASSERT(pde != NULL, 6243 ("pmap_unmapbios: Invalid page entry, va: 0x%lx", va)); 6244 KASSERT(lvl == 2, ("pmap_unmapbios: Invalid level %d", lvl)); 6245 6246 /* Unmap and invalidate the pages */ 6247 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 6248 pmap_kremove(va + tmpsize); 6249 6250 kva_free(va, size); 6251 } 6252 } 6253 6254 /* 6255 * Sets the memory attribute for the specified page. 6256 */ 6257 void 6258 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 6259 { 6260 6261 m->md.pv_memattr = ma; 6262 6263 /* 6264 * If "m" is a normal page, update its direct mapping. This update 6265 * can be relied upon to perform any cache operations that are 6266 * required for data coherence. 6267 */ 6268 if ((m->flags & PG_FICTITIOUS) == 0 && 6269 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE, 6270 m->md.pv_memattr) != 0) 6271 panic("memory attribute change on the direct map failed"); 6272 } 6273 6274 /* 6275 * Changes the specified virtual address range's memory type to that given by 6276 * the parameter "mode". The specified virtual address range must be 6277 * completely contained within either the direct map or the kernel map. If 6278 * the virtual address range is contained within the kernel map, then the 6279 * memory type for each of the corresponding ranges of the direct map is also 6280 * changed. (The corresponding ranges of the direct map are those ranges that 6281 * map the same physical pages as the specified virtual address range.) These 6282 * changes to the direct map are necessary because Intel describes the 6283 * behavior of their processors as "undefined" if two or more mappings to the 6284 * same physical page have different memory types. 6285 * 6286 * Returns zero if the change completed successfully, and either EINVAL or 6287 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 6288 * of the virtual address range was not mapped, and ENOMEM is returned if 6289 * there was insufficient memory available to complete the change. In the 6290 * latter case, the memory type may have been changed on some part of the 6291 * virtual address range or the direct map. 6292 */ 6293 int 6294 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 6295 { 6296 int error; 6297 6298 PMAP_LOCK(kernel_pmap); 6299 error = pmap_change_props_locked(va, size, PROT_NONE, mode, false); 6300 PMAP_UNLOCK(kernel_pmap); 6301 return (error); 6302 } 6303 6304 /* 6305 * Changes the specified virtual address range's protections to those 6306 * specified by "prot". Like pmap_change_attr(), protections for aliases 6307 * in the direct map are updated as well. Protections on aliasing mappings may 6308 * be a subset of the requested protections; for example, mappings in the direct 6309 * map are never executable. 6310 */ 6311 int 6312 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot) 6313 { 6314 int error; 6315 6316 /* Only supported within the kernel map. */ 6317 if (va < VM_MIN_KERNEL_ADDRESS) 6318 return (EINVAL); 6319 6320 PMAP_LOCK(kernel_pmap); 6321 error = pmap_change_props_locked(va, size, prot, -1, false); 6322 PMAP_UNLOCK(kernel_pmap); 6323 return (error); 6324 } 6325 6326 static int 6327 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot, 6328 int mode, bool skip_unmapped) 6329 { 6330 vm_offset_t base, offset, tmpva; 6331 vm_size_t pte_size; 6332 vm_paddr_t pa; 6333 pt_entry_t pte, *ptep, *newpte; 6334 pt_entry_t bits, mask; 6335 int lvl, rv; 6336 6337 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED); 6338 base = trunc_page(va); 6339 offset = va & PAGE_MASK; 6340 size = round_page(offset + size); 6341 6342 if (!VIRT_IN_DMAP(base) && 6343 !(base >= VM_MIN_KERNEL_ADDRESS && base < VM_MAX_KERNEL_ADDRESS)) 6344 return (EINVAL); 6345 6346 bits = 0; 6347 mask = 0; 6348 if (mode != -1) { 6349 bits = ATTR_S1_IDX(mode); 6350 mask = ATTR_S1_IDX_MASK; 6351 if (mode == VM_MEMATTR_DEVICE) { 6352 mask |= ATTR_S1_XN; 6353 bits |= ATTR_S1_XN; 6354 } 6355 } 6356 if (prot != VM_PROT_NONE) { 6357 /* Don't mark the DMAP as executable. It never is on arm64. */ 6358 if (VIRT_IN_DMAP(base)) { 6359 prot &= ~VM_PROT_EXECUTE; 6360 /* 6361 * XXX Mark the DMAP as writable for now. We rely 6362 * on this in ddb & dtrace to insert breakpoint 6363 * instructions. 6364 */ 6365 prot |= VM_PROT_WRITE; 6366 } 6367 6368 if ((prot & VM_PROT_WRITE) == 0) { 6369 bits |= ATTR_S1_AP(ATTR_S1_AP_RO); 6370 } 6371 if ((prot & VM_PROT_EXECUTE) == 0) { 6372 bits |= ATTR_S1_PXN; 6373 } 6374 bits |= ATTR_S1_UXN; 6375 mask |= ATTR_S1_AP_MASK | ATTR_S1_XN; 6376 } 6377 6378 for (tmpva = base; tmpva < base + size; ) { 6379 ptep = pmap_pte(kernel_pmap, tmpva, &lvl); 6380 if (ptep == NULL && !skip_unmapped) { 6381 return (EINVAL); 6382 } else if ((ptep == NULL && skip_unmapped) || 6383 (pmap_load(ptep) & mask) == bits) { 6384 /* 6385 * We already have the correct attribute or there 6386 * is no memory mapped at this address and we are 6387 * skipping unmapped memory. 6388 */ 6389 switch (lvl) { 6390 default: 6391 panic("Invalid DMAP table level: %d\n", lvl); 6392 case 1: 6393 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE; 6394 break; 6395 case 2: 6396 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE; 6397 break; 6398 case 3: 6399 tmpva += PAGE_SIZE; 6400 break; 6401 } 6402 } else { 6403 /* We can't demote/promote this entry */ 6404 MPASS((pmap_load(ptep) & ATTR_SW_NO_PROMOTE) == 0); 6405 6406 /* 6407 * Split the entry to an level 3 table, then 6408 * set the new attribute. 6409 */ 6410 switch (lvl) { 6411 default: 6412 panic("Invalid DMAP table level: %d\n", lvl); 6413 case 1: 6414 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 6415 if ((tmpva & L1_OFFSET) == 0 && 6416 (base + size - tmpva) >= L1_SIZE) { 6417 pte_size = L1_SIZE; 6418 break; 6419 } 6420 newpte = pmap_demote_l1(kernel_pmap, ptep, 6421 tmpva & ~L1_OFFSET); 6422 if (newpte == NULL) 6423 return (EINVAL); 6424 ptep = pmap_l1_to_l2(ptep, tmpva); 6425 /* FALLTHROUGH */ 6426 case 2: 6427 if ((tmpva & L2_OFFSET) == 0 && 6428 (base + size - tmpva) >= L2_SIZE) { 6429 pte_size = L2_SIZE; 6430 break; 6431 } 6432 newpte = pmap_demote_l2(kernel_pmap, ptep, 6433 tmpva); 6434 if (newpte == NULL) 6435 return (EINVAL); 6436 ptep = pmap_l2_to_l3(ptep, tmpva); 6437 /* FALLTHROUGH */ 6438 case 3: 6439 pte_size = PAGE_SIZE; 6440 break; 6441 } 6442 6443 /* Update the entry */ 6444 pte = pmap_load(ptep); 6445 pte &= ~mask; 6446 pte |= bits; 6447 6448 pmap_update_entry(kernel_pmap, ptep, pte, tmpva, 6449 pte_size); 6450 6451 pa = pte & ~ATTR_MASK; 6452 if (!VIRT_IN_DMAP(tmpva) && PHYS_IN_DMAP(pa)) { 6453 /* 6454 * Keep the DMAP memory in sync. 6455 */ 6456 rv = pmap_change_props_locked( 6457 PHYS_TO_DMAP(pa), pte_size, 6458 prot, mode, true); 6459 if (rv != 0) 6460 return (rv); 6461 } 6462 6463 /* 6464 * If moving to a non-cacheable entry flush 6465 * the cache. 6466 */ 6467 if (mode == VM_MEMATTR_UNCACHEABLE) 6468 cpu_dcache_wbinv_range(tmpva, pte_size); 6469 tmpva += pte_size; 6470 } 6471 } 6472 6473 return (0); 6474 } 6475 6476 /* 6477 * Create an L2 table to map all addresses within an L1 mapping. 6478 */ 6479 static pt_entry_t * 6480 pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va) 6481 { 6482 pt_entry_t *l2, newl2, oldl1; 6483 vm_offset_t tmpl1; 6484 vm_paddr_t l2phys, phys; 6485 vm_page_t ml2; 6486 int i; 6487 6488 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6489 oldl1 = pmap_load(l1); 6490 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 6491 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK, 6492 ("pmap_demote_l1: Demoting a non-block entry")); 6493 KASSERT((va & L1_OFFSET) == 0, 6494 ("pmap_demote_l1: Invalid virtual address %#lx", va)); 6495 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0, 6496 ("pmap_demote_l1: Level 1 table shouldn't be managed")); 6497 KASSERT((oldl1 & ATTR_SW_NO_PROMOTE) == 0, 6498 ("pmap_demote_l1: Demoting entry with no-demote flag set")); 6499 6500 tmpl1 = 0; 6501 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) { 6502 tmpl1 = kva_alloc(PAGE_SIZE); 6503 if (tmpl1 == 0) 6504 return (NULL); 6505 } 6506 6507 if ((ml2 = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED)) == 6508 NULL) { 6509 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx" 6510 " in pmap %p", va, pmap); 6511 l2 = NULL; 6512 goto fail; 6513 } 6514 6515 l2phys = VM_PAGE_TO_PHYS(ml2); 6516 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys); 6517 6518 /* Address the range points at */ 6519 phys = oldl1 & ~ATTR_MASK; 6520 /* The attributed from the old l1 table to be copied */ 6521 newl2 = oldl1 & ATTR_MASK; 6522 6523 /* Create the new entries */ 6524 for (i = 0; i < Ln_ENTRIES; i++) { 6525 l2[i] = newl2 | phys; 6526 phys += L2_SIZE; 6527 } 6528 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK), 6529 ("Invalid l2 page (%lx != %lx)", l2[0], 6530 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK)); 6531 6532 if (tmpl1 != 0) { 6533 pmap_kenter(tmpl1, PAGE_SIZE, 6534 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, 6535 VM_MEMATTR_WRITE_BACK); 6536 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK)); 6537 } 6538 6539 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE); 6540 6541 fail: 6542 if (tmpl1 != 0) { 6543 pmap_kremove(tmpl1); 6544 kva_free(tmpl1, PAGE_SIZE); 6545 } 6546 6547 return (l2); 6548 } 6549 6550 static void 6551 pmap_fill_l3(pt_entry_t *firstl3, pt_entry_t newl3) 6552 { 6553 pt_entry_t *l3; 6554 6555 for (l3 = firstl3; l3 - firstl3 < Ln_ENTRIES; l3++) { 6556 *l3 = newl3; 6557 newl3 += L3_SIZE; 6558 } 6559 } 6560 6561 static void 6562 pmap_demote_l2_abort(pmap_t pmap, vm_offset_t va, pt_entry_t *l2, 6563 struct rwlock **lockp) 6564 { 6565 struct spglist free; 6566 6567 SLIST_INIT(&free); 6568 (void)pmap_remove_l2(pmap, l2, va, pmap_load(pmap_l1(pmap, va)), &free, 6569 lockp); 6570 vm_page_free_pages_toq(&free, true); 6571 } 6572 6573 /* 6574 * Create an L3 table to map all addresses within an L2 mapping. 6575 */ 6576 static pt_entry_t * 6577 pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va, 6578 struct rwlock **lockp) 6579 { 6580 pt_entry_t *l3, newl3, oldl2; 6581 vm_offset_t tmpl2; 6582 vm_paddr_t l3phys; 6583 vm_page_t ml3; 6584 6585 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 6586 PMAP_ASSERT_STAGE1(pmap); 6587 KASSERT(ADDR_IS_CANONICAL(va), 6588 ("%s: Address not in canonical form: %lx", __func__, va)); 6589 6590 l3 = NULL; 6591 oldl2 = pmap_load(l2); 6592 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK, 6593 ("pmap_demote_l2: Demoting a non-block entry")); 6594 KASSERT((oldl2 & ATTR_SW_NO_PROMOTE) == 0, 6595 ("pmap_demote_l2: Demoting entry with no-demote flag set")); 6596 va &= ~L2_OFFSET; 6597 6598 tmpl2 = 0; 6599 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) { 6600 tmpl2 = kva_alloc(PAGE_SIZE); 6601 if (tmpl2 == 0) 6602 return (NULL); 6603 } 6604 6605 /* 6606 * Invalidate the 2MB page mapping and return "failure" if the 6607 * mapping was never accessed. 6608 */ 6609 if ((oldl2 & ATTR_AF) == 0) { 6610 KASSERT((oldl2 & ATTR_SW_WIRED) == 0, 6611 ("pmap_demote_l2: a wired mapping is missing ATTR_AF")); 6612 pmap_demote_l2_abort(pmap, va, l2, lockp); 6613 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx in pmap %p", 6614 va, pmap); 6615 goto fail; 6616 } 6617 6618 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) { 6619 KASSERT((oldl2 & ATTR_SW_WIRED) == 0, 6620 ("pmap_demote_l2: page table page for a wired mapping" 6621 " is missing")); 6622 6623 /* 6624 * If the page table page is missing and the mapping 6625 * is for a kernel address, the mapping must belong to 6626 * either the direct map or the early kernel memory. 6627 * Page table pages are preallocated for every other 6628 * part of the kernel address space, so the direct map 6629 * region and early kernel memory are the only parts of the 6630 * kernel address space that must be handled here. 6631 */ 6632 KASSERT(!ADDR_IS_KERNEL(va) || VIRT_IN_DMAP(va) || 6633 (va >= VM_MIN_KERNEL_ADDRESS && va < kernel_vm_end), 6634 ("pmap_demote_l2: No saved mpte for va %#lx", va)); 6635 6636 /* 6637 * If the 2MB page mapping belongs to the direct map 6638 * region of the kernel's address space, then the page 6639 * allocation request specifies the highest possible 6640 * priority (VM_ALLOC_INTERRUPT). Otherwise, the 6641 * priority is normal. 6642 */ 6643 ml3 = vm_page_alloc_noobj( 6644 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : 0) | 6645 VM_ALLOC_WIRED); 6646 6647 /* 6648 * If the allocation of the new page table page fails, 6649 * invalidate the 2MB page mapping and return "failure". 6650 */ 6651 if (ml3 == NULL) { 6652 pmap_demote_l2_abort(pmap, va, l2, lockp); 6653 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx" 6654 " in pmap %p", va, pmap); 6655 goto fail; 6656 } 6657 ml3->pindex = pmap_l2_pindex(va); 6658 6659 if (!ADDR_IS_KERNEL(va)) { 6660 ml3->ref_count = NL3PG; 6661 pmap_resident_count_inc(pmap, 1); 6662 } 6663 } 6664 l3phys = VM_PAGE_TO_PHYS(ml3); 6665 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys); 6666 newl3 = (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE; 6667 KASSERT((oldl2 & (ATTR_S1_AP_RW_BIT | ATTR_SW_DBM)) != 6668 (ATTR_S1_AP(ATTR_S1_AP_RO) | ATTR_SW_DBM), 6669 ("pmap_demote_l2: L2 entry is writeable but not dirty")); 6670 6671 /* 6672 * If the page table page is not leftover from an earlier promotion, 6673 * or the mapping attributes have changed, (re)initialize the L3 table. 6674 * 6675 * When pmap_update_entry() clears the old L2 mapping, it (indirectly) 6676 * performs a dsb(). That dsb() ensures that the stores for filling 6677 * "l3" are visible before "l3" is added to the page table. 6678 */ 6679 if (ml3->valid == 0 || (l3[0] & ATTR_MASK) != (newl3 & ATTR_MASK)) 6680 pmap_fill_l3(l3, newl3); 6681 6682 /* 6683 * Map the temporary page so we don't lose access to the l2 table. 6684 */ 6685 if (tmpl2 != 0) { 6686 pmap_kenter(tmpl2, PAGE_SIZE, 6687 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, 6688 VM_MEMATTR_WRITE_BACK); 6689 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK)); 6690 } 6691 6692 /* 6693 * The spare PV entries must be reserved prior to demoting the 6694 * mapping, that is, prior to changing the PDE. Otherwise, the state 6695 * of the L2 and the PV lists will be inconsistent, which can result 6696 * in reclaim_pv_chunk() attempting to remove a PV entry from the 6697 * wrong PV list and pmap_pv_demote_l2() failing to find the expected 6698 * PV entry for the 2MB page mapping that is being demoted. 6699 */ 6700 if ((oldl2 & ATTR_SW_MANAGED) != 0) 6701 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp); 6702 6703 /* 6704 * Pass PAGE_SIZE so that a single TLB invalidation is performed on 6705 * the 2MB page mapping. 6706 */ 6707 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE); 6708 6709 /* 6710 * Demote the PV entry. 6711 */ 6712 if ((oldl2 & ATTR_SW_MANAGED) != 0) 6713 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp); 6714 6715 atomic_add_long(&pmap_l2_demotions, 1); 6716 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx" 6717 " in pmap %p %lx", va, pmap, l3[0]); 6718 6719 fail: 6720 if (tmpl2 != 0) { 6721 pmap_kremove(tmpl2); 6722 kva_free(tmpl2, PAGE_SIZE); 6723 } 6724 6725 return (l3); 6726 6727 } 6728 6729 static pt_entry_t * 6730 pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va) 6731 { 6732 struct rwlock *lock; 6733 pt_entry_t *l3; 6734 6735 lock = NULL; 6736 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock); 6737 if (lock != NULL) 6738 rw_wunlock(lock); 6739 return (l3); 6740 } 6741 6742 /* 6743 * Perform the pmap work for mincore(2). If the page is not both referenced and 6744 * modified by this pmap, returns its physical address so that the caller can 6745 * find other mappings. 6746 */ 6747 int 6748 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap) 6749 { 6750 pt_entry_t *pte, tpte; 6751 vm_paddr_t mask, pa; 6752 int lvl, val; 6753 bool managed; 6754 6755 PMAP_ASSERT_STAGE1(pmap); 6756 PMAP_LOCK(pmap); 6757 pte = pmap_pte(pmap, addr, &lvl); 6758 if (pte != NULL) { 6759 tpte = pmap_load(pte); 6760 6761 switch (lvl) { 6762 case 3: 6763 mask = L3_OFFSET; 6764 break; 6765 case 2: 6766 mask = L2_OFFSET; 6767 break; 6768 case 1: 6769 mask = L1_OFFSET; 6770 break; 6771 default: 6772 panic("pmap_mincore: invalid level %d", lvl); 6773 } 6774 6775 managed = (tpte & ATTR_SW_MANAGED) != 0; 6776 val = MINCORE_INCORE; 6777 if (lvl != 3) 6778 val |= MINCORE_PSIND(3 - lvl); 6779 if ((managed && pmap_pte_dirty(pmap, tpte)) || (!managed && 6780 (tpte & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP(ATTR_S1_AP_RW))) 6781 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 6782 if ((tpte & ATTR_AF) == ATTR_AF) 6783 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 6784 6785 pa = (tpte & ~ATTR_MASK) | (addr & mask); 6786 } else { 6787 managed = false; 6788 val = 0; 6789 } 6790 6791 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 6792 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 6793 *pap = pa; 6794 } 6795 PMAP_UNLOCK(pmap); 6796 return (val); 6797 } 6798 6799 /* 6800 * Garbage collect every ASID that is neither active on a processor nor 6801 * reserved. 6802 */ 6803 static void 6804 pmap_reset_asid_set(pmap_t pmap) 6805 { 6806 pmap_t curpmap; 6807 int asid, cpuid, epoch; 6808 struct asid_set *set; 6809 enum pmap_stage stage; 6810 6811 set = pmap->pm_asid_set; 6812 stage = pmap->pm_stage; 6813 6814 set = pmap->pm_asid_set; 6815 KASSERT(set != NULL, ("%s: NULL asid set", __func__)); 6816 mtx_assert(&set->asid_set_mutex, MA_OWNED); 6817 6818 /* 6819 * Ensure that the store to asid_epoch is globally visible before the 6820 * loads from pc_curpmap are performed. 6821 */ 6822 epoch = set->asid_epoch + 1; 6823 if (epoch == INT_MAX) 6824 epoch = 0; 6825 set->asid_epoch = epoch; 6826 dsb(ishst); 6827 if (stage == PM_STAGE1) { 6828 __asm __volatile("tlbi vmalle1is"); 6829 } else { 6830 KASSERT(pmap_clean_stage2_tlbi != NULL, 6831 ("%s: Unset stage 2 tlb invalidation callback\n", 6832 __func__)); 6833 pmap_clean_stage2_tlbi(); 6834 } 6835 dsb(ish); 6836 bit_nclear(set->asid_set, ASID_FIRST_AVAILABLE, 6837 set->asid_set_size - 1); 6838 CPU_FOREACH(cpuid) { 6839 if (cpuid == curcpu) 6840 continue; 6841 if (stage == PM_STAGE1) { 6842 curpmap = pcpu_find(cpuid)->pc_curpmap; 6843 PMAP_ASSERT_STAGE1(pmap); 6844 } else { 6845 curpmap = pcpu_find(cpuid)->pc_curvmpmap; 6846 if (curpmap == NULL) 6847 continue; 6848 PMAP_ASSERT_STAGE2(pmap); 6849 } 6850 KASSERT(curpmap->pm_asid_set == set, ("Incorrect set")); 6851 asid = COOKIE_TO_ASID(curpmap->pm_cookie); 6852 if (asid == -1) 6853 continue; 6854 bit_set(set->asid_set, asid); 6855 curpmap->pm_cookie = COOKIE_FROM(asid, epoch); 6856 } 6857 } 6858 6859 /* 6860 * Allocate a new ASID for the specified pmap. 6861 */ 6862 static void 6863 pmap_alloc_asid(pmap_t pmap) 6864 { 6865 struct asid_set *set; 6866 int new_asid; 6867 6868 set = pmap->pm_asid_set; 6869 KASSERT(set != NULL, ("%s: NULL asid set", __func__)); 6870 6871 mtx_lock_spin(&set->asid_set_mutex); 6872 6873 /* 6874 * While this processor was waiting to acquire the asid set mutex, 6875 * pmap_reset_asid_set() running on another processor might have 6876 * updated this pmap's cookie to the current epoch. In which case, we 6877 * don't need to allocate a new ASID. 6878 */ 6879 if (COOKIE_TO_EPOCH(pmap->pm_cookie) == set->asid_epoch) 6880 goto out; 6881 6882 bit_ffc_at(set->asid_set, set->asid_next, set->asid_set_size, 6883 &new_asid); 6884 if (new_asid == -1) { 6885 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE, 6886 set->asid_next, &new_asid); 6887 if (new_asid == -1) { 6888 pmap_reset_asid_set(pmap); 6889 bit_ffc_at(set->asid_set, ASID_FIRST_AVAILABLE, 6890 set->asid_set_size, &new_asid); 6891 KASSERT(new_asid != -1, ("ASID allocation failure")); 6892 } 6893 } 6894 bit_set(set->asid_set, new_asid); 6895 set->asid_next = new_asid + 1; 6896 pmap->pm_cookie = COOKIE_FROM(new_asid, set->asid_epoch); 6897 out: 6898 mtx_unlock_spin(&set->asid_set_mutex); 6899 } 6900 6901 static uint64_t __read_mostly ttbr_flags; 6902 6903 /* 6904 * Compute the value that should be stored in ttbr0 to activate the specified 6905 * pmap. This value may change from time to time. 6906 */ 6907 uint64_t 6908 pmap_to_ttbr0(pmap_t pmap) 6909 { 6910 uint64_t ttbr; 6911 6912 ttbr = pmap->pm_ttbr; 6913 ttbr |= ASID_TO_OPERAND(COOKIE_TO_ASID(pmap->pm_cookie)); 6914 ttbr |= ttbr_flags; 6915 6916 return (ttbr); 6917 } 6918 6919 static void 6920 pmap_set_cnp(void *arg) 6921 { 6922 uint64_t ttbr0, ttbr1; 6923 u_int cpuid; 6924 6925 cpuid = *(u_int *)arg; 6926 if (cpuid == curcpu) { 6927 /* 6928 * Set the flags while all CPUs are handling the 6929 * smp_rendezvous so will not call pmap_to_ttbr0. Any calls 6930 * to pmap_to_ttbr0 after this will have the CnP flag set. 6931 * The dsb after invalidating the TLB will act as a barrier 6932 * to ensure all CPUs can observe this change. 6933 */ 6934 ttbr_flags |= TTBR_CnP; 6935 } 6936 6937 ttbr0 = READ_SPECIALREG(ttbr0_el1); 6938 ttbr0 |= TTBR_CnP; 6939 6940 ttbr1 = READ_SPECIALREG(ttbr1_el1); 6941 ttbr1 |= TTBR_CnP; 6942 6943 /* Update ttbr{0,1}_el1 with the CnP flag */ 6944 WRITE_SPECIALREG(ttbr0_el1, ttbr0); 6945 WRITE_SPECIALREG(ttbr1_el1, ttbr1); 6946 isb(); 6947 __asm __volatile("tlbi vmalle1is"); 6948 dsb(ish); 6949 isb(); 6950 } 6951 6952 /* 6953 * Defer enabling CnP until we have read the ID registers to know if it's 6954 * supported on all CPUs. 6955 */ 6956 static void 6957 pmap_init_cnp(void *dummy __unused) 6958 { 6959 uint64_t reg; 6960 u_int cpuid; 6961 6962 if (!get_kernel_reg(ID_AA64MMFR2_EL1, ®)) 6963 return; 6964 6965 if (ID_AA64MMFR2_CnP_VAL(reg) != ID_AA64MMFR2_CnP_NONE) { 6966 if (bootverbose) 6967 printf("Enabling CnP\n"); 6968 cpuid = curcpu; 6969 smp_rendezvous(NULL, pmap_set_cnp, NULL, &cpuid); 6970 } 6971 6972 } 6973 SYSINIT(pmap_init_cnp, SI_SUB_SMP, SI_ORDER_ANY, pmap_init_cnp, NULL); 6974 6975 static bool 6976 pmap_activate_int(pmap_t pmap) 6977 { 6978 struct asid_set *set; 6979 int epoch; 6980 6981 KASSERT(PCPU_GET(curpmap) != NULL, ("no active pmap")); 6982 KASSERT(pmap != kernel_pmap, ("kernel pmap activation")); 6983 6984 if ((pmap->pm_stage == PM_STAGE1 && pmap == PCPU_GET(curpmap)) || 6985 (pmap->pm_stage == PM_STAGE2 && pmap == PCPU_GET(curvmpmap))) { 6986 /* 6987 * Handle the possibility that the old thread was preempted 6988 * after an "ic" or "tlbi" instruction but before it performed 6989 * a "dsb" instruction. If the old thread migrates to a new 6990 * processor, its completion of a "dsb" instruction on that 6991 * new processor does not guarantee that the "ic" or "tlbi" 6992 * instructions performed on the old processor have completed. 6993 */ 6994 dsb(ish); 6995 return (false); 6996 } 6997 6998 set = pmap->pm_asid_set; 6999 KASSERT(set != NULL, ("%s: NULL asid set", __func__)); 7000 7001 /* 7002 * Ensure that the store to curpmap is globally visible before the 7003 * load from asid_epoch is performed. 7004 */ 7005 if (pmap->pm_stage == PM_STAGE1) 7006 PCPU_SET(curpmap, pmap); 7007 else 7008 PCPU_SET(curvmpmap, pmap); 7009 dsb(ish); 7010 epoch = COOKIE_TO_EPOCH(pmap->pm_cookie); 7011 if (epoch >= 0 && epoch != set->asid_epoch) 7012 pmap_alloc_asid(pmap); 7013 7014 if (pmap->pm_stage == PM_STAGE1) { 7015 set_ttbr0(pmap_to_ttbr0(pmap)); 7016 if (PCPU_GET(bcast_tlbi_workaround) != 0) 7017 invalidate_local_icache(); 7018 } 7019 return (true); 7020 } 7021 7022 void 7023 pmap_activate_vm(pmap_t pmap) 7024 { 7025 7026 PMAP_ASSERT_STAGE2(pmap); 7027 7028 (void)pmap_activate_int(pmap); 7029 } 7030 7031 void 7032 pmap_activate(struct thread *td) 7033 { 7034 pmap_t pmap; 7035 7036 pmap = vmspace_pmap(td->td_proc->p_vmspace); 7037 PMAP_ASSERT_STAGE1(pmap); 7038 critical_enter(); 7039 (void)pmap_activate_int(pmap); 7040 critical_exit(); 7041 } 7042 7043 /* 7044 * Activate the thread we are switching to. 7045 * To simplify the assembly in cpu_throw return the new threads pcb. 7046 */ 7047 struct pcb * 7048 pmap_switch(struct thread *new) 7049 { 7050 pcpu_bp_harden bp_harden; 7051 struct pcb *pcb; 7052 7053 /* Store the new curthread */ 7054 PCPU_SET(curthread, new); 7055 #if defined(PERTHREAD_SSP) 7056 /* Set the new threads SSP canary */ 7057 __asm("msr sp_el0, %0" :: "r"(&new->td_md.md_canary)); 7058 #endif 7059 7060 /* And the new pcb */ 7061 pcb = new->td_pcb; 7062 PCPU_SET(curpcb, pcb); 7063 7064 /* 7065 * TODO: We may need to flush the cache here if switching 7066 * to a user process. 7067 */ 7068 7069 if (pmap_activate_int(vmspace_pmap(new->td_proc->p_vmspace))) { 7070 /* 7071 * Stop userspace from training the branch predictor against 7072 * other processes. This will call into a CPU specific 7073 * function that clears the branch predictor state. 7074 */ 7075 bp_harden = PCPU_GET(bp_harden); 7076 if (bp_harden != NULL) 7077 bp_harden(); 7078 } 7079 7080 return (pcb); 7081 } 7082 7083 void 7084 pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz) 7085 { 7086 7087 PMAP_ASSERT_STAGE1(pmap); 7088 KASSERT(ADDR_IS_CANONICAL(va), 7089 ("%s: Address not in canonical form: %lx", __func__, va)); 7090 7091 if (ADDR_IS_KERNEL(va)) { 7092 cpu_icache_sync_range(va, sz); 7093 } else { 7094 u_int len, offset; 7095 vm_paddr_t pa; 7096 7097 /* Find the length of data in this page to flush */ 7098 offset = va & PAGE_MASK; 7099 len = imin(PAGE_SIZE - offset, sz); 7100 7101 while (sz != 0) { 7102 /* Extract the physical address & find it in the DMAP */ 7103 pa = pmap_extract(pmap, va); 7104 if (pa != 0) 7105 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len); 7106 7107 /* Move to the next page */ 7108 sz -= len; 7109 va += len; 7110 /* Set the length for the next iteration */ 7111 len = imin(PAGE_SIZE, sz); 7112 } 7113 } 7114 } 7115 7116 static int 7117 pmap_stage2_fault(pmap_t pmap, uint64_t esr, uint64_t far) 7118 { 7119 pd_entry_t *pdep; 7120 pt_entry_t *ptep, pte; 7121 int rv, lvl, dfsc; 7122 7123 PMAP_ASSERT_STAGE2(pmap); 7124 rv = KERN_FAILURE; 7125 7126 /* Data and insn aborts use same encoding for FSC field. */ 7127 dfsc = esr & ISS_DATA_DFSC_MASK; 7128 switch (dfsc) { 7129 case ISS_DATA_DFSC_TF_L0: 7130 case ISS_DATA_DFSC_TF_L1: 7131 case ISS_DATA_DFSC_TF_L2: 7132 case ISS_DATA_DFSC_TF_L3: 7133 PMAP_LOCK(pmap); 7134 pdep = pmap_pde(pmap, far, &lvl); 7135 if (pdep == NULL || lvl != (dfsc - ISS_DATA_DFSC_TF_L1)) { 7136 PMAP_LOCK(pmap); 7137 break; 7138 } 7139 7140 switch (lvl) { 7141 case 0: 7142 ptep = pmap_l0_to_l1(pdep, far); 7143 break; 7144 case 1: 7145 ptep = pmap_l1_to_l2(pdep, far); 7146 break; 7147 case 2: 7148 ptep = pmap_l2_to_l3(pdep, far); 7149 break; 7150 default: 7151 panic("%s: Invalid pde level %d", __func__,lvl); 7152 } 7153 goto fault_exec; 7154 7155 case ISS_DATA_DFSC_AFF_L1: 7156 case ISS_DATA_DFSC_AFF_L2: 7157 case ISS_DATA_DFSC_AFF_L3: 7158 PMAP_LOCK(pmap); 7159 ptep = pmap_pte(pmap, far, &lvl); 7160 fault_exec: 7161 if (ptep != NULL && (pte = pmap_load(ptep)) != 0) { 7162 if (icache_vmid) { 7163 pmap_invalidate_vpipt_icache(); 7164 } else { 7165 /* 7166 * If accessing an executable page invalidate 7167 * the I-cache so it will be valid when we 7168 * continue execution in the guest. The D-cache 7169 * is assumed to already be clean to the Point 7170 * of Coherency. 7171 */ 7172 if ((pte & ATTR_S2_XN_MASK) != 7173 ATTR_S2_XN(ATTR_S2_XN_NONE)) { 7174 invalidate_icache(); 7175 } 7176 } 7177 pmap_set_bits(ptep, ATTR_AF | ATTR_DESCR_VALID); 7178 rv = KERN_SUCCESS; 7179 } 7180 PMAP_UNLOCK(pmap); 7181 break; 7182 } 7183 7184 return (rv); 7185 } 7186 7187 int 7188 pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far) 7189 { 7190 pt_entry_t pte, *ptep; 7191 register_t intr; 7192 uint64_t ec, par; 7193 int lvl, rv; 7194 7195 rv = KERN_FAILURE; 7196 7197 ec = ESR_ELx_EXCEPTION(esr); 7198 switch (ec) { 7199 case EXCP_INSN_ABORT_L: 7200 case EXCP_INSN_ABORT: 7201 case EXCP_DATA_ABORT_L: 7202 case EXCP_DATA_ABORT: 7203 break; 7204 default: 7205 return (rv); 7206 } 7207 7208 if (pmap->pm_stage == PM_STAGE2) 7209 return (pmap_stage2_fault(pmap, esr, far)); 7210 7211 /* Data and insn aborts use same encoding for FSC field. */ 7212 switch (esr & ISS_DATA_DFSC_MASK) { 7213 case ISS_DATA_DFSC_AFF_L1: 7214 case ISS_DATA_DFSC_AFF_L2: 7215 case ISS_DATA_DFSC_AFF_L3: 7216 PMAP_LOCK(pmap); 7217 ptep = pmap_pte(pmap, far, &lvl); 7218 if (ptep != NULL) { 7219 pmap_set_bits(ptep, ATTR_AF); 7220 rv = KERN_SUCCESS; 7221 /* 7222 * XXXMJ as an optimization we could mark the entry 7223 * dirty if this is a write fault. 7224 */ 7225 } 7226 PMAP_UNLOCK(pmap); 7227 break; 7228 case ISS_DATA_DFSC_PF_L1: 7229 case ISS_DATA_DFSC_PF_L2: 7230 case ISS_DATA_DFSC_PF_L3: 7231 if ((ec != EXCP_DATA_ABORT_L && ec != EXCP_DATA_ABORT) || 7232 (esr & ISS_DATA_WnR) == 0) 7233 return (rv); 7234 PMAP_LOCK(pmap); 7235 ptep = pmap_pte(pmap, far, &lvl); 7236 if (ptep != NULL && 7237 ((pte = pmap_load(ptep)) & ATTR_SW_DBM) != 0) { 7238 if ((pte & ATTR_S1_AP_RW_BIT) == 7239 ATTR_S1_AP(ATTR_S1_AP_RO)) { 7240 pmap_clear_bits(ptep, ATTR_S1_AP_RW_BIT); 7241 pmap_invalidate_page(pmap, far, true); 7242 } 7243 rv = KERN_SUCCESS; 7244 } 7245 PMAP_UNLOCK(pmap); 7246 break; 7247 case ISS_DATA_DFSC_TF_L0: 7248 case ISS_DATA_DFSC_TF_L1: 7249 case ISS_DATA_DFSC_TF_L2: 7250 case ISS_DATA_DFSC_TF_L3: 7251 /* 7252 * Retry the translation. A break-before-make sequence can 7253 * produce a transient fault. 7254 */ 7255 if (pmap == kernel_pmap) { 7256 /* 7257 * The translation fault may have occurred within a 7258 * critical section. Therefore, we must check the 7259 * address without acquiring the kernel pmap's lock. 7260 */ 7261 if (pmap_klookup(far, NULL)) 7262 rv = KERN_SUCCESS; 7263 } else { 7264 PMAP_LOCK(pmap); 7265 /* Ask the MMU to check the address. */ 7266 intr = intr_disable(); 7267 par = arm64_address_translate_s1e0r(far); 7268 intr_restore(intr); 7269 PMAP_UNLOCK(pmap); 7270 7271 /* 7272 * If the translation was successful, then we can 7273 * return success to the trap handler. 7274 */ 7275 if (PAR_SUCCESS(par)) 7276 rv = KERN_SUCCESS; 7277 } 7278 break; 7279 } 7280 7281 return (rv); 7282 } 7283 7284 /* 7285 * Increase the starting virtual address of the given mapping if a 7286 * different alignment might result in more superpage mappings. 7287 */ 7288 void 7289 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 7290 vm_offset_t *addr, vm_size_t size) 7291 { 7292 vm_offset_t superpage_offset; 7293 7294 if (size < L2_SIZE) 7295 return; 7296 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 7297 offset += ptoa(object->pg_color); 7298 superpage_offset = offset & L2_OFFSET; 7299 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE || 7300 (*addr & L2_OFFSET) == superpage_offset) 7301 return; 7302 if ((*addr & L2_OFFSET) < superpage_offset) 7303 *addr = (*addr & ~L2_OFFSET) + superpage_offset; 7304 else 7305 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset; 7306 } 7307 7308 /** 7309 * Get the kernel virtual address of a set of physical pages. If there are 7310 * physical addresses not covered by the DMAP perform a transient mapping 7311 * that will be removed when calling pmap_unmap_io_transient. 7312 * 7313 * \param page The pages the caller wishes to obtain the virtual 7314 * address on the kernel memory map. 7315 * \param vaddr On return contains the kernel virtual memory address 7316 * of the pages passed in the page parameter. 7317 * \param count Number of pages passed in. 7318 * \param can_fault TRUE if the thread using the mapped pages can take 7319 * page faults, FALSE otherwise. 7320 * 7321 * \returns TRUE if the caller must call pmap_unmap_io_transient when 7322 * finished or FALSE otherwise. 7323 * 7324 */ 7325 boolean_t 7326 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, 7327 boolean_t can_fault) 7328 { 7329 vm_paddr_t paddr; 7330 boolean_t needs_mapping; 7331 int error __diagused, i; 7332 7333 /* 7334 * Allocate any KVA space that we need, this is done in a separate 7335 * loop to prevent calling vmem_alloc while pinned. 7336 */ 7337 needs_mapping = FALSE; 7338 for (i = 0; i < count; i++) { 7339 paddr = VM_PAGE_TO_PHYS(page[i]); 7340 if (__predict_false(!PHYS_IN_DMAP(paddr))) { 7341 error = vmem_alloc(kernel_arena, PAGE_SIZE, 7342 M_BESTFIT | M_WAITOK, &vaddr[i]); 7343 KASSERT(error == 0, ("vmem_alloc failed: %d", error)); 7344 needs_mapping = TRUE; 7345 } else { 7346 vaddr[i] = PHYS_TO_DMAP(paddr); 7347 } 7348 } 7349 7350 /* Exit early if everything is covered by the DMAP */ 7351 if (!needs_mapping) 7352 return (FALSE); 7353 7354 if (!can_fault) 7355 sched_pin(); 7356 for (i = 0; i < count; i++) { 7357 paddr = VM_PAGE_TO_PHYS(page[i]); 7358 if (!PHYS_IN_DMAP(paddr)) { 7359 panic( 7360 "pmap_map_io_transient: TODO: Map out of DMAP data"); 7361 } 7362 } 7363 7364 return (needs_mapping); 7365 } 7366 7367 void 7368 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, 7369 boolean_t can_fault) 7370 { 7371 vm_paddr_t paddr; 7372 int i; 7373 7374 if (!can_fault) 7375 sched_unpin(); 7376 for (i = 0; i < count; i++) { 7377 paddr = VM_PAGE_TO_PHYS(page[i]); 7378 if (!PHYS_IN_DMAP(paddr)) { 7379 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data"); 7380 } 7381 } 7382 } 7383 7384 boolean_t 7385 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode) 7386 { 7387 7388 return (mode >= VM_MEMATTR_DEVICE && mode <= VM_MEMATTR_WRITE_THROUGH); 7389 } 7390 7391 /* 7392 * Track a range of the kernel's virtual address space that is contiguous 7393 * in various mapping attributes. 7394 */ 7395 struct pmap_kernel_map_range { 7396 vm_offset_t sva; 7397 pt_entry_t attrs; 7398 int l3pages; 7399 int l3contig; 7400 int l2blocks; 7401 int l1blocks; 7402 }; 7403 7404 static void 7405 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range, 7406 vm_offset_t eva) 7407 { 7408 const char *mode; 7409 int index; 7410 7411 if (eva <= range->sva) 7412 return; 7413 7414 index = range->attrs & ATTR_S1_IDX_MASK; 7415 switch (index) { 7416 case ATTR_S1_IDX(VM_MEMATTR_DEVICE): 7417 mode = "DEV"; 7418 break; 7419 case ATTR_S1_IDX(VM_MEMATTR_UNCACHEABLE): 7420 mode = "UC"; 7421 break; 7422 case ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK): 7423 mode = "WB"; 7424 break; 7425 case ATTR_S1_IDX(VM_MEMATTR_WRITE_THROUGH): 7426 mode = "WT"; 7427 break; 7428 default: 7429 printf( 7430 "%s: unknown memory type %x for range 0x%016lx-0x%016lx\n", 7431 __func__, index, range->sva, eva); 7432 mode = "??"; 7433 break; 7434 } 7435 7436 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %3s %d %d %d %d\n", 7437 range->sva, eva, 7438 (range->attrs & ATTR_S1_AP_RW_BIT) == ATTR_S1_AP_RW ? 'w' : '-', 7439 (range->attrs & ATTR_S1_PXN) != 0 ? '-' : 'x', 7440 (range->attrs & ATTR_S1_UXN) != 0 ? '-' : 'X', 7441 (range->attrs & ATTR_S1_AP(ATTR_S1_AP_USER)) != 0 ? 'u' : 's', 7442 mode, range->l1blocks, range->l2blocks, range->l3contig, 7443 range->l3pages); 7444 7445 /* Reset to sentinel value. */ 7446 range->sva = 0xfffffffffffffffful; 7447 } 7448 7449 /* 7450 * Determine whether the attributes specified by a page table entry match those 7451 * being tracked by the current range. 7452 */ 7453 static bool 7454 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs) 7455 { 7456 7457 return (range->attrs == attrs); 7458 } 7459 7460 static void 7461 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va, 7462 pt_entry_t attrs) 7463 { 7464 7465 memset(range, 0, sizeof(*range)); 7466 range->sva = va; 7467 range->attrs = attrs; 7468 } 7469 7470 /* Get the block/page attributes that correspond to the table attributes */ 7471 static pt_entry_t 7472 sysctl_kmaps_table_attrs(pd_entry_t table) 7473 { 7474 pt_entry_t attrs; 7475 7476 attrs = 0; 7477 if ((table & TATTR_UXN_TABLE) != 0) 7478 attrs |= ATTR_S1_UXN; 7479 if ((table & TATTR_PXN_TABLE) != 0) 7480 attrs |= ATTR_S1_PXN; 7481 if ((table & TATTR_AP_TABLE_RO) != 0) 7482 attrs |= ATTR_S1_AP(ATTR_S1_AP_RO); 7483 7484 return (attrs); 7485 } 7486 7487 /* Read the block/page attributes we care about */ 7488 static pt_entry_t 7489 sysctl_kmaps_block_attrs(pt_entry_t block) 7490 { 7491 return (block & (ATTR_S1_AP_MASK | ATTR_S1_XN | ATTR_S1_IDX_MASK)); 7492 } 7493 7494 /* 7495 * Given a leaf PTE, derive the mapping's attributes. If they do not match 7496 * those of the current run, dump the address range and its attributes, and 7497 * begin a new run. 7498 */ 7499 static void 7500 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range, 7501 vm_offset_t va, pd_entry_t l0e, pd_entry_t l1e, pd_entry_t l2e, 7502 pt_entry_t l3e) 7503 { 7504 pt_entry_t attrs; 7505 7506 attrs = sysctl_kmaps_table_attrs(l0e); 7507 7508 if ((l1e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) { 7509 attrs |= sysctl_kmaps_block_attrs(l1e); 7510 goto done; 7511 } 7512 attrs |= sysctl_kmaps_table_attrs(l1e); 7513 7514 if ((l2e & ATTR_DESCR_TYPE_MASK) == ATTR_DESCR_TYPE_BLOCK) { 7515 attrs |= sysctl_kmaps_block_attrs(l2e); 7516 goto done; 7517 } 7518 attrs |= sysctl_kmaps_table_attrs(l2e); 7519 attrs |= sysctl_kmaps_block_attrs(l3e); 7520 7521 done: 7522 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) { 7523 sysctl_kmaps_dump(sb, range, va); 7524 sysctl_kmaps_reinit(range, va, attrs); 7525 } 7526 } 7527 7528 static int 7529 sysctl_kmaps(SYSCTL_HANDLER_ARGS) 7530 { 7531 struct pmap_kernel_map_range range; 7532 struct sbuf sbuf, *sb; 7533 pd_entry_t l0e, *l1, l1e, *l2, l2e; 7534 pt_entry_t *l3, l3e; 7535 vm_offset_t sva; 7536 vm_paddr_t pa; 7537 int error, i, j, k, l; 7538 7539 error = sysctl_wire_old_buffer(req, 0); 7540 if (error != 0) 7541 return (error); 7542 sb = &sbuf; 7543 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req); 7544 7545 /* Sentinel value. */ 7546 range.sva = 0xfffffffffffffffful; 7547 7548 /* 7549 * Iterate over the kernel page tables without holding the kernel pmap 7550 * lock. Kernel page table pages are never freed, so at worst we will 7551 * observe inconsistencies in the output. 7552 */ 7553 for (sva = 0xffff000000000000ul, i = pmap_l0_index(sva); i < Ln_ENTRIES; 7554 i++) { 7555 if (i == pmap_l0_index(DMAP_MIN_ADDRESS)) 7556 sbuf_printf(sb, "\nDirect map:\n"); 7557 else if (i == pmap_l0_index(VM_MIN_KERNEL_ADDRESS)) 7558 sbuf_printf(sb, "\nKernel map:\n"); 7559 7560 l0e = kernel_pmap->pm_l0[i]; 7561 if ((l0e & ATTR_DESCR_VALID) == 0) { 7562 sysctl_kmaps_dump(sb, &range, sva); 7563 sva += L0_SIZE; 7564 continue; 7565 } 7566 pa = l0e & ~ATTR_MASK; 7567 l1 = (pd_entry_t *)PHYS_TO_DMAP(pa); 7568 7569 for (j = pmap_l1_index(sva); j < Ln_ENTRIES; j++) { 7570 l1e = l1[j]; 7571 if ((l1e & ATTR_DESCR_VALID) == 0) { 7572 sysctl_kmaps_dump(sb, &range, sva); 7573 sva += L1_SIZE; 7574 continue; 7575 } 7576 if ((l1e & ATTR_DESCR_MASK) == L1_BLOCK) { 7577 PMAP_ASSERT_L1_BLOCKS_SUPPORTED; 7578 sysctl_kmaps_check(sb, &range, sva, l0e, l1e, 7579 0, 0); 7580 range.l1blocks++; 7581 sva += L1_SIZE; 7582 continue; 7583 } 7584 pa = l1e & ~ATTR_MASK; 7585 l2 = (pd_entry_t *)PHYS_TO_DMAP(pa); 7586 7587 for (k = pmap_l2_index(sva); k < Ln_ENTRIES; k++) { 7588 l2e = l2[k]; 7589 if ((l2e & ATTR_DESCR_VALID) == 0) { 7590 sysctl_kmaps_dump(sb, &range, sva); 7591 sva += L2_SIZE; 7592 continue; 7593 } 7594 if ((l2e & ATTR_DESCR_MASK) == L2_BLOCK) { 7595 sysctl_kmaps_check(sb, &range, sva, 7596 l0e, l1e, l2e, 0); 7597 range.l2blocks++; 7598 sva += L2_SIZE; 7599 continue; 7600 } 7601 pa = l2e & ~ATTR_MASK; 7602 l3 = (pt_entry_t *)PHYS_TO_DMAP(pa); 7603 7604 for (l = pmap_l3_index(sva); l < Ln_ENTRIES; 7605 l++, sva += L3_SIZE) { 7606 l3e = l3[l]; 7607 if ((l3e & ATTR_DESCR_VALID) == 0) { 7608 sysctl_kmaps_dump(sb, &range, 7609 sva); 7610 continue; 7611 } 7612 sysctl_kmaps_check(sb, &range, sva, 7613 l0e, l1e, l2e, l3e); 7614 if ((l3e & ATTR_CONTIGUOUS) != 0) 7615 range.l3contig += l % 16 == 0 ? 7616 1 : 0; 7617 else 7618 range.l3pages++; 7619 } 7620 } 7621 } 7622 } 7623 7624 error = sbuf_finish(sb); 7625 sbuf_delete(sb); 7626 return (error); 7627 } 7628 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps, 7629 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE | CTLFLAG_SKIP, 7630 NULL, 0, sysctl_kmaps, "A", 7631 "Dump kernel address layout"); 7632