1 /*- 2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by BAE Systems, the University of Cambridge 6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract 7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing 8 * (TC) research program. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <machine/bus.h> 42 43 #include <arm64/coresight/coresight.h> 44 #include <arm64/coresight/coresight_etm4x.h> 45 46 #include "coresight_if.h" 47 48 #define ETM_DEBUG 49 #undef ETM_DEBUG 50 51 #ifdef ETM_DEBUG 52 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) 53 #else 54 #define dprintf(fmt, ...) 55 #endif 56 57 /* 58 * Typical trace flow: 59 * 60 * CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM 61 * CPU1 -> ETM1 -> funnel1 -^ 62 * CPU2 -> ETM2 -> funnel1 -^ 63 * CPU3 -> ETM3 -> funnel1 -^ 64 */ 65 66 static struct resource_spec etm_spec[] = { 67 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 68 { -1, 0 } 69 }; 70 71 static int 72 etm_prepare(device_t dev, struct coresight_event *event) 73 { 74 struct etm_softc *sc; 75 uint32_t reg; 76 int i; 77 78 sc = device_get_softc(dev); 79 80 /* Configure ETM */ 81 82 /* 83 * Enable the return stack, global timestamping, 84 * Context ID, and Virtual context identifier tracing. 85 */ 86 reg = TRCCONFIGR_RS | TRCCONFIGR_TS; 87 reg |= TRCCONFIGR_CID | TRCCONFIGR_VMID; 88 reg |= TRCCONFIGR_INSTP0_LDRSTR; 89 reg |= TRCCONFIGR_COND_ALL; 90 bus_write_4(sc->res, TRCCONFIGR, reg); 91 92 /* Disable all event tracing. */ 93 bus_write_4(sc->res, TRCEVENTCTL0R, 0); 94 bus_write_4(sc->res, TRCEVENTCTL1R, 0); 95 96 /* Disable stalling, if implemented. */ 97 bus_write_4(sc->res, TRCSTALLCTLR, 0); 98 99 /* Enable trace synchronization every 4096 bytes of trace. */ 100 bus_write_4(sc->res, TRCSYNCPR, TRCSYNCPR_4K); 101 102 /* Set a value for the trace ID */ 103 bus_write_4(sc->res, TRCTRACEIDR, event->etm.trace_id); 104 105 /* 106 * Disable the timestamp event. The trace unit still generates 107 * timestamps due to other reasons such as trace synchronization. 108 */ 109 bus_write_4(sc->res, TRCTSCTLR, 0); 110 111 /* 112 * Enable ViewInst to trace everything, with the start/stop 113 * logic started. 114 */ 115 reg = TRCVICTLR_SSSTATUS; 116 117 /* The number of the single resource used to activate the event. */ 118 reg |= (1 << EVENT_SEL_S); 119 120 if (event->excp_level > 2) 121 return (-1); 122 123 reg |= TRCVICTLR_EXLEVEL_NS_M; 124 reg &= ~TRCVICTLR_EXLEVEL_NS(event->excp_level); 125 reg |= TRCVICTLR_EXLEVEL_S_M; 126 reg &= ~TRCVICTLR_EXLEVEL_S(event->excp_level); 127 bus_write_4(sc->res, TRCVICTLR, reg); 128 129 for (i = 0; i < event->naddr * 2; i++) { 130 dprintf("configure range %d, address %lx\n", 131 i, event->addr[i]); 132 bus_write_8(sc->res, TRCACVR(i), event->addr[i]); 133 134 reg = 0; 135 /* Secure state */ 136 reg |= TRCACATR_EXLEVEL_S_M; 137 reg &= ~TRCACATR_EXLEVEL_S(event->excp_level); 138 /* Non-secure state */ 139 reg |= TRCACATR_EXLEVEL_NS_M; 140 reg &= ~TRCACATR_EXLEVEL_NS(event->excp_level); 141 bus_write_4(sc->res, TRCACATR(i), reg); 142 143 /* Address range is included */ 144 reg = bus_read_4(sc->res, TRCVIIECTLR); 145 reg |= (1 << (TRCVIIECTLR_INCLUDE_S + i / 2)); 146 bus_write_4(sc->res, TRCVIIECTLR, reg); 147 } 148 149 /* No address filtering for ViewData. */ 150 bus_write_4(sc->res, TRCVDARCCTLR, 0); 151 152 /* Clear the STATUS bit to zero */ 153 bus_write_4(sc->res, TRCSSCSR(0), 0); 154 155 if (event->naddr == 0) { 156 /* No address range filtering for ViewInst. */ 157 bus_write_4(sc->res, TRCVIIECTLR, 0); 158 } 159 160 /* No start or stop points for ViewInst. */ 161 bus_write_4(sc->res, TRCVISSCTLR, 0); 162 163 /* Disable ViewData */ 164 bus_write_4(sc->res, TRCVDCTLR, 0); 165 166 /* No address filtering for ViewData. */ 167 bus_write_4(sc->res, TRCVDSACCTLR, 0); 168 169 return (0); 170 } 171 172 static int 173 etm_init(device_t dev) 174 { 175 struct etm_softc *sc; 176 uint32_t reg; 177 178 sc = device_get_softc(dev); 179 180 /* Unlocking Coresight */ 181 bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK); 182 183 /* Unlocking ETM */ 184 bus_write_4(sc->res, TRCOSLAR, 0); 185 186 reg = bus_read_4(sc->res, TRCIDR(1)); 187 dprintf("ETM Version: %d.%d\n", 188 (reg & TRCIDR1_TRCARCHMAJ_M) >> TRCIDR1_TRCARCHMAJ_S, 189 (reg & TRCIDR1_TRCARCHMIN_M) >> TRCIDR1_TRCARCHMIN_S); 190 191 return (0); 192 } 193 194 static int 195 etm_enable(device_t dev, struct endpoint *endp, 196 struct coresight_event *event) 197 { 198 struct etm_softc *sc; 199 uint32_t reg; 200 201 sc = device_get_softc(dev); 202 203 etm_prepare(dev, event); 204 205 /* Enable the trace unit */ 206 bus_write_4(sc->res, TRCPRGCTLR, TRCPRGCTLR_EN); 207 208 /* Wait for an IDLE bit to be LOW */ 209 do { 210 reg = bus_read_4(sc->res, TRCSTATR); 211 } while ((reg & TRCSTATR_IDLE) == 1); 212 213 if ((bus_read_4(sc->res, TRCPRGCTLR) & TRCPRGCTLR_EN) == 0) 214 panic("etm is not enabled\n"); 215 216 return (0); 217 } 218 219 static void 220 etm_disable(device_t dev, struct endpoint *endp, 221 struct coresight_event *event) 222 { 223 struct etm_softc *sc; 224 uint32_t reg; 225 226 sc = device_get_softc(dev); 227 228 /* Disable the trace unit */ 229 bus_write_4(sc->res, TRCPRGCTLR, 0); 230 231 /* Wait for an IDLE bit */ 232 do { 233 reg = bus_read_4(sc->res, TRCSTATR); 234 } while ((reg & TRCSTATR_IDLE) == 0); 235 } 236 237 int 238 etm_attach(device_t dev) 239 { 240 struct coresight_desc desc; 241 struct etm_softc *sc; 242 243 sc = device_get_softc(dev); 244 245 if (bus_alloc_resources(dev, etm_spec, &sc->res) != 0) { 246 device_printf(dev, "cannot allocate resources for device\n"); 247 return (ENXIO); 248 } 249 250 desc.pdata = sc->pdata; 251 desc.dev = dev; 252 desc.dev_type = CORESIGHT_ETMV4; 253 coresight_register(&desc); 254 255 return (0); 256 } 257 258 static device_method_t etm_methods[] = { 259 /* Coresight interface */ 260 DEVMETHOD(coresight_init, etm_init), 261 DEVMETHOD(coresight_enable, etm_enable), 262 DEVMETHOD(coresight_disable, etm_disable), 263 DEVMETHOD_END 264 }; 265 266 DEFINE_CLASS_0(etm, etm_driver, etm_methods, sizeof(struct etm_softc)); 267