1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 37 #include <dev/extres/clk/clk.h> 38 39 #include <arm64/freescale/imx/clk/imx_clk_sscg_pll.h> 40 41 #include "clkdev_if.h" 42 43 struct imx_clk_sscg_pll_sc { 44 uint32_t offset; 45 }; 46 47 #define WRITE4(_clk, off, val) \ 48 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) 49 #define READ4(_clk, off, val) \ 50 CLKDEV_READ_4(clknode_get_device(_clk), off, val) 51 #define DEVICE_LOCK(_clk) \ 52 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) 53 #define DEVICE_UNLOCK(_clk) \ 54 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) 55 56 #define CFG0 0x00 57 #define CFG0_PLL_LOCK (1 << 31) 58 #define CFG0_PD (1 << 7) 59 #define CFG0_BYPASS2 (1 << 5) 60 #define CFG0_BYPASS1 (1 << 4) 61 #define CFG1 0x04 62 #define CFG2 0x08 63 #define CFG2_DIVR1_MASK (7 << 25) 64 #define CFG2_DIVR1_SHIFT 25 65 #define CFG2_DIVR2_MASK (0x3f << 19) 66 #define CFG2_DIVR2_SHIFT 19 67 #define CFG2_DIVF1_MASK (0x3f << 13) 68 #define CFG2_DIVF1_SHIFT 13 69 #define CFG2_DIVF2_MASK (0x3f << 7) 70 #define CFG2_DIVF2_SHIFT 7 71 #define CFG2_DIV_MASK (0x3f << 1) 72 #define CFG2_DIV_SHIFT 1 73 74 #if 0 75 #define dprintf(format, arg...) \ 76 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) 77 #else 78 #define dprintf(format, arg...) 79 #endif 80 81 static int 82 imx_clk_sscg_pll_init(struct clknode *clk, device_t dev) 83 { 84 if (clknode_get_parents_num(clk) > 1) { 85 device_printf(clknode_get_device(clk), 86 "error: SSCG PLL does not support more than one parent yet\n"); 87 return (EINVAL); 88 } 89 clknode_init_parent_idx(clk, 0); 90 91 return (0); 92 } 93 94 static int 95 imx_clk_sscg_pll_set_gate(struct clknode *clk, bool enable) 96 { 97 struct imx_clk_sscg_pll_sc *sc; 98 uint32_t cfg0; 99 int timeout; 100 101 sc = clknode_get_softc(clk); 102 103 DEVICE_LOCK(clk); 104 READ4(clk, sc->offset + CFG0, &cfg0); 105 if (enable) 106 cfg0 &= ~(CFG0_PD); 107 else 108 cfg0 |= CFG0_PD; 109 WRITE4(clk, sc->offset + CFG0, cfg0); 110 111 /* Reading lock */ 112 if (enable) { 113 for (timeout = 1000; timeout; timeout--) { 114 READ4(clk, sc->offset + CFG0, &cfg0); 115 if (cfg0 & CFG0_PLL_LOCK) 116 break; 117 DELAY(1); 118 } 119 } 120 121 DEVICE_UNLOCK(clk); 122 123 return (0); 124 } 125 126 static int 127 imx_clk_sscg_pll_recalc(struct clknode *clk, uint64_t *freq) 128 { 129 struct imx_clk_sscg_pll_sc *sc; 130 uint32_t cfg0, cfg2; 131 int divr1, divr2, divf1, divf2, div; 132 133 sc = clknode_get_softc(clk); 134 135 DEVICE_LOCK(clk); 136 READ4(clk, sc->offset + CFG0, &cfg0); 137 READ4(clk, sc->offset + CFG2, &cfg2); 138 DEVICE_UNLOCK(clk); 139 140 /* PLL is bypassed */ 141 if (cfg0 & CFG0_BYPASS2) 142 return (0); 143 144 divr1 = (cfg2 & CFG2_DIVR1_MASK) >> CFG2_DIVR1_SHIFT; 145 divr2 = (cfg2 & CFG2_DIVR2_MASK) >> CFG2_DIVR2_SHIFT; 146 divf1 = (cfg2 & CFG2_DIVF1_MASK) >> CFG2_DIVF1_SHIFT; 147 divf2 = (cfg2 & CFG2_DIVF2_MASK) >> CFG2_DIVF2_SHIFT; 148 div = (cfg2 & CFG2_DIV_MASK) >> CFG2_DIV_SHIFT; 149 150 if (cfg0 & CFG0_BYPASS1) { 151 *freq = *freq / ((divr2 + 1) * (div + 1)); 152 return (0); 153 } 154 155 *freq *= 2 * (divf1 + 1) * (divf2 + 1); 156 *freq /= (divr1 + 1) * (divr2 + 1) * (div + 1); 157 158 return (0); 159 } 160 161 static clknode_method_t imx_clk_sscg_pll_clknode_methods[] = { 162 /* Device interface */ 163 CLKNODEMETHOD(clknode_init, imx_clk_sscg_pll_init), 164 CLKNODEMETHOD(clknode_set_gate, imx_clk_sscg_pll_set_gate), 165 CLKNODEMETHOD(clknode_recalc_freq, imx_clk_sscg_pll_recalc), 166 CLKNODEMETHOD_END 167 }; 168 169 DEFINE_CLASS_1(imx_clk_sscg_pll_clknode, imx_clk_sscg_pll_clknode_class, 170 imx_clk_sscg_pll_clknode_methods, sizeof(struct imx_clk_sscg_pll_sc), 171 clknode_class); 172 173 int 174 imx_clk_sscg_pll_register(struct clkdom *clkdom, 175 struct imx_clk_sscg_pll_def *clkdef) 176 { 177 struct clknode *clk; 178 struct imx_clk_sscg_pll_sc *sc; 179 180 clk = clknode_create(clkdom, &imx_clk_sscg_pll_clknode_class, 181 &clkdef->clkdef); 182 if (clk == NULL) 183 return (1); 184 185 sc = clknode_get_softc(clk); 186 187 sc->offset = clkdef->offset; 188 189 clknode_register(clkdom, clk); 190 191 return (0); 192 } 193