1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/rman.h> 37 #include <sys/proc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 41 #include <machine/bus.h> 42 #include <machine/intr.h> 43 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include "pic_if.h" 49 50 struct imx7gpc_softc { 51 device_t dev; 52 struct resource *memres; 53 device_t parent; 54 }; 55 56 static struct ofw_compat_data compat_data[] = { 57 { "fsl,imx7gpc", 1}, 58 { "fsl,imx8mq-gpc", 1}, 59 { NULL, 0} 60 }; 61 62 static inline uint32_t 63 imx7gpc_read_4(struct imx7gpc_softc *sc, int reg) 64 { 65 66 return (bus_read_4(sc->memres, reg)); 67 } 68 69 static inline void 70 imx7gpc_write_4(struct imx7gpc_softc *sc, int reg, uint32_t val) 71 { 72 73 bus_write_4(sc->memres, reg, val); 74 } 75 76 static int 77 imx7gpc_activate_intr(device_t dev, struct intr_irqsrc *isrc, 78 struct resource *res, struct intr_map_data *data) 79 { 80 struct imx7gpc_softc *sc = device_get_softc(dev); 81 82 return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data)); 83 } 84 85 static void 86 imx7gpc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 87 { 88 struct imx7gpc_softc *sc = device_get_softc(dev); 89 90 PIC_DISABLE_INTR(sc->parent, isrc); 91 } 92 93 static void 94 imx7gpc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 95 { 96 struct imx7gpc_softc *sc = device_get_softc(dev); 97 98 PIC_ENABLE_INTR(sc->parent, isrc); 99 } 100 101 static int 102 imx7gpc_map_intr(device_t dev, struct intr_map_data *data, 103 struct intr_irqsrc **isrcp) 104 { 105 struct imx7gpc_softc *sc = device_get_softc(dev); 106 107 return (PIC_MAP_INTR(sc->parent, data, isrcp)); 108 } 109 110 static int 111 imx7gpc_deactivate_intr(device_t dev, struct intr_irqsrc *isrc, 112 struct resource *res, struct intr_map_data *data) 113 { 114 struct imx7gpc_softc *sc = device_get_softc(dev); 115 116 return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data)); 117 } 118 119 static int 120 imx7gpc_setup_intr(device_t dev, struct intr_irqsrc *isrc, 121 struct resource *res, struct intr_map_data *data) 122 { 123 struct imx7gpc_softc *sc = device_get_softc(dev); 124 125 return (PIC_SETUP_INTR(sc->parent, isrc, res, data)); 126 } 127 128 static int 129 imx7gpc_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 130 struct resource *res, struct intr_map_data *data) 131 { 132 struct imx7gpc_softc *sc = device_get_softc(dev); 133 134 return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data)); 135 } 136 137 static void 138 imx7gpc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 139 { 140 struct imx7gpc_softc *sc = device_get_softc(dev); 141 142 PIC_PRE_ITHREAD(sc->parent, isrc); 143 } 144 145 static void 146 imx7gpc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 147 { 148 struct imx7gpc_softc *sc = device_get_softc(dev); 149 150 PIC_POST_ITHREAD(sc->parent, isrc); 151 } 152 153 static void 154 imx7gpc_post_filter(device_t dev, struct intr_irqsrc *isrc) 155 { 156 struct imx7gpc_softc *sc = device_get_softc(dev); 157 158 PIC_POST_FILTER(sc->parent, isrc); 159 } 160 161 #ifdef SMP 162 static int 163 imx7gpc_bind_intr(device_t dev, struct intr_irqsrc *isrc) 164 { 165 struct imx7gpc_softc *sc = device_get_softc(dev); 166 167 return (PIC_BIND_INTR(sc->parent, isrc)); 168 } 169 #endif 170 171 static int 172 imx7gpc_probe(device_t dev) 173 { 174 175 if (!ofw_bus_status_okay(dev)) 176 return (ENXIO); 177 178 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 179 return (ENXIO); 180 181 device_set_desc(dev, "General Power Controller"); 182 return (BUS_PROBE_DEFAULT); 183 } 184 185 static int 186 imx7gpc_attach(device_t dev) 187 { 188 struct imx7gpc_softc *sc = device_get_softc(dev); 189 phandle_t node; 190 phandle_t parent_xref; 191 int i, rv; 192 193 sc->dev = dev; 194 195 node = ofw_bus_get_node(dev); 196 197 rv = OF_getencprop(node, "interrupt-parent", &parent_xref, 198 sizeof(parent_xref)); 199 if (rv <= 0) { 200 device_printf(dev, "Can't read parent node property\n"); 201 return (ENXIO); 202 } 203 sc->parent = OF_device_from_xref(parent_xref); 204 if (sc->parent == NULL) { 205 device_printf(dev, "Can't find parent controller\n"); 206 return (ENXIO); 207 } 208 209 i = 0; 210 sc->memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, 211 RF_ACTIVE); 212 if (sc->memres == NULL) { 213 device_printf(dev, "could not allocate resources\n"); 214 return (ENXIO); 215 } 216 217 /* TODO: power up OTG domain and unmask all interrupts */ 218 219 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { 220 bus_release_resource(dev, SYS_RES_MEMORY, i, sc->memres); 221 device_printf(dev, "Cannot register PIC\n"); 222 return (ENXIO); 223 } 224 225 return (0); 226 } 227 228 static device_method_t imx7gpc_methods[] = { 229 DEVMETHOD(device_probe, imx7gpc_probe), 230 DEVMETHOD(device_attach, imx7gpc_attach), 231 232 /* Interrupt controller interface */ 233 DEVMETHOD(pic_activate_intr, imx7gpc_activate_intr), 234 DEVMETHOD(pic_disable_intr, imx7gpc_disable_intr), 235 DEVMETHOD(pic_enable_intr, imx7gpc_enable_intr), 236 DEVMETHOD(pic_map_intr, imx7gpc_map_intr), 237 DEVMETHOD(pic_deactivate_intr, imx7gpc_deactivate_intr), 238 DEVMETHOD(pic_setup_intr, imx7gpc_setup_intr), 239 DEVMETHOD(pic_teardown_intr, imx7gpc_teardown_intr), 240 DEVMETHOD(pic_pre_ithread, imx7gpc_pre_ithread), 241 DEVMETHOD(pic_post_ithread, imx7gpc_post_ithread), 242 DEVMETHOD(pic_post_filter, imx7gpc_post_filter), 243 #ifdef SMP 244 DEVMETHOD(pic_bind_intr, imx7gpc_bind_intr), 245 #endif 246 247 DEVMETHOD_END 248 }; 249 250 static driver_t imx7gpc_driver = { 251 "imx7gpc", 252 imx7gpc_methods, 253 sizeof(struct imx7gpc_softc), 254 }; 255 256 static devclass_t imx7gpc_devclass; 257 258 EARLY_DRIVER_MODULE(imx7gpc, ofwbus, imx7gpc_driver, imx7gpc_devclass, 0, 0, 259 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 260 EARLY_DRIVER_MODULE(imx7gpc, simplebus, imx7gpc_driver, imx7gpc_devclass, 0, 0, 261 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 262