1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _MACHINE_ARMREG_H_ 34 #define _MACHINE_ARMREG_H_ 35 36 #define INSN_SIZE 4 37 38 #define READ_SPECIALREG(reg) \ 39 ({ uint64_t val; \ 40 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ 41 val; \ 42 }) 43 #define WRITE_SPECIALREG(reg, val) \ 44 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) 45 46 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 47 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 48 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 49 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 50 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 51 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 52 53 /* CPACR_EL1 */ 54 #define CPACR_FPEN_MASK (0x3 << 20) 55 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 56 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 57 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 58 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 59 #define CPACR_TTA (0x1 << 28) 60 61 /* CTR_EL0 - Cache Type Register */ 62 #define CTR_DLINE_SHIFT 16 63 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 64 #define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 65 #define CTR_ILINE_SHIFT 0 66 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 67 #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 68 69 /* ESR_ELx */ 70 #define ESR_ELx_ISS_MASK 0x00ffffff 71 #define ISS_INSN_FnV (0x01 << 10) 72 #define ISS_INSN_EA (0x01 << 9) 73 #define ISS_INSN_S1PTW (0x01 << 7) 74 #define ISS_INSN_IFSC_MASK (0x1f << 0) 75 #define ISS_DATA_ISV (0x01 << 24) 76 #define ISS_DATA_SAS_MASK (0x03 << 22) 77 #define ISS_DATA_SSE (0x01 << 21) 78 #define ISS_DATA_SRT_MASK (0x1f << 16) 79 #define ISS_DATA_SF (0x01 << 15) 80 #define ISS_DATA_AR (0x01 << 14) 81 #define ISS_DATA_FnV (0x01 << 10) 82 #define ISS_DATa_EA (0x01 << 9) 83 #define ISS_DATa_CM (0x01 << 8) 84 #define ISS_INSN_S1PTW (0x01 << 7) 85 #define ISS_DATa_WnR (0x01 << 6) 86 #define ISS_DATA_DFSC_MASK (0x1f << 0) 87 #define ESR_ELx_IL (0x01 << 25) 88 #define ESR_ELx_EC_SHIFT 26 89 #define ESR_ELx_EC_MASK (0x3f << 26) 90 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 91 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 92 #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 93 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 94 #define EXCP_SVC 0x15 /* SVC trap */ 95 #define EXCP_MSR 0x18 /* MSR/MRS trap */ 96 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 97 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 98 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 99 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 100 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 101 #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 102 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 103 #define EXCP_SERROR 0x2f /* SError interrupt */ 104 #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 105 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 106 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 107 #define EXCP_BRK 0x3c /* Breakpoint */ 108 109 /* ICC_CTLR_EL1 */ 110 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 111 112 /* ICC_IAR1_EL1 */ 113 #define ICC_IAR1_EL1_SPUR (0x03ff) 114 115 /* ICC_IGRPEN0_EL1 */ 116 #define ICC_IGRPEN0_EL1_EN (1U << 0) 117 118 /* ICC_PMR_EL1 */ 119 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 120 121 /* ICC_SGI1R_EL1 */ 122 #define ICC_SGI1R_EL1_TL_MASK 0xffffUL 123 #define ICC_SGI1R_EL1_AFF1_SHIFT 16 124 #define ICC_SGI1R_EL1_SGIID_SHIFT 24 125 #define ICC_SGI1R_EL1_AFF2_SHIFT 32 126 #define ICC_SGI1R_EL1_AFF3_SHIFT 48 127 #define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 128 #define ICC_SGI1R_EL1_IRM (0x1UL << 40) 129 130 /* ICC_SRE_EL1 */ 131 #define ICC_SRE_EL1_SRE (1U << 0) 132 133 /* ICC_SRE_EL2 */ 134 #define ICC_SRE_EL2_SRE (1U << 0) 135 #define ICC_SRE_EL2_EN (1U << 3) 136 137 /* ID_AA64DFR0_EL1 */ 138 #define ID_AA64DFR0_MASK 0xf0f0ffff 139 #define ID_AA64DFR0_DEBUG_VER_SHIFT 0 140 #define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) 141 #define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) 142 #define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) 143 #define ID_AA64DFR0_TRACE_VER_SHIFT 4 144 #define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) 145 #define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) 146 #define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT) 147 #define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT) 148 #define ID_AA64DFR0_PMU_VER_SHIFT 8 149 #define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 150 #define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) 151 #define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT) 152 #define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT) 153 #define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 154 #define ID_AA64DFR0_BRPS_SHIFT 12 155 #define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT) 156 #define ID_AA64DFR0_BRPS(x) \ 157 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) 158 #define ID_AA64DFR0_WRPS_SHIFT 20 159 #define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT) 160 #define ID_AA64DFR0_WRPS(x) \ 161 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) 162 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 163 #define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT) 164 #define ID_AA64DFR0_CTX_CMPS(x) \ 165 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) 166 167 /* ID_AA64ISAR0_EL1 */ 168 #define ID_AA64ISAR0_MASK 0x000ffff0 169 #define ID_AA64ISAR0_AES_SHIFT 4 170 #define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT) 171 #define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 172 #define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT) 173 #define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT) 174 #define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT) 175 #define ID_AA64ISAR0_SHA1_SHIFT 8 176 #define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT) 177 #define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 178 #define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT) 179 #define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT) 180 #define ID_AA64ISAR0_SHA2_SHIFT 12 181 #define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT) 182 #define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 183 #define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT) 184 #define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT) 185 #define ID_AA64ISAR0_CRC32_SHIFT 16 186 #define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT) 187 #define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 188 #define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT) 189 #define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT) 190 191 /* ID_AA64MMFR0_EL1 */ 192 #define ID_AA64MMFR0_MASK 0xffffffff 193 #define ID_AA64MMFR0_PA_RANGE_SHIFT 0 194 #define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT) 195 #define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) 196 #define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT) 197 #define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT) 198 #define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT) 199 #define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT) 200 #define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT) 201 #define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT) 202 #define ID_AA64MMFR0_ASID_BITS_SHIFT 4 203 #define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT) 204 #define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) 205 #define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT) 206 #define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT) 207 #define ID_AA64MMFR0_BIGEND_SHIFT 8 208 #define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT) 209 #define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) 210 #define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT) 211 #define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT) 212 #define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 213 #define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT) 214 #define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) 215 #define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 216 #define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 217 #define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 218 #define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 219 #define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) 220 #define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 221 #define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 222 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 223 #define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT) 224 #define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) 225 #define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT) 226 #define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT) 227 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 228 #define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 229 #define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) 230 #define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT) 231 #define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 232 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 233 #define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 234 #define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) 235 #define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT) 236 #define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 237 238 /* ID_AA64PFR0_EL1 */ 239 #define ID_AA64PFR0_MASK 0x0fffffff 240 #define ID_AA64PFR0_EL0_SHIFT 0 241 #define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT) 242 #define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 243 #define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT) 244 #define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT) 245 #define ID_AA64PFR0_EL1_SHIFT 4 246 #define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT) 247 #define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 248 #define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT) 249 #define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT) 250 #define ID_AA64PFR0_EL2_SHIFT 8 251 #define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT) 252 #define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 253 #define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT) 254 #define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT) 255 #define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT) 256 #define ID_AA64PFR0_EL3_SHIFT 12 257 #define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT) 258 #define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 259 #define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT) 260 #define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT) 261 #define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT) 262 #define ID_AA64PFR0_FP_SHIFT 16 263 #define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT) 264 #define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 265 #define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT) 266 #define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT) 267 #define ID_AA64PFR0_ADV_SIMD_SHIFT 20 268 #define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 269 #define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) 270 #define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT) 271 #define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 272 #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 273 #define ID_AA64PFR0_GIC_SHIFT 24 274 #define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT) 275 #define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 276 #define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT) 277 #define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) 278 279 /* MAIR_EL1 - Memory Attribute Indirection Register */ 280 #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 281 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 282 283 /* SCTLR_EL1 - System Control Register */ 284 #define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */ 285 #define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */ 286 287 #define SCTLR_M 0x00000001 288 #define SCTLR_A 0x00000002 289 #define SCTLR_C 0x00000004 290 #define SCTLR_SA 0x00000008 291 #define SCTLR_SA0 0x00000010 292 #define SCTLR_CP15BEN 0x00000020 293 #define SCTLR_THEE 0x00000040 294 #define SCTLR_ITD 0x00000080 295 #define SCTLR_SED 0x00000100 296 #define SCTLR_UMA 0x00000200 297 #define SCTLR_I 0x00001000 298 #define SCTLR_DZE 0x00004000 299 #define SCTLR_UCT 0x00008000 300 #define SCTLR_nTWI 0x00010000 301 #define SCTLR_nTWE 0x00040000 302 #define SCTLR_WXN 0x00080000 303 #define SCTLR_EOE 0x01000000 304 #define SCTLR_EE 0x02000000 305 #define SCTLR_UCI 0x04000000 306 307 /* SPSR_EL1 */ 308 /* 309 * When the exception is taken in AArch64: 310 * M[4] is 0 for AArch64 mode 311 * M[3:2] is the exception level 312 * M[1] is unused 313 * M[0] is the SP select: 314 * 0: always SP0 315 * 1: current ELs SP 316 */ 317 #define PSR_M_EL0t 0x00000000 318 #define PSR_M_EL1t 0x00000004 319 #define PSR_M_EL1h 0x00000005 320 #define PSR_M_EL2t 0x00000008 321 #define PSR_M_EL2h 0x00000009 322 #define PSR_M_MASK 0x0000001f 323 324 #define PSR_F 0x00000040 325 #define PSR_I 0x00000080 326 #define PSR_A 0x00000100 327 #define PSR_D 0x00000200 328 #define PSR_IL 0x00100000 329 #define PSR_SS 0x00200000 330 #define PSR_V 0x10000000 331 #define PSR_C 0x20000000 332 #define PSR_Z 0x40000000 333 #define PSR_N 0x80000000 334 335 /* TCR_EL1 - Translation Control Register */ 336 #define TCR_ASID_16 (1 << 36) 337 338 #define TCR_IPS_SHIFT 32 339 #define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT) 340 #define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT) 341 #define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT) 342 #define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT) 343 #define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT) 344 #define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT) 345 346 #define TCR_TG1_SHIFT 30 347 #define TCR_TG1_16K (1 << TCR_TG1_SHIFT) 348 #define TCR_TG1_4K (2 << TCR_TG1_SHIFT) 349 #define TCR_TG1_64K (3 << TCR_TG1_SHIFT) 350 351 #define TCR_SH1_SHIFT 28 352 #define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 353 #define TCR_ORGN1_SHIFT 26 354 #define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 355 #define TCR_IRGN1_SHIFT 24 356 #define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 357 #define TCR_SH0_SHIFT 12 358 #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 359 #define TCR_ORGN0_SHIFT 10 360 #define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 361 #define TCR_IRGN0_SHIFT 8 362 #define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 363 364 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 365 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 366 367 #ifdef SMP 368 #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 369 #else 370 #define TCR_SMP_ATTRS 0 371 #endif 372 373 #define TCR_T1SZ_SHIFT 16 374 #define TCR_T0SZ_SHIFT 0 375 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 376 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 377 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 378 379 /* Saved Program Status Register */ 380 #define DBG_SPSR_SS (0x1 << 21) 381 382 /* Monitor Debug System Control Register */ 383 #define DBG_MDSCR_SS (0x1 << 0) 384 #define DBG_MDSCR_KDE (0x1 << 13) 385 #define DBG_MDSCR_MDE (0x1 << 15) 386 387 /* Perfomance Monitoring Counters */ 388 #define PMCR_E (1 << 0) /* Enable all counters */ 389 #define PMCR_P (1 << 1) /* Reset all counters */ 390 #define PMCR_C (1 << 2) /* Clock counter reset */ 391 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 392 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 393 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 394 #define PMCR_LC (1 << 6) /* Long cycle count enable */ 395 #define PMCR_IMP_SHIFT 24 /* Implementer code */ 396 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 397 #define PMCR_IDCODE_SHIFT 16 /* Identification code */ 398 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 399 #define PMCR_IDCODE_CORTEX_A57 0x01 400 #define PMCR_IDCODE_CORTEX_A72 0x02 401 #define PMCR_IDCODE_CORTEX_A53 0x03 402 #define PMCR_N_SHIFT 11 /* Number of counters implemented */ 403 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 404 405 #endif /* !_MACHINE_ARMREG_H_ */ 406